CN103246616A - Global shared cache replacement method for realizing long-short cycle access frequency - Google Patents
Global shared cache replacement method for realizing long-short cycle access frequency Download PDFInfo
- Publication number
- CN103246616A CN103246616A CN2013101954277A CN201310195427A CN103246616A CN 103246616 A CN103246616 A CN 103246616A CN 2013101954277 A CN2013101954277 A CN 2013101954277A CN 201310195427 A CN201310195427 A CN 201310195427A CN 103246616 A CN103246616 A CN 103246616A
- Authority
- CN
- China
- Prior art keywords
- data
- long
- buffer
- term
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a global shared cache replacement method for realizing long-short cycle access frequency. A host accesses data in two access modes including long-term cycle access and short-term frequent access, long-term cycle access indicates that a data block is cyclically and repeatedly accessed in long interval time, but a traditional replacement strategy based on aging cannot recognize the type of data access, and consequently, a cache completely fails when coping with long-term cycle access. In order to solve the technical problem, the global shared cache replacement method for realizing the long-short cycle access frequency includes a mapping manager module, a cache replacement module, a cache distribution module, a mirror image processing module and a cache consistency processing module.
Description
Technical field
The present invention relates to computer application field, specifically a kind of overall shared buffer memory replacement method of access frequency within long and short cycle.
Background technology
Digital information on the network is explosive increase, to the year two thousand twenty, the global metadata amount will enlarge 50 times, data have presented at a high speed simultaneously, multifarious characteristics, data diversity mainly is owing to novel many structured datas, and comprises that data types such as network log, social medium, internet hunt, mobile phone call history and sensor network cause.The quantity of host side also presents the growth of progression level simultaneously, different host side is far different at aspects such as response time, transmission bandwidth, transmission granularities to the I/O processing demands, be accompanied by the generation of these demands, multi-control disk array arises at the historic moment, it is core that multi-control disk array adopts with the global buffer, the architecture that interconnects by the cross matrix switch between controller, buffer unit.Buffer unit is independent physical unit, by the Crossbar exchange link realization of redundancy and clog-free, the high band wide data transmission of each controller.All buffer units are formed overall shared buffer memory, and to all controllers as seen, and each controller has the control of equality to it.Overall situation shared buffer memory is as the core component of multi-control disk array, and how it being managed optimization will become one of system performance critical bottleneck to satisfy different business demands.
Summary of the invention
The overall shared buffer memory replacement method that the purpose of this invention is to provide a kind of access frequency within long and short cycle.
The objective of the invention is to realize in the following manner, block-based visiting frequency value is come page or leaf is replaced, long period and short-period type of data access have been taken into account simultaneously, improved cache hit rate effectively, system comprises the map manager module, buffer memory replacement processing module, buffer memory allocation process module, mirror image processing module and five modules of cache consistance processing module, wherein:
The map manager module, be used for the mapping in local internal memory and shared virtual memory address space, its function be with local memory-mapped in the global sharing memory address space and keep the consistance of data;
The buffer memory replacement processing moduleThe replacement that is used for overall shared buffer memory is handled, in the mapping process of address, if the page of finding to visit in the page is not in internal memory, then produce the interruption of skipping leaf, operating system must select a page that it is shifted out internal memory at internal memory when interrupting when skipping leaf, in order to be that the page that is about to call in is abdicated the space;
Buffer memory allocation process module, use the two-stage memory management scheme, use the mode of multistage page table to carry out address translation, even as far as possible for the distribution that makes the communal space, the distribution of system's shared drive is to adopt the mode of cycle assignment to carry out;
The mirror image processing module, be used in order to prevent that single node lost efficacy, when reading and writing data, data are written to two independently in the region of memory simultaneously, prevented that effectively arbitrary node is owing to chance failure causes loss of data in the buffer memory;
Cache consistance processing moduleBased on the implementation of catalogue guarantee the to unite unanimity of a plurality of copies of same data in a plurality of nodes, it keeps a directory entry for each page or leaf in the internal memory, this directory entry records all the current node of this journey copy and status informations of data block held, comprise whether being write, whether monopolized still by a plurality of nodes sharing by certain node, when a node desire is write number and may be caused that data are inconsistent toward a certain, it just only sends the consistance that makes invalid or update signal keep data to those nodes of the backup of holding this journey according to the content of catalogue, and concrete steps are as follows:
1) to be organized into be a global buffer pond to all buffer units, buffer unit because the reason of fault or upgrading leave or add cache pool, system adopts the cache resources discovery mechanism, realize seamless increase or reduce the global buffer capacity, guarantee that stores service can not be subjected to the influence of resource change, buffer unit is initiatively declared oneself availability of buffer memory partly or completely by periodic broadcasting resource assert message, new buffer unit adds fashionable to all controllers, after receiving, buffer unit broadcast resource assert message, controller namely this element is added in the available cache memory resource index;
2) overall shared buffer memory has three kinds of operational modes, it is respectively normal mode, degraded mode and straight WriteMode, the buffer unit redundancy scheme adopts the state-detection mechanism of the software and hardware combining in the multi-controller redundancy scheme to realize, in order to improve reliability, will be only after certain buffer unit lost efficacy take over its buffer memory service by the high forward direction node in available of annular, cache pool enters degraded mode simultaneously, in normal mode and degraded mode, the global buffer pond is adopted and is write back pattern the data cached back-end physical disk that writes, and tolerates that at synchronization arbitrary buffer unit breaks down; Under the extreme case, during buffer unit operation of system's residue, overall shared buffer memory will be taked the straight WriteMode of data, and under the straight WriteMode, the buffer unit fault can not have any influence to data integrality and consistance;
3) buffer unit comprises logical address mapping mechanism and long-distance inner access protocal equally, realize logical address mapping and data communication with the cache client module, buffer unit is divided into the index area, three parts of data field and MIRROR SITE, the index area is used for carrying out reflection and the conversion of data, preserve all data field pages of this buffer unit, the index of the MIRROR SITE page, the read-write cache data of stores service are deposited in the data field, MIRROR SITE is deposited the mirror image data that other controllers send over, and the index data of other buffer units, realize reading and writing data, the full mirror image of index data;
4) host side has two kinds of access modes to data: long-term cycle access and short-term are frequently visited, long-term cycle access refers to data block periodic repeated accesses of quilt in the long at interval time, application comprises daily record, timed backup, the frequent visit of short-term refers to that data block is accessed frequently in the short period of time, be the maximization cache hit rate, should preserve the data that short-term is accessed frequently in the global buffer as far as possible, but if the data of the frequent visit of short-term do not obtain visit always, they also should be prior to the data of long-term cycle access and are replaced out global buffer so, this just need take into account the visit situation of long-term and short-term, research is replaced based on the global buffer of shot and long term visiting frequency and is handled, increase the data access frequency value of 4 bytes for the data block of global buffer, data block visiting frequency value each byte from high to low, represented the interval in the cycle from short to long, the accessed situation of data block, use Bn[i] the expression value of n byte i position from high to low, if in unit interval T, data block is accessed, then put B0[0] be 1, otherwise put B0[0] be 0, every the 8a*T time, adopt following Policy Updates data block visiting frequency value:
Ba[i+1]=Ba[i]?(i=0,1,……,6)
Ba+1[i+1]=Ba+1[i]?(i=0,1,……,6)
Ba+1[0]=Ba[0]?||?Ba[1]?||?…?…?||?Ba[6]?||?Ba[7]
Top rule guarantees, if access module is long-term cycle access, it is 1 continuously that multidigit will be arranged in the low byte so, if access module is that short-term is frequently visited, it is 1 continuously that multidigit will be arranged in the upper byte so, is 1 situation continuously and multidigit seldom can appear in low byte;
When 5) replacing data in the global buffer, all select replacing of data block visiting frequency value minimum at every turn, this is because the data of the frequent visit of short-term have bigger visiting frequency value, but it is not if accessed in long one period, the data access frequency value of the frequent visit of short-term will be gradually less than the data of long-term cycle access, can guarantee to preserve in the global buffer data of the frequent visit of short-term so as far as possible, but if not accessed in long one period, they will be replaced prior to long-term cycle access data.
The invention has the beneficial effects as follows: host side mainly contains two kinds of access modes to data: long-term cycle access and short-term are frequently visited, long-term cycle access refers to data block periodic repeated accesses of quilt in the long at interval time, and the traditional data access that can not identify this type based on the burin-in process replacement policy, buffer memory complete failure when causing being buffered in this type of visit of reply, in order to solve the problems of the technologies described above, the invention provides a kind of overall shared buffer memory replacement method that realizes access frequency within long and short cycle.
Description of drawings
Fig. 1 is data access frequency value synoptic diagram;
Fig. 2 is overall shared buffer memory pond topological diagram.
Embodiment
Below in conjunction with accompanying drawing and example technical scheme of the present invention is at length set forth.
Host side mainly contains two kinds of access modes to data: long-term cycle access and short-term are frequently visited, long-term cycle access refers to data block periodic repeated accesses of quilt in the long at interval time, and traditional can not identify the data access of this type, buffer memory complete failure when causing being buffered in this type of visit of reply based on the burin-in process replacement policy.
In order to solve the problems of the technologies described above, the invention provides a kind of overall shared buffer memory replacement method that realizes access frequency within long and short cycle, comprise map manager, buffer memory is replaced and is handled, the buffer memory allocation process, mirror image processing and cache consistance are handled five modules, wherein:
Map manager module, memory-mapped manager have realized the mapping in local internal memory and shared virtual memory address space, its function be with local memory-mapped in the global sharing memory address space and keep the consistance of data.
The buffer memory replacement processing module, the replacement that is used for overall shared buffer memory is handled, in the mapping process of address, if the page of finding to visit in the page not in internal memory, then produces the interruption of skipping leaf.Operating system must select a page that it is shifted out internal memory at internal memory when interrupting when skipping leaf, so that for the page that is about to call in is abdicated the space, this replacement is handled based on type of data access, the data of frequent visit of identification long period data and short period, and strategy carries out the buffer memory replacement according to this.
The buffer memory allocation process is used the two-stage memory management scheme, uses the mode of multistage page table to carry out address translation.Even as far as possible for the distribution that makes the communal space, the distribution of system's shared drive is to adopt the mode of cycle assignment to carry out.
The mirror image processing module is used in order to prevent that single node lost efficacy, and when reading and writing data, data is written to two independently in the region of memory simultaneously, has prevented that effectively arbitrary node is owing to chance failure causes loss of data in the buffer memory.
Cache consistance processing module, based on the implementation of catalogue guarantee the to unite unanimity of a plurality of copies of same data in a plurality of nodes, it keeps a directory entry for each page or leaf in the internal memory, this directory entry records all the current node of this journey copy and status informations of data block (as whether being write, being monopolized by certain node still is by a plurality of nodes sharing etc.) held.When node was desired to write number and may cause that data are inconsistent toward a certain, it just can send the consistance that makes invalid or update signal keep data according to content those nodes to the backup of holding this journey of catalogue.
It is a global buffer pond that all buffer units are organized into.Buffer unit is because reasons such as fault or upgrading are left or added cache pool, and system adopts the cache resources discovery mechanism, realizes seamless increase or reduces the global buffer capacity, guarantees that stores service can not be subjected to the influence of resource change.Buffer unit is initiatively declared oneself availability of buffer memory partly or completely by periodic broadcasting resource assert message.New buffer unit adds fashionable to all controllers, buffer unit broadcast resource assert message, namely this element is added in the available cache memory resource index after controller is received.
Overall situation shared buffer memory has three kinds of operational modes, is respectively normal mode, degraded mode and straight WriteMode.The buffer unit redundancy scheme adopts the state-detection mechanism of the software and hardware combining in the multi-controller redundancy scheme to realize.In order to improve reliability, will be only after certain buffer unit lost efficacy take over its buffer memory service by the high forward direction node in available of annular, cache pool enters degraded mode simultaneously.In normal mode and degraded mode, the global buffer pond is adopted and is write back pattern the data cached back-end physical disk that writes, and can tolerate that at synchronization arbitrary buffer unit breaks down; Under the extreme case, during buffer unit operation of system's residue, overall shared buffer memory will be taked the straight WriteMode of data.Under the straight WriteMode, the buffer unit fault can not have any influence to data integrality and consistance.
Buffer unit comprises logical address mapping mechanism and long-distance inner access protocal equally, realizes logical address mapping and data communication with the cache client module.Buffer unit is divided into index area, data field and three parts of MIRROR SITE.The index area is used for carrying out reflection and the conversion of data, preserves the index of all data field pages of this buffer unit, the MIRROR SITE page.The read-write cache data of stores service are deposited in the data field.MIRROR SITE is deposited the mirror image data that other controllers send over, and the index data of other buffer units, and realization reads and writes data, the full mirror image of index data.
Host side mainly contains two kinds of access modes to data: long-term cycle access and short-term are frequently visited.Long-term cycle access refers to data block periodic repeated accesses of quilt in the long at interval time, and the typical case uses and comprises daily record, timed backup etc.The frequent visit of short-term refers to that data block is accessed frequently in the short period of time.For the maximization cache hit rate, should preserve the data that short-term is accessed frequently in the global buffer, but if the data of the frequent visit of short-term do not obtain visit always as far as possible, they also should be replaced out global buffer prior to the data of long-term cycle access so.This just need take into account the visit situation of long-term and short-term, and research is replaced based on the global buffer of shot and long term visiting frequency and handled.For the data block of global buffer increases the data access frequency value of 4 bytes,
Data block visiting frequency value each byte has from high to low represented the interval in the cycle from short to long, the accessed situation of data block.Use Bn[i] represent the value of n byte i position from high to low, if in unit interval T, data block is accessed, then puts B0[0] be 1, otherwise put B0[0] be 0.Every the 8a*T time, adopt following Policy Updates data block visiting frequency value:
Ba[i+1]=Ba[i]?(i=0,1,……,6)
Ba+1[i+1]=Ba+1[i]?(i=0,1,……,6)
Ba+1[0]=Ba[0]?||?Ba[1]?||?…?…?||?Ba[6]?||?Ba[7]
Top rule can guarantee, if access module is long-term cycle access, it is 1 continuously that multidigit will be arranged in the low byte so, if access module is that short-term is frequently visited, it is 1 continuously that multidigit will be arranged in the upper byte so, is 1 situation continuously and multidigit seldom can appear in low byte.
When replacing the data in the global buffer, all select replacing of data block visiting frequency value minimum at every turn.This is because the data of the frequent visit of short-term have bigger visiting frequency value, but if not accessed in long one period, the data access frequency value of the frequent visit of short-term will be gradually less than the data of long-term cycle access.Can guarantee to preserve in the global buffer data of the frequent visit of short-term like this, but if not accessed in long one period, they will be replaced prior to long-term cycle access data as far as possible.
Except the described technical characterictic of instructions, be the known technology of those skilled in the art.
Claims (1)
1. the overall shared buffer memory replacement method of an access frequency within long and short cycle, it is characterized in that, block-based visiting frequency value is come page or leaf is replaced, taken into account long period and short-period type of data access simultaneously, improved cache hit rate effectively, system comprises the map manager module, the buffer memory replacement processing module, buffer memory allocation process module, mirror image processing module and five modules of cache consistance processing module, wherein:
The map manager module, be used for the mapping in local internal memory and shared virtual memory address space, its function be with local memory-mapped in the global sharing memory address space and keep the consistance of data;
The buffer memory replacement processing moduleThe replacement that is used for overall shared buffer memory is handled, in the mapping process of address, if the page of finding to visit in the page is not in internal memory, then produce the interruption of skipping leaf, operating system must select a page that it is shifted out internal memory at internal memory when interrupting when skipping leaf, in order to be that the page that is about to call in is abdicated the space;
Buffer memory allocation process module, use the two-stage memory management scheme, use the mode of multistage page table to carry out address translation, even as far as possible for the distribution that makes the communal space, the distribution of system's shared drive is to adopt the mode of cycle assignment to carry out;
The mirror image processing module, be used in order to prevent that single node lost efficacy, when reading and writing data, data are written to two independently in the region of memory simultaneously, prevented that effectively arbitrary node is owing to chance failure causes loss of data in the buffer memory;
Cache consistance processing moduleBased on the implementation of catalogue guarantee the to unite unanimity of a plurality of copies of same data in a plurality of nodes, it keeps a directory entry for each page or leaf in the internal memory, this directory entry records all the current node of this journey copy and status informations of data block held, comprise whether being write, whether monopolized still by a plurality of nodes sharing by certain node, when a node desire is write number and may be caused that data are inconsistent toward a certain, it just only sends the consistance that makes invalid or update signal keep data to those nodes of the backup of holding this journey according to the content of catalogue, and concrete steps are as follows:
1) to be organized into be a global buffer pond to all buffer units, buffer unit because the reason of fault or upgrading leave or add cache pool, system adopts the cache resources discovery mechanism, realize seamless increase or reduce the global buffer capacity, guarantee that stores service can not be subjected to the influence of resource change, buffer unit is initiatively declared oneself availability of buffer memory partly or completely by periodic broadcasting resource assert message, new buffer unit adds fashionable to all controllers, after receiving, buffer unit broadcast resource assert message, controller namely this element is added in the available cache memory resource index;
2) overall shared buffer memory has three kinds of operational modes, it is respectively normal mode, degraded mode and straight WriteMode, the buffer unit redundancy scheme adopts the state-detection mechanism of the software and hardware combining in the multi-controller redundancy scheme to realize, in order to improve reliability, will be only after certain buffer unit lost efficacy take over its buffer memory service by the high forward direction node in available of annular, cache pool enters degraded mode simultaneously, in normal mode and degraded mode, the global buffer pond is adopted and is write back pattern the data cached back-end physical disk that writes, and tolerates that at synchronization arbitrary buffer unit breaks down; Under the extreme case, during buffer unit operation of system's residue, overall shared buffer memory will be taked the straight WriteMode of data, and under the straight WriteMode, the buffer unit fault can not have any influence to data integrality and consistance;
3) buffer unit comprises logical address mapping mechanism and long-distance inner access protocal equally, realize logical address mapping and data communication with the cache client module, buffer unit is divided into the index area, three parts of data field and MIRROR SITE, the index area is used for carrying out reflection and the conversion of data, preserve all data field pages of this buffer unit, the index of the MIRROR SITE page, the read-write cache data of stores service are deposited in the data field, MIRROR SITE is deposited the mirror image data that other controllers send over, and the index data of other buffer units, realize reading and writing data, the full mirror image of index data;
4) host side has two kinds of access modes to data: long-term cycle access and short-term are frequently visited, long-term cycle access refers to data block periodic repeated accesses of quilt in the long at interval time, application comprises daily record, timed backup, the frequent visit of short-term refers to that data block is accessed frequently in the short period of time, be the maximization cache hit rate, should preserve the data that short-term is accessed frequently in the global buffer as far as possible, but if the data of the frequent visit of short-term do not obtain visit always, they also should be prior to the data of long-term cycle access and are replaced out global buffer so, this just need take into account the visit situation of long-term and short-term, research is replaced based on the global buffer of shot and long term visiting frequency and is handled, increase the data access frequency value of 4 bytes for the data block of global buffer, data block visiting frequency value each byte from high to low, represented the interval in the cycle from short to long, the accessed situation of data block, use Bn[i] the expression value of n byte i position from high to low, if in unit interval T, data block is accessed, then put B0[0] be 1, otherwise put B0[0] be 0, every the 8a*T time, adopt following Policy Updates data block visiting frequency value:
Ba[i+1]=Ba[i]?(i=0,1,……,6)
Ba+1[i+1]=Ba+1[i]?(i=0,1,……,6)
Ba+1[0]=Ba[0]?||?Ba[1]?||?…?…?||?Ba[6]?||?Ba[7]
Top rule guarantees, if access module is long-term cycle access, it is 1 continuously that multidigit will be arranged in the low byte so, if access module is that short-term is frequently visited, it is 1 continuously that multidigit will be arranged in the upper byte so, is 1 situation continuously and multidigit seldom can appear in low byte;
When 5) replacing data in the global buffer, all select replacing of data block visiting frequency value minimum at every turn, this is because the data of the frequent visit of short-term have bigger visiting frequency value, but it is not if accessed in long one period, the data access frequency value of the frequent visit of short-term will be gradually less than the data of long-term cycle access, can guarantee to preserve in the global buffer data of the frequent visit of short-term so as far as possible, but if not accessed in long one period, they will be replaced prior to long-term cycle access data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310195427.7A CN103246616B (en) | 2013-05-24 | 2013-05-24 | A kind of globally shared buffer replacing method of access frequency within long and short cycle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310195427.7A CN103246616B (en) | 2013-05-24 | 2013-05-24 | A kind of globally shared buffer replacing method of access frequency within long and short cycle |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103246616A true CN103246616A (en) | 2013-08-14 |
| CN103246616B CN103246616B (en) | 2017-09-26 |
Family
ID=48926144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310195427.7A Active CN103246616B (en) | 2013-05-24 | 2013-05-24 | A kind of globally shared buffer replacing method of access frequency within long and short cycle |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103246616B (en) |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104268101A (en) * | 2014-09-22 | 2015-01-07 | 无锡城市云计算中心有限公司 | Storage space allocation method and device |
| CN104331352A (en) * | 2014-11-19 | 2015-02-04 | 浪潮(北京)电子信息产业有限公司 | Out-of-band reading detection method and out-of-band reading detection device for cache consistency chip address |
| CN104461935A (en) * | 2014-11-27 | 2015-03-25 | 华为技术有限公司 | Method, device and system for data storage |
| CN106201919A (en) * | 2015-06-01 | 2016-12-07 | Arm 有限公司 | Buffer consistency |
| WO2017117734A1 (en) * | 2016-01-06 | 2017-07-13 | 华为技术有限公司 | Cache management method, cache controller and computer system |
| CN107111569A (en) * | 2014-12-19 | 2017-08-29 | 联发科技股份有限公司 | Support the EMS memory management process and correlation machine computer-readable recording medium of shared virtual memory used with mixing page table |
| CN107291635A (en) * | 2017-06-16 | 2017-10-24 | 郑州云海信息技术有限公司 | A kind of buffer replacing method and device |
| CN107329696A (en) * | 2017-06-23 | 2017-11-07 | 华中科技大学 | A kind of method and system for ensureing data corruption uniformity |
| CN107810490A (en) * | 2015-06-18 | 2018-03-16 | 华为技术有限公司 | System and method for the buffer consistency based on catalogue |
| CN109376022A (en) * | 2018-09-29 | 2019-02-22 | 中国科学技术大学 | It is a kind of promoted Halide language multiple nucleus system execution efficiency threading model implementation method |
| CN109582895A (en) * | 2018-12-04 | 2019-04-05 | 山东浪潮通软信息科技有限公司 | A kind of cache implementing method |
| CN110750507A (en) * | 2019-09-30 | 2020-02-04 | 华中科技大学 | Client persistent caching method and system under global namespace facing DFS |
| CN111158578A (en) * | 2018-11-08 | 2020-05-15 | 浙江宇视科技有限公司 | Storage space management method and device |
| CN111273860A (en) * | 2020-01-15 | 2020-06-12 | 华东师范大学 | Distributed memory management method based on network and page granularity management |
| CN112612727A (en) * | 2020-12-08 | 2021-04-06 | 海光信息技术股份有限公司 | Cache line replacement method and device and electronic equipment |
| WO2022021158A1 (en) * | 2020-07-29 | 2022-02-03 | 华为技术有限公司 | Cache system, method and chip |
| CN115374046A (en) * | 2022-10-21 | 2022-11-22 | 山东云海国创云计算装备产业创新中心有限公司 | Multiprocessor data interaction method, device, equipment and storage medium |
| CN117032596A (en) * | 2023-10-09 | 2023-11-10 | 苏州元脑智能科技有限公司 | Data access method and device, storage medium and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060112237A1 (en) * | 2004-11-19 | 2006-05-25 | Intel Corporation | Software caching with bounded-error delayed update |
| CN1996944A (en) * | 2006-11-09 | 2007-07-11 | 华中科技大学 | A method for global buffer management of the cluster storage system |
| CN101609432A (en) * | 2009-07-13 | 2009-12-23 | 中国科学院计算技术研究所 | Shared buffer memory management system and method |
| CN102262512A (en) * | 2011-07-21 | 2011-11-30 | 浪潮(北京)电子信息产业有限公司 | System, device and method for realizing disk array cache partition management |
| CN102609362A (en) * | 2012-01-30 | 2012-07-25 | 复旦大学 | Method for dynamically dividing shared high-speed caches and circuit |
-
2013
- 2013-05-24 CN CN201310195427.7A patent/CN103246616B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060112237A1 (en) * | 2004-11-19 | 2006-05-25 | Intel Corporation | Software caching with bounded-error delayed update |
| CN1996944A (en) * | 2006-11-09 | 2007-07-11 | 华中科技大学 | A method for global buffer management of the cluster storage system |
| CN101609432A (en) * | 2009-07-13 | 2009-12-23 | 中国科学院计算技术研究所 | Shared buffer memory management system and method |
| CN102262512A (en) * | 2011-07-21 | 2011-11-30 | 浪潮(北京)电子信息产业有限公司 | System, device and method for realizing disk array cache partition management |
| CN102609362A (en) * | 2012-01-30 | 2012-07-25 | 复旦大学 | Method for dynamically dividing shared high-speed caches and circuit |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104268101A (en) * | 2014-09-22 | 2015-01-07 | 无锡城市云计算中心有限公司 | Storage space allocation method and device |
| CN104268101B (en) * | 2014-09-22 | 2017-12-05 | 无锡城市云计算中心有限公司 | A kind of memory allocation method and device |
| CN104331352A (en) * | 2014-11-19 | 2015-02-04 | 浪潮(北京)电子信息产业有限公司 | Out-of-band reading detection method and out-of-band reading detection device for cache consistency chip address |
| CN104331352B (en) * | 2014-11-19 | 2018-03-09 | 浪潮(北京)电子信息产业有限公司 | Detection method and device are read outside cache uniformity chip address band |
| CN104461935A (en) * | 2014-11-27 | 2015-03-25 | 华为技术有限公司 | Method, device and system for data storage |
| CN104461935B (en) * | 2014-11-27 | 2018-03-13 | 华为技术有限公司 | A kind of method, apparatus and system for carrying out data storage |
| CN107111569A (en) * | 2014-12-19 | 2017-08-29 | 联发科技股份有限公司 | Support the EMS memory management process and correlation machine computer-readable recording medium of shared virtual memory used with mixing page table |
| CN106201919A (en) * | 2015-06-01 | 2016-12-07 | Arm 有限公司 | Buffer consistency |
| CN106201919B (en) * | 2015-06-01 | 2021-10-29 | Arm 有限公司 | Cache coherency |
| CN107810490A (en) * | 2015-06-18 | 2018-03-16 | 华为技术有限公司 | System and method for the buffer consistency based on catalogue |
| US10831677B2 (en) | 2016-01-06 | 2020-11-10 | Huawei Technologies Co., Ltd. | Cache management method, cache controller, and computer system |
| WO2017117734A1 (en) * | 2016-01-06 | 2017-07-13 | 华为技术有限公司 | Cache management method, cache controller and computer system |
| CN107291635A (en) * | 2017-06-16 | 2017-10-24 | 郑州云海信息技术有限公司 | A kind of buffer replacing method and device |
| CN107329696A (en) * | 2017-06-23 | 2017-11-07 | 华中科技大学 | A kind of method and system for ensureing data corruption uniformity |
| CN107329696B (en) * | 2017-06-23 | 2019-05-14 | 华中科技大学 | A kind of method and system guaranteeing data corruption consistency |
| CN109376022A (en) * | 2018-09-29 | 2019-02-22 | 中国科学技术大学 | It is a kind of promoted Halide language multiple nucleus system execution efficiency threading model implementation method |
| CN111158578A (en) * | 2018-11-08 | 2020-05-15 | 浙江宇视科技有限公司 | Storage space management method and device |
| CN109582895A (en) * | 2018-12-04 | 2019-04-05 | 山东浪潮通软信息科技有限公司 | A kind of cache implementing method |
| CN110750507A (en) * | 2019-09-30 | 2020-02-04 | 华中科技大学 | Client persistent caching method and system under global namespace facing DFS |
| CN110750507B (en) * | 2019-09-30 | 2022-09-20 | 华中科技大学 | Persistent client caching method and system under global namespace facing DFS |
| CN111273860B (en) * | 2020-01-15 | 2022-07-08 | 华东师范大学 | Distributed memory management method based on network and page granularity management |
| CN111273860A (en) * | 2020-01-15 | 2020-06-12 | 华东师范大学 | Distributed memory management method based on network and page granularity management |
| WO2022021158A1 (en) * | 2020-07-29 | 2022-02-03 | 华为技术有限公司 | Cache system, method and chip |
| CN112612727A (en) * | 2020-12-08 | 2021-04-06 | 海光信息技术股份有限公司 | Cache line replacement method and device and electronic equipment |
| CN115374046A (en) * | 2022-10-21 | 2022-11-22 | 山东云海国创云计算装备产业创新中心有限公司 | Multiprocessor data interaction method, device, equipment and storage medium |
| CN117032596A (en) * | 2023-10-09 | 2023-11-10 | 苏州元脑智能科技有限公司 | Data access method and device, storage medium and electronic equipment |
| CN117032596B (en) * | 2023-10-09 | 2024-01-26 | 苏州元脑智能科技有限公司 | Data access method and device, storage medium and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103246616B (en) | 2017-09-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103246616A (en) | Global shared cache replacement method for realizing long-short cycle access frequency | |
| CN103152395B (en) | A kind of storage means of distributed file system and device | |
| US10747746B2 (en) | Efficient read replicas | |
| CN107391391B (en) | Method, system and the solid state hard disk of data copy are realized in the FTL of solid state hard disk | |
| US9330108B2 (en) | Multi-site heat map management | |
| CN100481028C (en) | Method and device for implementing data storage using cache | |
| CN103067433B (en) | A kind of data migration method of distributed memory system, equipment and system | |
| CN107798130A (en) | A kind of Snapshot Method of distributed storage | |
| CN102117248A (en) | Caching system and method for caching data in caching system | |
| CN114860163B (en) | Storage system, memory management method and management node | |
| CN106446159B (en) | A kind of method of storage file, the first virtual machine and name node | |
| CN104111804A (en) | Distributed file system | |
| CN101916290B (en) | Managing method of internal memory database and device | |
| CN103037004A (en) | Implement method and device of cloud storage system operation | |
| CN105897859B (en) | Storage system | |
| CN109299056B (en) | A kind of method of data synchronization and device based on distributed file system | |
| CN103501319A (en) | Low-delay distributed storage system for small files | |
| US11080207B2 (en) | Caching framework for big-data engines in the cloud | |
| CN103516549B (en) | A kind of file system metadata log mechanism based on shared object storage | |
| US11128535B2 (en) | Computer system and data management method | |
| KR20170042593A (en) | Flushing in file system | |
| CN105159845A (en) | Memory reading method | |
| CN110196818A (en) | Data cached method, buffer memory device and storage system | |
| CN111159176A (en) | Method and system for storing and reading mass stream data | |
| US20220374407A1 (en) | Multi-tenant partitioning in a time-series database |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |