CN103227633A - High-speed-mode signal detection circuit - Google Patents
High-speed-mode signal detection circuit Download PDFInfo
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- CN103227633A CN103227633A CN2013101768339A CN201310176833A CN103227633A CN 103227633 A CN103227633 A CN 103227633A CN 2013101768339 A CN2013101768339 A CN 2013101768339A CN 201310176833 A CN201310176833 A CN 201310176833A CN 103227633 A CN103227633 A CN 103227633A
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- circuit
- mode signal
- stage circuit
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- signal deteching
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Abstract
The invention discloses a high-speed-mode signal detection circuit which is suitable for detecting USB (universal serial bus) 2.0 signals. The high-speed-mode signal detection circuit comprises a first-stage circuit, a second-stage circuit, a third-stage circuit, a forth-stage circuit and an amplitude limiting circuit, wherein the first-stage circuit, the second-stage circuit and the third-stage circuit are electrically connected, and the forth-stage circuit and the amplitude limiting circuit are respectively arranged below the first-stage circuit, the second-stage circuit and the third-stage circuit. Through the manner, the high-speed-mode signal detection circuit provided by the invention has the advantages of having a good resisting intersymbol interference effect and being capable of well detecting a lower-amplitude USB 2.0 signal, and meeting the worst USB 2.0 case condition.
Description
Technical field
The present invention relates to the CMOS(complementary metal oxide semiconductors (CMOS)) the integrated circuit (IC) design field, particularly relate to a kind of fast mode signal deteching circuit, be applicable to the input of USB2.0.
Background technology
(Squelch Detector) input of USB2.0 according to the agreement regulation, under worst case, needs can detect 30% duty ratio, the signal of 25mV.It is 1.6GHz that 30% duty ratio is equivalent to signal frequency, far above the data frequency of its 480MHz.1.6GHz signal, its ISI(Inter symbol Interference intersymbol interference) effect is very obvious.
Prior USB 2.0 signal deteching circuits, substantially all be at be 480MHz, anti-intersymbol interference effect is poor, so be difficult to satisfy the requirement of worst case.
Summary of the invention
The technical problem that the present invention mainly solves provides a kind of fast mode signal deteching circuit, solved the requirement that USB2.0 signal deteching circuit in the prior art can not satisfy the worst case of USB2.0 protocol definition.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: a kind of fast mode signal deteching circuit is provided, be applicable to the input of USB2.0, comprise first order circuit, second level circuit, tertiary circuit, fourth stage circuit and amplitude limiter circuit, described first order circuit, second level circuit and tertiary circuit electrically connect, and described fourth stage circuit and amplitude limiter circuit are separately positioned on the below of first order circuit, second level circuit and tertiary circuit.
In a preferred embodiment of the present invention, described first order circuit comprises three PMOS pipes and two resistance that series connection is provided with, and described two resistance are connected with earth terminal respectively.
In a preferred embodiment of the present invention, described second level circuit comprises three PMOS pipes that series connection is provided with, and described second level circuit is parallel between first order circuit and the tertiary circuit.
In a preferred embodiment of the present invention, described tertiary circuit comprises three PMOS pipes and two resistance that series connection is provided with, and described two resistance are connected with earth terminal respectively.
In a preferred embodiment of the present invention, described fourth stage circuit comprises five PMOS pipes that series connection is provided with, and wherein two PMOS pipes are connected with earth terminal respectively.
In a preferred embodiment of the present invention, described amplitude limiter circuit comprises NMOS pipe and the 2nd NMOS pipe that is connected in parallel.
The invention has the beneficial effects as follows: the present invention has the fast mode signal deteching circuit, be applicable to the input of USB2.0, in existing, increased amplitude limiter circuit on the basis of USB2.0 signal deteching circuit to reduce intersymbol interference, has anti-preferably intersymbol interference effect, thereby can be good at, detect the low amplitude signal of USB2.0, can satisfy the requirement of USB2.0 worst case.
Description of drawings
Fig. 1 is the circuit diagram of fast mode signal deteching circuit one preferred embodiment of the present invention;
Fig. 2 is the circuit diagram of USB2.0 signal deteching circuit in the prior art;
Mark in the accompanying drawing is as follows: M1, NMOS pipe, M2, the 2nd NMOS pipe.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present invention is described in detail, thereby protection scope of the present invention is made more explicit defining so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that.
See also Fig. 1, the invention provides a kind of fast mode signal deteching circuit, be applicable to the input of USB2.0, comprise first order circuit, second level circuit, tertiary circuit, fourth stage circuit and amplitude limiter circuit, described first order circuit, second level circuit and tertiary circuit electrically connect, and described fourth stage circuit and amplitude limiter circuit are separately positioned on the below of first order circuit, second level circuit and tertiary circuit.
Wherein, described first order circuit comprises three PMOS pipes and two resistance that series connection is provided with, and described two resistance are connected with earth terminal respectively; Described second level circuit comprises three PMOS pipes that series connection is provided with, and described second level circuit is parallel between first order circuit and the tertiary circuit; Described tertiary circuit comprises three PMOS pipes and two resistance that series connection is provided with, and described two resistance are connected with earth terminal respectively; Described fourth stage circuit comprises five PMOS pipes that series connection is provided with, and wherein two PMOS pipes are connected with earth terminal respectively; Described amplitude limiter circuit comprises NMOS pipe and M1 the 2nd NMOS pipe M2 that is connected in parallel.
In above-mentioned, first order circuit input reference voltage and earthed voltage, described second level circuit input difference voltage dp and dn, wherein, described reference voltage is 125mV; Earthed voltage is 0 mV; Tertiary circuit output diffpp and diffpn signal, described fourth stage circuit input diffpp and diffpn signal.
As shown in Figure 2, the circuit diagram of USB2.0 signal deteching circuit in the prior art.At first, first order circuit and second level electric circuit inspection go out dp and the dn differential voltage difference to reference voltage;
, wherein, a is a multiplication factor, i.e. gain;
Tertiary circuit amplifies V1-V1B, makes signal arrive certain amplitude,
Fourth stage circuit becomes single-ended output throttle signal to difference input, and its output level is 0 or supply voltage, can regard output as logical signal 0 or 1.
When input signal differential amplitude during, output 1 greater than 125mV, during less than 125mV, output 0;
When output signal frequency than higher the time, because the voltage amplitude of diffpp-diffpn without limits, the signal amplitude of low frequency can be amplified to very big, away from common mode electrical level, cause the signal of high frequency to have little time reaction like this, produce intersymbol interference, make and whether to detect input differential signal normally greater than 125mV.
As shown in Figure 1, in existing, increased amplitude limiter circuit on the basis of USB2.0 signal deteching circuit.NMOS pipe because the voltage amplitude of diffpp-diffpn is limited in the circuit and the restriction of M1 the 2nd NMOS pipe M2 clamper, the signal amplitude of low frequency can be very not big.High-frequency signal has enough time to react, and does not produce intersymbol interference, whether can detect input differential signal normally greater than 125mV.
The present invention discloses has the fast mode signal deteching circuit, be applicable to the input of USB2.0, in existing, increased amplitude limiter circuit on the basis of USB2.0 signal deteching circuit to reduce intersymbol interference, has anti-preferably intersymbol interference effect, thereby can be good at, detect the low amplitude signal of USB2.0, can satisfy the requirement of USB2.0 worst case.
The above only is embodiments of the invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes specification of the present invention and accompanying drawing content to be done; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (6)
1. fast mode signal deteching circuit, be applicable to the input of USB2.0, it is characterized in that, comprise first order circuit, second level circuit, tertiary circuit, fourth stage circuit and amplitude limiter circuit, described first order circuit, second level circuit and tertiary circuit electrically connect, and described fourth stage circuit and amplitude limiter circuit are separately positioned on the below of first order circuit, second level circuit and tertiary circuit.
2. fast mode signal deteching circuit according to claim 1 is characterized in that, described first order circuit comprises three PMOS pipes and two resistance that series connection is provided with, and described two resistance are connected with earth terminal respectively.
3. fast mode signal deteching circuit according to claim 1 is characterized in that, described second level circuit comprises three PMOS pipes that series connection is provided with, and described second level circuit is parallel between first order circuit and the tertiary circuit.
4. fast mode signal deteching circuit according to claim 1 is characterized in that, described tertiary circuit comprises three PMOS pipes and two resistance that series connection is provided with, and described two resistance are connected with earth terminal respectively.
5. fast mode signal deteching circuit according to claim 1 is characterized in that, described fourth stage circuit comprises five PMOS pipes that series connection is provided with, and wherein two PMOS pipes are connected with earth terminal respectively.
6. fast mode signal deteching circuit according to claim 1 is characterized in that, described amplitude limiter circuit comprises NMOS pipe and the 2nd NMOS pipe that is connected in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101768339A CN103227633A (en) | 2013-05-14 | 2013-05-14 | High-speed-mode signal detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101768339A CN103227633A (en) | 2013-05-14 | 2013-05-14 | High-speed-mode signal detection circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103227633A true CN103227633A (en) | 2013-07-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013101768339A Pending CN103227633A (en) | 2013-05-14 | 2013-05-14 | High-speed-mode signal detection circuit |
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| CN (1) | CN103227633A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103888110A (en) * | 2014-04-17 | 2014-06-25 | 苏州坤信微电子科技有限公司 | One-of-many selection circuit for RF local-oscillator signal |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868914A (en) * | 2007-09-27 | 2010-10-20 | 美商豪威科技股份有限公司 | Reduced voltage differential receiver |
| CN203289400U (en) * | 2013-05-14 | 2013-11-13 | 苏州文芯微电子科技有限公司 | High-speed mode signal detection circuit |
-
2013
- 2013-05-14 CN CN2013101768339A patent/CN103227633A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868914A (en) * | 2007-09-27 | 2010-10-20 | 美商豪威科技股份有限公司 | Reduced voltage differential receiver |
| CN203289400U (en) * | 2013-05-14 | 2013-11-13 | 苏州文芯微电子科技有限公司 | High-speed mode signal detection circuit |
Non-Patent Citations (1)
| Title |
|---|
| 陈雷: "用于低频小信号检测的CMOS放大器设计", 《现代电子技术》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103888110A (en) * | 2014-04-17 | 2014-06-25 | 苏州坤信微电子科技有限公司 | One-of-many selection circuit for RF local-oscillator signal |
| CN103888110B (en) * | 2014-04-17 | 2016-08-24 | 苏州坤信微电子科技有限公司 | Multiselect one circuit of RF local oscillator signal |
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Application publication date: 20130731 |