CN103199051B - Manufacture method of all-dielectric isolation silicon on insulator (SOI) material sheet for complementary bipolar process - Google Patents
Manufacture method of all-dielectric isolation silicon on insulator (SOI) material sheet for complementary bipolar process Download PDFInfo
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- CN103199051B CN103199051B CN201310110891.1A CN201310110891A CN103199051B CN 103199051 B CN103199051 B CN 103199051B CN 201310110891 A CN201310110891 A CN 201310110891A CN 103199051 B CN103199051 B CN 103199051B
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Abstract
A manufacture method of an all-dielectric isolation silicon on insulator (SOI) material sheet for a complementary bipolar process comprises of the steps of manufacturing an N-type buried layer and a P-type buried layer on a first monocrystalline wafer, performing deep-trench etching, sacrificial layer oxidation, trench resistor oxidation and deposition trench filling of polycrystalline silicon and corrugated metal pipe (CMP) polycrystalline silicon on the first monocrystalline wafer to form a dielectric isolation region; arranging a buried oxide layer on a second monocrystalline wafer; performing front silicon bonding of the first monocrystalline wafer with the formed dielectric isolation region and the second monocrystalline wafer with the formed buried oxide layer; and performing reduction and CMP finishing polish of a substrate on the side of the first monocrystalline wafer, and finally forming the all-dielectric isolation SOI material sheet for the complementary bipolar process. The manufacture method has the advantages of being low manufacture cost, few in active layer defects, good in active layer parameter consistency, free of figure drifting and the like, and can be widely applied to the manufacture field of the all-dielectric isolation complementary bipolar process.
Description
Technical field
The present invention relates to a kind of manufacture method of the Fully dielectric isolation SOI material piece for Complementary bipolar technology, be applied to the field of semiconductor manufacture of Complementary bipolar technology.
Background technology
Complementary bipolar technology is one of semiconductor fabrication process be most widely used, manufacture method for the conventional media isolation SOI material piece of Complementary bipolar technology is: on SOI sheet, first make n type buried layer and p type buried layer, and then grows N-type or P type epitaxial loayer makes.First, the quality of epitaxial loayer affects very large by the defect concentration of buried regions doping content and backing material self, easily occurs fault and sliding line, and delays buried regions figure outside and easily occur larger drift; Secondly, the autodoping effect in epitaxial process can cause in sheet and between sheet, epitaxy layer thickness and resistivity distribution there are differences, thus causes the circuit manufactured by material piece or device parameters discreteness large (as CE puncture voltage) that use the method to make; Again, the equipment cost of N-type extension or P type extension and process costs all higher.
Patent documentation 1 (the patent No.: 200910190948.7) " manufacture method of shallow junction complementary bipolar transistor ", propose and form SOI material piece by silicon/silicon bonding, attenuated polishing method, in SOI material piece, make Deep trench isolation by deep etching, polysilicon refilling again and add shallow divider wall, in conjunction with the Complementary bipolar technology of longitudinal NPN pipe with longitudinal P NP pipe compatibility with shallow junction polysilicon emitter, the shallow junction complementary bipolar transistor described in making.The SOI material piece that the method is produced is due to needs high-temperature technology, as the epitaxial growth of 1150 DEG C, therefore there is the defect such as fault and sliding line in it, and buried regions figure is delayed outside and easily occurred pattern drifting, makes epitaxial thickness and resistivity all there is larger difference between sheet He in sheet.
Patent documentation 2 (the patent No.: 200510052287.3) " manufacture method of high-voltage high-power low differential pressure linear integrated regulated power supply circuit ", propose the SOI sheet first utilized required for the acquisition of silicon/silicon bonding, attenuated polishing technical method, in SOI material piece, then carried out the manufacture of described high-voltage high-power low differential pressure linear integrated regulated power supply circuit by the medium isolation technology methods combining longitudinal P NP of deep etching, polysilicon refilling and the bipolar process of longitudinal NPN compatibility.The SOI material piece that the method makes owing to needing regrowth extension on the SOI sheet that bonding is good, its active layer exist fault and sliding line, active layer parameter consistency poor, delay the shortcomings such as pattern drifting outward, and its manufacture craft is more complicated, cost is higher.
Summary of the invention
In order to the SOI material piece active layer overcoming above-mentioned background fabrication techniques exists the problem that fault and sliding line, active layer parameter consistency are poor, delay pattern drifting outward, the present invention proposes a kind of manufacture method of the Fully dielectric isolation SOI material piece for Complementary bipolar technology, realize that cost of manufacture is low, active layer defect is few, active layer parameter consistency is good, without the object of the Fully dielectric isolation SOI material piece of pattern drifting.
To achieve these goals, the manufacture method of a kind of Fully dielectric isolation SOI material piece for Complementary bipolar technology of the present invention, it is characterized in that, the method step is:
(1) on monocrystalline silicon disk one, n type buried layer and p type buried layer is made;
(2) on the monocrystalline silicon disk one forming n type buried layer and p type buried layer, carry out deep etching, sacrifice layer is oxidized, ditch resistance is oxidized, groove polysilicon and CMP polysilicon are filled out in deposit, forms medium isolation;
(3) on monocrystalline silicon disk two, oxygen buried layer is grown;
(4) with the described monocrystalline silicon disk two forming oxygen buried layer, front Si-Si bonding is carried out to the described monocrystalline silicon disk one forming medium isolation, form SOI silicon materials sheet;
(5) on described SOI silicon materials sheet, thinning, CMP finishing polish is carried out to the substrate in its that face of monocrystalline silicon disk one, the described Fully dielectric isolation SOI material piece for Complementary bipolar technology of final formation.
The described step making n type buried layer and p type buried layer on monocrystalline silicon disk one is: carry out RCA cleaning to monocrystalline silicon disk one, makes the zero layer alignment mark of disk, and growth thin oxide layer, injects and form n type buried layer and p type buried layer, annealing.
The described monocrystalline silicon disk one forming n type buried layer and p type buried layer carries out deep etching, sacrifice layer is oxidized, ditch resistance oxidation, the step that groove polysilicon and CMP polysilicon are filled out in deposit is: make medium isolation channel district by lithography, dry etching silicon dioxide, dry etching silicon, form deep trouth, remove photoresist, RCA cleans, sacrifice layer is oxidized, 2:1HF floats sacrifice layer 30 seconds, RCA cleans, ditch resistance oxidation growth, groove polysilicon layer is filled out in the deposit of LPCVD technique, polysilicon layer thicknesses >=2 μm, fill out groove polysilicon cmp planarization, finally polysilicon surface is thrown into minute surface, form medium isolation.
The described step growing oxygen buried layer on monocrystalline silicon disk two is: carry out RCA cleaning to monocrystalline silicon disk two, oxidation, forms oxygen buried layer.
The step that the described described monocrystalline silicon disk one to forming medium isolation and the described monocrystalline silicon disk two having formed oxygen buried layer carry out front Si-Si bonding is: to monocrystalline silicon disk one and monocrystalline silicon disk two, RCA cleans, pre-bonding, checks whether to there is cavity, at O with infrared equipment
2or N
2environment in, through process at 1050 ± 10 DEG C in 3.5 ~ 4.5 hours, form silicon materials sheet SOI sheet.
Described on described SOI silicon materials sheet, carrying out step that is thinning, CMP finishing polish to the substrate in its that face of monocrystalline silicon disk one is: carry out RCA cleaning to SOI sheet, carry out thinning to that face of monocrystalline silicon disk one, reserved required active epitaxy layer thickness, its thickness is required by the difference of Complementary bipolar technology device parameters and determines, the detection of active epitaxy layer thickness, CMP finishing polish, reach minute surface, RCA cleans, detect the final thickness of silicon chip, the Fully dielectric isolation SOI material piece for Complementary bipolar technology described in final formation.
Beneficial effect
The manufacture method of the Fully dielectric isolation SOI material piece of a kind of Complementary bipolar technology of the present invention, has the following advantages:
1) due to the high temperature epitaxy technique of 1150 in common manufacturing method DEG C, the defect such as fault and sliding line of active epitaxial loayer can be brought, and manufacture method of the present invention does not adopt high temperature epitaxy technique, the SOI material piece produced has the few feature of active layer defect.
2) manufacture method of the present invention is before described SOI material piece completes, just complete the making of n type buried layer, p type buried layer and isolation channel, and active layer is single crystal silicon material, the therefore active layer parameter of the inventive method, the consistency as active layer thickness, resistivity is fine.
3) because the manufacture method of this material piece does not use expensive N-type epitaxial furnace or P type epitaxial furnace, compared with patent documentation 2, eliminate extension operation, therefore the inventive method has the advantage that technique is simple, cost of manufacture is low.
Table 1 is asked for an interview in the contrast of the some processes parameter of conventional Fully dielectric isolation SOI material piece process described in the inventive method and patent documentation 1, document 2.As can be seen from Table 1, the inventive method has that cost of manufacture is low, active layer defect is few, active layer parameter consistency is good, without advantages such as pattern driftings.
The contrast table of the some processes parameter of table 1 the inventive method and conventional Fully dielectric isolation SOI material piece manufacture method
Accompanying drawing explanation
Fig. 1 is that the present invention grows thin oxide layer on monocrystalline silicon disk one, forms the cross-sectional view after n type buried layer, p type buried layer;
Fig. 2 is the cross-sectional view of the present invention after completing deep etching window;
Fig. 3 is the cross-sectional view of the present invention after completing deep etching;
Fig. 4 is the cross-sectional view of the present invention after completing ditch resistance oxidation;
Fig. 5 be the present invention complete polysilicon fill out groove after cross-sectional view;
Fig. 6 is the cross-sectional view of the present invention after completing polysilicon cmp planarization;
Fig. 7 is the cross-sectional view after the present invention grows oxygen buried layer on monocrystalline silicon disk two;
Fig. 8 is the cross-sectional view of the present invention after completing monocrystalline silicon disk one and monocrystalline silicon disk two front bonding;
Fig. 9 is the cross-sectional view of the present invention's monocrystalline silicon disk one face down after completing bonding;
Figure 10 is the cross-sectional view of the Fully dielectric isolation SOI material piece for Complementary bipolar technology described in final formation of the present invention.
Wherein in Fig. 1 ~ 10: 1 represents P type or n type single crystal silicon disk; 2 represent n type buried layer; 3 represent p type buried layer; 4 represent thin oxide layer; 5 represent deep etching window; 6 represent deep trouth; 7 represent ditch resistance oxide layer; Groove polysilicon is filled out in 8 expressions; Polysilicon after 9 expression cmp planarizations; 10 represent N-type or p type single crystal silicon disk; 11 represent oxygen buried layer; 12 represent the active epitaxial loayer after being with deep trouth one side thinning.
Embodiment
Below in conjunction with drawings and Examples, the inventive method is further illustrated.Technical scheme of the present invention is not limited only to the description of the present embodiment.
The concrete making step of the present embodiment is as follows:
(1) on monocrystalline silicon disk one, n type buried layer 3 and p type buried layer 4 is made:
Monocrystalline silicon disk 1 is formed zero layer mark, and 950 DEG C of hot oxide growth thickness are the thin oxide layer 2 of 13.5 ~ 15.5nm, and make n type buried layer 3, p type buried layer 4,1050 DEG C annealing 55 minutes, as shown in Figure 1.
(2) on the silicon chip forming n type buried layer 3 and p type buried layer 4, carry out that deep trouth 6 etches, sacrifice layer oxidation, ditch resistance oxidation 7, deposit fill out groove polysilicon 8 and CMP polysilicon 9, form medium isolation:
First medium isolation channel district is carved at monocrystalline silicon disk 1 front lighting; Dry etching silicon dioxide, forms deep etching window 5, as shown in Figure 2;
Dry etching silicon, forms deep trouth 6, groove width >=1.6 μm, etching groove depth >=22 μm, as shown in Figure 3;
Remove photoresist; Cleaning (RCA cleaning); 850 DEG C of growth sacrificial oxide layer 27 ~ 33nm, 2:1HF floats sacrifice layer 30 seconds, cleaning (RCA cleaning); 1000 DEG C of growth thickness are the ditch resistance oxidation 7 of 220nm ~ 280nm, as shown in Figure 4;
Adopt the deposit of LPCVD method to fill out groove polysilicon 8, polysilicon thickness >=2 μm, the thickness of polysilicon depends on the degree of depth and the width of groove and the ability of Si-Si bonding equipment, as shown in Figure 5;
Fill out the planarization of groove polysilicon and adopt CMP mode, in order to ensure uniformity and the consistency of top silicon surface thickness after bonding, first rough polishing is carried out to polysilicon, and then carry out essence throwing, skim surface 2.0 ~ 3.5um polysilicon, surface is without residual polycrystalline silicon, and surface-brightening, to reach the surface requirements of Si-Si bonding, as shown in Figure 6.
(3) on monocrystalline silicon disk 2 10, oxygen buried layer 11 is grown:
Described monocrystalline silicon disk 2 10 is cleaned (RCA cleaning); 1050 DEG C of growth thickness are the oxygen buried layer 11 of 540 ~ 660nm, as shown in Figure 7.
(4) with the described monocrystalline silicon disk 2 10 forming oxygen buried layer, front Si-Si bonding is carried out to the described monocrystalline silicon disk 1 forming medium isolation, forms SOI silicon materials sheet:
Described monocrystalline silicon disk 1 and monocrystalline silicon disk 2 10 are cleaned (RCA cleaning); In pre-bonder, pre-bonding is carried out under room temperature; Check whether to there is cavity with infrared equipment after pre-bonding; After pre-bonding, at O
2or N
2environment in through 3.5 ~ 4.5 hours at 1050 ± 10 DEG C process after, form good bonding; Wafer bonding situation is checked with infrared equipment again, as shown in Figure 8 after high temperature bonding.
(5) on the described SOI silicon materials sheet of formation, thinning, CMP finishing polish is carried out to the substrate in its that face of monocrystalline silicon disk 1, reserved required active epitaxy layer thickness 12, the Fully dielectric isolation SOI material piece for Complementary bipolar technology described in final formation:
Complete the SOI material piece after high temperature bonding, the monocrystalline silicon disk 1 comprising n type buried layer and p type buried layer is faced up, as shown in Figure 9;
Carry out thinning to the back side in described that face of monocrystalline silicon disk 1, the thickness being reserved with active layer epitaxial loayer 12 after thinning is 22 μm, detect the thickness of active epitaxial loayer 12, the CMP finishing polish thickness of reserved 2 μm, its thickness is required by the difference of Complementary bipolar technology device parameters and determines; Silicon chip, after rough polishing and essence are thrown, reaches minute surface; RCA cleans; Detect the final thickness of silicon chip.The Fully dielectric isolation SOI material piece for Complementary bipolar technology described in final formation, as shown in Figure 10.
Process used in the inventive method, except being described in detail, other, as n type buried layer, p type buried layer, RCA cleaning, photoetching, remove photoresist, the oxidation of LPCVD deposit polycrystalline, sacrifice layer, burn into drift light, pre-bonding, high temperature bonding, thinning, finishing polish, process, equipment and chemical materials, the reagent such as cmp planarization is this area current techique, no longer describe in detail.
Claims (6)
1., for a manufacture method for the Fully dielectric isolation SOI material piece of Complementary bipolar technology, it is characterized in that, the method step is:
(1) on monocrystalline silicon disk one, n type buried layer and p type buried layer is made;
(2) on the monocrystalline silicon disk one forming n type buried layer and p type buried layer, carry out deep etching, sacrifice layer is oxidized, ditch resistance is oxidized, groove polysilicon and CMP polysilicon are filled out in deposit, forms medium isolation;
(3) on monocrystalline silicon disk two, oxygen buried layer is grown;
(4) with the described monocrystalline silicon disk two forming oxygen buried layer, front Si-Si bonding is carried out to the described monocrystalline silicon disk one forming medium isolation, form SOI silicon materials sheet;
(5) on described SOI silicon materials sheet, thinning, CMP finishing polish is carried out to the substrate in its that face of monocrystalline silicon disk one, the described Fully dielectric isolation SOI material piece for Complementary bipolar technology of final formation.
2. the manufacture method of the Fully dielectric isolation SOI material piece for Complementary bipolar technology according to claim 1, it is characterized in that: the described step making n type buried layer and p type buried layer on monocrystalline silicon disk one is: carry out RCA cleaning to monocrystalline silicon disk one, make the zero layer alignment mark of disk, growth thin oxide layer, inject and form n type buried layer and p type buried layer, annealing.
3. the manufacture method of the Fully dielectric isolation SOI material piece for Complementary bipolar technology according to claim 1, it is characterized in that: the described monocrystalline silicon disk one forming n type buried layer and p type buried layer carries out deep etching, sacrifice layer is oxidized, ditch resistance oxidation, the step that groove polysilicon and CMP polysilicon are filled out in deposit is: make medium isolation channel district by lithography, dry etching silicon dioxide, dry etching silicon, form deep trouth, remove photoresist, RCA cleans, sacrifice layer is oxidized, 2:1HF floats sacrifice layer 30 seconds, RCA cleans, ditch resistance oxidation growth, groove polysilicon layer is filled out in the deposit of LPCVD technique, polysilicon layer thicknesses >=2 μm, fill out groove polysilicon cmp planarization, finally polysilicon surface is thrown into minute surface, form medium isolation.
4. the manufacture method of the Fully dielectric isolation SOI material piece for Complementary bipolar technology according to claim 1, it is characterized in that: the described step growing oxygen buried layer on monocrystalline silicon disk two is: carry out RCA cleaning to monocrystalline silicon disk two, oxidation, forms oxygen buried layer.
5. the manufacture method of the Fully dielectric isolation SOI material piece for Complementary bipolar technology according to claim 1, it is characterized in that: the step that the described described monocrystalline silicon disk one to forming medium isolation and the described monocrystalline silicon disk two having formed oxygen buried layer carry out front Si-Si bonding is: to monocrystalline silicon disk one and monocrystalline silicon disk two, RCA cleans, pre-bonding, check whether to there is cavity, at O with infrared equipment
2or N
2environment in, through process at 1050 ± 10 DEG C in 3.5 ~ 4.5 hours, form silicon materials sheet SOI sheet.
6. the manufacture method of the Fully dielectric isolation SOI material piece for Complementary bipolar technology according to claim 1, it is characterized in that: described on described SOI silicon materials sheet, carry out thinning to the substrate in its that face of monocrystalline silicon disk one, the step of CMP finishing polish is: carry out RCA cleaning to SOI sheet, carry out thinning to that face of monocrystalline silicon disk one, reserved required active epitaxy layer thickness, its thickness is required by the difference of Complementary bipolar technology device parameters and determines, the detection of active epitaxy layer thickness, CMP finishing polish, reach minute surface, RCA cleans, detect the final thickness of silicon chip, the Fully dielectric isolation SOI material piece for Complementary bipolar technology described in final formation.
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| CN101673715B (en) * | 2009-09-25 | 2012-05-02 | 中国电子科技集团公司第二十四研究所 | Method for manufacturing shallow junction complementary bipolar transistor |
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