CN103149963A - Linear power circuit with high power supply rejection ratio - Google Patents

Abstract

The invention discloses a linear power circuit with a high power supply rejection ratio. In the linear power circuit, two biasing circuits, namely a biasing circuit a and a biasing circuit b, are adopted, during electrification, the biasing circuit b supplies a reference voltage and a reference current to an error amplifier, the power supply of the biasing circuit b is a system power supply VBAT, when the power supply is stabilized, the output VLDO of the linear power supply supplies power to the biasing circuit a, the biasing circuit b stops working at the moment, the biasing circuit a supplies the reference voltage and the reference current to the error amplifier, and because the stability of the VLDO is far higher than that of the power supply VBAT, the stability of the reference voltage and reference current generated by the biasing circuit a is far higher than that of the reference voltage and reference current generated by the biasing circuit b, so that the linear power circuit with high power supply rejection ratio is realized.

Description

A kind of linear power supply circuit of high PSRR

Technical field

The present invention relates generally to the design field of linear power supply circuit, refers in particular to a kind of linear power supply circuit of high PSRR.

Background technology

For Analogous Integrated Electronic Circuits, the quality of its performance depends on several factors, wherein the quality of power supply is also a key factor that affects the Analogous Integrated Electronic Circuits performance, some high-precision analog circuit particularly, as high-precision adc (ADC), high precision digital-to-analog converter (DAC), instrument amplifier etc., this class circuit all needs a high-quality Power supply usually, usually be all to adopt linear power supply (LDO), the major function one of LDO is to carry out voltage transitions, the 2nd, and the noise on filter out power.Power Supply Rejection Ratio is to weigh a key index of mimic channel, certainly be also a key index weighing LDO, what it characterized is the ability that the anti-power supply of LDO output disturbs, Power Supply Rejection Ratio is higher, its output is more stable, the performance of mimic channel is more guaranteed, and design a linear voltage regulator with high PSRR is a difficult point always.

Summary of the invention

The problem to be solved in the present invention just is: for the problem that prior art exists, propose a kind of linear power supply circuit of high PSRR.

The solution that the present invention proposes is: this circuit adopts two biasing circuits with mistake, i.e. biasing circuit a, and biasing circuit b provides reference voltage and reference current with biasing circuit b to error amplifier when powering on, and the power supply of biasing circuit b is system power supply V _BAT, after power supply is stable, with the output V of linear power supply _LDOGive biasing circuit a power supply, this moment, biasing circuit b quit work, provided reference voltage and reference current by biasing circuit a to error amplifier, due to V _LDOStability much larger than power supply V _BATSo, the reference voltage that the reference voltage that biasing circuit a produces and the stability of reference current produce far above biasing circuit b and the stability of reference current, thus realized a kind of linear power supply circuit of high PSRR.

Description of drawings

Fig. 1 is circuit theory schematic diagram of the present invention;

Embodiment

Below with reference to accompanying drawing and concrete enforcement, the present invention is described in further details.

As shown in Figure 1, biasing circuit a and biasing circuit b circuit structure are identical, and just power supply is distinguished to some extent, and the power supply of biasing circuit a is the output V of linear power supply _LDO, the power supply of biasing circuit b is system power supply V _BAT, when circuit powers on, V _LDOVoltage does not also establish, at this moment the bias voltage V of error amplifier EA _ref, bias current I _refB provides by biasing circuit, and biasing circuit a does not work.Work as V _BATRise gradually, V _LDOAlso can increase gradually, when increasing to certain value, biasing circuit a also starts working, at this moment the bias voltage V of EA _ref, bias current I _refProvided simultaneously by biasing circuit a, b, this moment, NMOS managed M _a5, M _b5Leakage current all pass through resistance R _PAnd R ₀, due to V _LDOIncrease gradually, so M _a5Leakage current also increase gradually, NMOS manages M _a9, M _b9Grid voltage increase gradually, due to NMOS pipe M _a9W/L much smaller than M _b9W/L, according to NMOS pipe saturation region leakage current expression formula

$I_{\mathrm{ds}}=\frac{1}{2}{\mathrm{\μ}}_n{c}_{\mathrm{ox}}\frac{W}{L}{(V_{\mathrm{gs}}-V_{\mathrm{th}})}^2(1+\mathrm{\λ}{V}_{\mathrm{ds}})---\left(1\right)$

Due to NMOS pipe M _a9, M _b9V _gsChange identical, but M _b9Leakage current I _dsAdded value is much larger than M _a9The added value of leakage current, due to the characteristic of MOS itself, in order to keep so large electric current, NMOS manages M _b9V _dsCan increase, i.e. M _b9Drain voltage can increase, when it increases to certain value, can make NMOS pipe M _b6V _gs＜V _th, i.e. M _b6By, biasing circuit b quits work, at this moment the bias voltage V of EA _ref, bias current I _refA provides by biasing circuit, and circuit powers on and completes.

After biasing circuit a work, flow through resistance R _PElectric current circuit parameter and the resistance R of biasing circuit a are arranged fully _PAnd R ₀Value determine, suppose that NMOS manages M _a5Leakage current be I _ds5, and hypothesis forms current mirror M _a5And M _a6W/L identical, M _a1And M _a2W/L identical, ignore NMOS pipe M _a9Channel modulation corresponding,

$I_{\mathrm{ds}5}=\frac{1}{2}{\mathrm{\μ}}_n{c}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_{\mathrm{Ma}9}\·{(I_{\mathrm{ds}5}\·R_0-V_{\mathrm{th}})}^2---\left(2\right)$

Suppose $\frac{1}{2}{\mathrm{\μ}}_n{c}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_{\mathrm{Ma}9}=\mathrm{\α},$

$I_{\mathrm{ds}5}=\frac{(2R_0{V}_{\mathrm{th}}+\frac{1}{\mathrm{\α}})+\sqrt{{(2R_0{V}_{\mathrm{th}}+\frac{1}{\mathrm{\α}})}^2-4R_0^2{V}_{\mathrm{th}}^2}}{2R_0^2}---\left(3\right)$

The reference voltage of EA

V _ref=I _ds5·(R ₀+R _P) (4)

The reference current I of EA _ref=I _ds5, according to amplifier characteristic V as can be known _F=V _ref, namely

$V_{\mathrm{LDO}}\·\frac{R_2}{R_1+R_2}=I_{\mathrm{ds}5}\·(R_0+R_P)---\left(5\right)$

Namely

$V_{\mathrm{LDO}}=(1+\frac{R_1}{R_2})\·(R_0+R_P)\·I_{\mathrm{ds}5}---\left(6\right)$

By formula (6) as can be known, the output voltage V of linear power supply _LDOCan be by changing variable resistor R _PValue regulate.

In sum, this circuit adopts two biasing circuits with crossing, i.e. biasing circuit a, and the mode that biasing circuit b works stage by stage makes after the circuit normal operation output V with linear power supply _LDOTo the offset generating circuit power supply, greatly improved the stability of bias voltage and the bias current of its generation, thereby greatly improved the final output V of linear power supply _LDOHave high Power Supply Rejection Ratio, thereby realized a kind of linear power supply circuit with high PSRR.

Claims (1)

1. the linear power supply circuit of a high PSRR is characterized in that:

By biasing circuit a, biasing circuit b, resistance R _P, resistance R ₀, resistance R ₁, resistance R ₂, capacitor C _C, error amplifier EA and power tube M _PForm; Biasing circuit a comprises PMOS pipe M _a1, PMOS manages M _a2, PMOS manages M _a3, PMOS manages M _a4, NMOS manages M _a5, NMOS manages M _a6, NMOS manages M _a7, NMOS manages M _a8, NMOS manages M _a9, resistance R _a1, resistance R _a2, the power supply of biasing circuit a is the output V of linear power supply _LDO, PMOS manages M _a1, M _a2, M _a3, M _a4And resistance R _a1An end be connected to V _LDO, resistance R _a1The other end be connected to NMOS pipe M _a7Grid and NMOS pipe M _a8Drain electrode, resistance R _a2One terminate to NMOS pipe M _a7Source electrode and NMOS pipe M _a8Grid, the other end is received ground, NMOS manages M _a8, M _a9Source ground, PMOS manages M _a4The grid leak short circuit and with PMOS pipe M _a3Grid be connected to form current-mirror structure, and be connected to NMOS pipe M _a7Drain electrode, NMOS manages M _a6The grid leak short circuit and with NMOS pipe M _a5Grid be connected to form current-mirror structure, and be connected to PMOS pipe M _a3Drain electrode, NMOS manages M _a5Source electrode be connected to resistance R _pAn end, resistance R _pThe other end be connected to resistance R ₀An end and NMOS pipe M _a9Grid, R ₀The other end receive, PMOS manages M _a2The grid leak short circuit and with PMOS pipe M _a1Grid be connected to form current-mirror structure, and be connected to NMOS pipe M _a5Drain electrode, PMOS manages M _a1Drain electrode be connected to I _refBiasing circuit b manages M by PMOS _b1, PMOS manages M _b2, PMOS manages M _b3, PMOS manages M _b4, NMOS manages M _b5, NMOS manages M _b6, NMOS manages M _b7, NMOS manages M _b8, NMOS manages M _b9, resistance R _b1, resistance R _b2Form, its power supply is system power supply V _BAT, the circuit structure of biasing circuit b and annexation and biasing circuit a are in full accord; The positive input terminal of error amplifier EA connects feedback voltage V _F, i.e. resistance R ₁And resistance R ₂An end, negative input end is connected to V _ref, its reference current is input as I _ref, the output of EA is connected to PMOS power tube M _PGrid, M _PSource electrode be connected to power supply V _BAT, drain electrode is connected to resistance R ₁And capacitor C _CAn end, resistance R ₂And capacitor C _COther end ground connection, M _PDrain electrode V _LDOBe the output of linear power supply.