CN103096002B - Imaging device and formation method thereof - Google Patents
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Abstract
The present invention relates to a kind of imaging device, including: pel array, it includes the multiple pixels being arranged in rows and columns；And multiple pixel output line, the plurality of pixel of at least a part of which string corresponds to more than one pixel output line；Wherein, in the described the plurality of pixel of at least string, more than one pixel reads via described more than one pixel output line simultaneously.
Description
Technical field
The present invention relates to imaging field, particularly a kind of imaging device and formation method thereof.
Background technology
The application of high speed imaging sensor is the most extensive.Such as in many application such as automobile sensor, safety monitoring, Industry Control and specialty camcorder, the requirement to the speed of imageing sensor is more and more higher.The common method of existing offer imageing sensor image taking speed includes: multichannel and row parallel read-out etc..Although these existing frameworks can improve frame per second to a certain extent.But, reading into the time required in column processing circuit from pel array cannot shorten due to single row of pixels simultaneously, and the raising of frame per second is finally limited by single file pixel readout times.Single row of pixels readout time is generally in the magnitude of 10 microseconds.This has become bottleneck and the restriction that current imageing sensor image taking speed improves further.
Summary of the invention
For technical problem present in prior art, according to an aspect of the present invention, it is proposed that a kind of imaging device, including: pel array, it includes the multiple pixels being arranged in rows and columns；And multiple pixel output line, the plurality of pixel of at least a part of which string corresponds to more than one pixel output line；Wherein, in the described the plurality of pixel of at least string, more than one pixel reads via described more than one pixel output line simultaneously.
According to another aspect of the present invention, propose a kind of reading circuit, including: multiple pixel output line, in wherein said multiple pixel output line, more than one pixel output line is corresponding with string pixel, wherein, in described at least row pixel, more than one pixel reads via described more than one pixel output line simultaneously；Multiple analog switches, it is connected with the plurality of pixel output line, selects the output signal of the pixel simultaneously read；And multiple process circuit, it is connected with multiple analog switches；Wherein, the chosen output of described output signal of the pixel simultaneously read is to different process circuit.
According to another aspect of the present invention, it is proposed that a kind of formation method, including: utilize pel array imaging, wherein said pel array to include the multiple pixels being arranged in rows and columns；And the multiple pixels by the row described pel array of reading, wherein said multiple pixels read via multiple pixel output line more than one-row pixels simultaneously；Wherein, at least the plurality of pixel of string is corresponding to more than one pixel output line.
Accompanying drawing explanation
Below, in conjunction with accompanying drawing, the preferred embodiment of the present invention will be described in more detail, wherein:
Fig. 1 is the schematic diagram of the structure of a kind of imaging device；
Fig. 2 is the schematic diagram illustrating a kind of representative pixels structure；
Fig. 3 is the schematic diagram illustrating a kind of representative pixels structure；
Fig. 4 is the structural representation of imaging device according to an embodiment of the invention；
Fig. 5 is the circuit diagram of imaging device according to an embodiment of the invention；
Fig. 6 is the sequential chart of the line control circuit of the imaging device shown in Fig. 5；
Fig. 7 is horizontal drive circuit schematic diagram according to an embodiment of the invention；
Fig. 8 a and Fig. 8 b is the functional schematic of analog switch according to an embodiment of the invention；
Fig. 9 a and Fig. 9 b is the functional schematic of another analog switch corresponding with the analog switch of Fig. 8 a and Fig. 8 b；And
Figure 10 is the flow chart of formation method according to an embodiment of the invention.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of protection of the invention.
In the following detailed description, may refer to as the application part for each Figure of description of the specific embodiment of the application is described.In the accompanying drawings, similar reference describes substantially similar assembly in different drawings.Each specific embodiment of the application has carried out the most detailed description following so that the those of ordinary skill possessing this area relevant knowledge and technology can implement the technical scheme of the application.It is to be understood that, it is also possible to utilize other embodiments or embodiments herein is carried out structure, logic or electrical change.
Term " pixel " one word refers to containing sensor devices or for converting electromagnetic signal into the electronic component of other devices of the signal of telecommunication.For illustrative purposes, Fig. 1 describes a kind of representative imaging device, and it comprises a pel array.A kind of representational pixel described in Fig. 2, and all pixels in pel array the most all will manufacture in a similar fashion.
Fig. 1 illustrates the schematic diagram of the structure of a kind of imaging device.Imaging device 100 shown in Fig. 1, such as CMOS imager device, including pel array 110.Pel array 110 comprises the multiple pixels being arranged in rows and columns.In pel array 110, every string pixel is all also turned on by column selection line, and every one-row pixels is optionally exported by row select line respectively.Each pixel has row address and column address.The column address of pixel is corresponding to the row select line driven by row decoding and drive circuit 120, and the row address of pixel is corresponding to the row select line driven by row decoding and drive circuit 130.Control circuit 140 controls the pixel output signal that row decoding is corresponding selectively to read row and column suitable in pel array with drive circuit 130 with row decoding with drive circuit 120.
Pixel output signal includes pixel reset signal Vrst and pixel image signal Vsig.The signal that pixel reset signal Vrst obtains from floating diffusion region when representing the floating diffusion region reseting sensor devices (such as photodiode).Pixel image signal Vsig represents the signal obtained after being transferred to floating diffusion region by the electric charge of the representative image acquired in sensor devices.Pixel reset signal Vrst and pixel image signal Vsig are read by row sampling and holding circuit 150, and subtract each other through differential amplifier 160.The Vrst-Vsig signal that differential amplifier 160 is exported i.e. represents the picture signal acquired in sensor devices.This picture signal is converted to digital signal after analog-digital converter ADC170, is then further processed by image processor 180, to export digitized image.
Fig. 2 is the schematic diagram illustrating a kind of representative pixels structure.The pixel 200 of Fig. 2 includes photodiode 202, transfering transistor 204, resets transistor 206, source following transistor 208 and row selecting transistor 210.Photodiode 202 is connected to the source electrode of transfering transistor 204.Transfering transistor 204 is controlled by signal TX.When TX controls transfering transistor to " on " state, in photodiode, the electric charge of accumulation is transferred in memory area 21.Meanwhile, photodiode 202 is reset.The grid of source following transistor 208 is connected to memory area 21.Source following transistor 208 amplifies the signal received from memory area 21.Reset transistor 206 source electrode and be also connected to memory area 21.Reset transistor 206 to be controlled by signal RST, be used for reseting memory area 21.Pixel 200 still further comprises by row selecting transistor 210.Row selecting transistor 210 is controlled by signal RowSel, and the signal that source following transistor 208 amplifies is exported output lead Vout.
Fig. 3 is also the schematic diagram illustrating a kind of representative pixels structure.Fig. 3 is not abstract circuit logic relation schematic diagram, but concrete semiconductor structure schematic diagram.Pixel 300 described in Fig. 3 includes photodiode 302 as sensor devices.Pixel 300 includes transfer gate 303, and it forms transfering transistor together with photodiode 302 and memory area, i.e. floating diffusion region 304.Pixel 300 also includes reseting grid 305, and it is connected between floating diffusion region 304 and active region 306, to reset floating diffusion region 304.Active region 306 is connected to electrode source Vaa.Pixel 300 also includes source follower gate 307, and it is connected between active region 306 and 308, forms source following transistor, and source follower gate 307 is electrically coupled to floating diffusion region 304 by electrical connection 347.Pixel 300 farther includes row selecting transistor grid 309, its be connected to active region 308 and as the active region 310 of pixel output between, formed row selecting transistor.
Channel region between source/drain regions of the source/drain region of above-mentioned transistor, floating diffusion region, under the gate one-level and photodiode are defined as active region because of its doping property, and it combines with grid structure and defines active electronic device.
For the problems of the prior art, the present invention proposes the reading circuit framework that a kind of multirow reads simultaneously so that can read two row even multirow picture element signal within the same time.This can greatly reduce the time that a line reads, and then improves the frame per second that whole sensor reads.The present invention can apply in the imaging device shown in Fig. 1-Fig. 3, it is also possible to applies in the structure that other are similar.
Fig. 4 is the structural representation of imaging device according to an embodiment of the invention.The embodiment of Fig. 4 have employed two row sense architecture simultaneously.It will be appreciated by those skilled in the art that the present invention equally uses more than reading framework while two row.As shown in Figure 4, imaging device 400 includes pel array 401.Fig. 4 shows 4 row of the arbitrary neighborhood of pel array 400 and the (n-1)th row, line n and the (n+1)th row and the n-th-2 row and a part for the n-th+2 row.String pixel every from other picture element array structures is different corresponding to 1 pixel output line, and the every string pixel in the embodiment shown in Fig. 4 is corresponding to 2 pixel output line.Such as, the string pixel of the leftmost side corresponds to pixel output line pixout0 and pixout1, and the secondary series pixel being adjacent is corresponding to pixel output line pixout2 and pixout3.So, every string pixel can there be 2 pixels to be read through 2 pixel output line simultaneously.According to one embodiment of present invention, in pel array, 2 pixels in every same row of string will be read simultaneously.Such as, the B pixel in the (n-1)th row and Gr pixel are read by pixel output line pixout0 and pixout1 simultaneously；Gb pixel and R pixel in (n-1)th row are read by pixel output line pixout2 and pixout3 simultaneously.B pixel in line n and Gr pixel are also read by pixel output line pixout0 and pixout1 simultaneously in the diagram；Gb pixel and R pixel in line n are also read by pixel output line pixout2 and pixout3 simultaneously., B pixel and Gr pixel in the (n+1)th row are read by pixel output line pixout0 and pixout1 simultaneously；Gb pixel and R pixel in (n+1)th row are read by pixel output line pixout2 and pixout3 simultaneously.
According to one embodiment of present invention, there is the potential difference of a pixel with two pixels the most adjacent in string, to be used for avoiding two pixels sharing same pixel output line to read simultaneously.
According to one embodiment of present invention, in the column circuits of the embodiment shown in Fig. 4, every two row pixels are corresponding to the analog switch of two 4 input 2 outputs, and its function is that two green pixels and red blue pixel are adjusted to correct position and are read.Such as: the signal of two colors of Gr and Gb is adjusted to a circuit；And the signal of two colors of B and R is adjusted to another circuit.As shown in Figure 4, two row pixels of the leftmost side correspond to analog switch MUX1 and MUX2.Wherein, analog switch MUX1 is used for being included into by the signal of Gr and Gb color in the circuit of lower section；And analog switch MUX2 is used for being included into by the signal of B and R color in the circuit of top.According to one embodiment of present invention, this analog switch is simulation multiple-input, multiple-output on-off circuit.Quantity according to pixel output line corresponding to each column pixel is different, analog switch can also be 6 inputs 3 export, 8 input 4 outputs etc..
As it has been described above, in the fig. 4 embodiment, for every string pixel, it is read simultaneously with two pixels of a line.Discounting for color, in other words, there are two row pixels to be read simultaneously.The reading circuit structure that this two row read simultaneously can effectively be accelerated to read frame per second, because being actually equivalent to needing the line number read to halve.In theory, if whole row is controlled by row for a long time readout time, then whole frame per second will promote 2 times.Present invention effect in this regard will be further illustrated about the comparison example of the calculating of frame per second by one.
Have employed two pixels in the fig. 4 embodiment and share the structure of output line.It will be appreciated by those skilled in the art that the multirow sense architecture of the present invention goes for any one dot structure.
Although the embodiment of Fig. 4 is the example read for two row simultaneously, the application of the present invention reads while can also extending into more multirow.Difference with the embodiment shown in Fig. 4 is, will need more pixel output line pixout when more multirow reads simultaneously.Such as, when 4 row read simultaneously, each column pixel needs 4 pixel output line.According to one embodiment of present invention, the elemental area of imaging device accounts for the 80% of whole imaging device area, pixel sensitivity will not cause the impact of essence limiting the increase of sense line.According to another embodiment of the invention, the imaging device that the multirow of the present invention reads simultaneously is applied BSI(BackSideIllumination) backlight technology, to improve the light sensitivitys of pixel.
Owing to Gr and Gb is to be read by different reading circuits, these reading circuits are owing to there being fine distinction on circuit layout, this may cause floating diffusion capacitance CFDThere is a little difference.Because the conversion gain of pixel is defined by formula below,
ConversionGain=q/CFD(uV/e)
Therefore, the conversion gain of Gr and Gb the two pixel also can be different.This can cause the reaction difference to light of two identical pixels, so that forming the examination board (checkboard) being similar to fixed pattern noise (Fixed-Partten-Noise, FPN) in the picture.When using higher conversion gain and greater compactness of pixel layout to reduce the volume of pixel, this defect can become even more serious.
According to one embodiment of present invention, add in the digital circuit after analog-digital converter ADC by digitized correction circuit.In the digitized correction of this circuit, pixel output will be multiplied by the correction digitized gain with special value, to compensate the difference of the conversion gain between Gr and Gb pixel.Revise digitized gain to be stored in the register memory of imageing sensor.When this imageing sensor powers on, revise digitized gain and be automatically loaded and be multiplied with pixel data output, so that the conversion gain between Gr and Gb pixel is identical, thus remove possible examination board pattern noise.
Fig. 5 is the circuit diagram of imaging device according to an embodiment of the invention.As it is shown in figure 5, imaging device 500 includes pel array.Showing a part for pel array in Fig. 5, including the line n of any two row and the (n+1)th row and n-1 row and a n+2 trade part, wherein n is positive integer, and n is approximately equal to 1.The embodiment of Fig. 5 have employed two pixel shared memories and do not has the dot structure of row selection signal line row_sel.It will be appreciated by those skilled in the art that other dot structure can be suitable for.As it is shown in figure 5, the neighbor of different rows shares electric charge storage region in first row.Such as, the (n-1)th row blueness B pixel 510 shares electric charge storage region 5201 with line n green Gr pixel 520；Line n blueness B pixel 530 and the (n+1)th row green Gr pixel 540 share electric charge storage region 5401；(n+1)th row blueness B pixel 550 and the n-th+2 row green Gr pixel 560 share electric charge storage region 5601.And often signal RST and RS control is reseted by respective two in the memory block of a line.Such as, the electric charge storage region 5201 of line n is by reseting signal RST<n>and RS<n>control；The electric charge storage region 5401 of the (n+1)th row is by reseting signal RST<n+1>and RS<n+1>control；The electric charge storage region 5601 of the n-th+2 row is by reseting signal RST<n+2>and RS<n+2>control.TX holding wire is shared with the pixel of a line different colours.Such as, green Gr pixel 520 and the blue B pixel 530 of line n shares holding wire TX<n>；Green Gr pixel 540 and the blue B pixel 550 of the (n+1)th row share holding wire TX<n+1>.The output of adjacent lines is connected respectively to different pixel output line.Such as, the electric charge storage region 5201 of line n is connected to pixel output line pixout0；The electric charge storage region 5401 of the (n+1)th row is connected to pixel output line pixout1；And the electric charge storage region 5601 of the n-th+2 row is connected to pixel output line pixout0 again.As it is shown in figure 5, the attachment structure of secondary series is identical with first row.The difference is that only that the color of pixel is different, repeat no more here.
Fig. 6 is the sequential chart of the line control circuit of the imaging device shown in Fig. 5.As shown in Figure 5 and Figure 6,2 pixels of row same for every string, its pixel control signal has same row cutting address；And, the two shares same TX holding wire.Therefore, when the row address of n and n+1 is opened, reset signal RS and RST and can reset line n and the electric charge storage region of the (n+1)th row, such as electric charge storage region 5201 and 5401 simultaneously.Then, n row address is opened, and when TX line signal arrives, two pixels of this row sharing this TX signal complete electric charge transfer simultaneously.Such as, line n green Gr pixel and blue B pixel complete electric charge transfer simultaneously.The signal of telecommunication shifted and formed is output in pixel output line pixout0 and pixout1 respectively.Thus, it is read simultaneously with the pixel of two different colours in a line.
As shown in Figure 5 and Figure 6, two pixels simultaneously read are because being controlled by different RS and RST signal.Therefore, row address<n>and<n+1>of RS and RST needs to be simultaneously open.And for TX signal, because two pixels read share a TX line simultaneously, therefore have only to a row address<n>and open the most permissible.In order to realize function above, horizontal drive circuit can be carried out suitable adjustment.
Fig. 7 is horizontal drive circuit schematic diagram according to an embodiment of the invention.As shown in Figure 7: horizontal drive circuit 700 includes that multiple row address switchs, such as switch 701 and 702.The direct control of row address switch is relative resets signal RS and RST and TX signal.Such as, what line n address switch 701 controlled line n resets signal RS<n>and RST<n>and TX<n>signal;(n+1)th row address switch 702 control the (n+1)th row reset signal RS<n+1>and RST<n+1>and TX<n+1>signal.In the embodiment shown in fig. 7, reset signal RS and RST and row address switch between be separately added into or door.And another input of these or door is connected to the row address switch of lastrow.Such as, reset signal RS<n in line n>and RST<n>and line n address switch 701 between be separately added into or door 703 and 704.Or an input of door 703 and 704 is connected to line n address switch 701, or another input of door 703 and 704 is connected to the (n-1)th row address switch.Similarly, reset signal RS<n+1 at the (n+1)th row>and RST<n+1>and the (n+1)th row address switch 702 between be separately added into or door 705 and 706.Or an input of door 705 and 706 is connected to the (n+1)th row address switch 702, or another input of door 703 and 704 is connected to line n address switch 702.Thus, when line n address is opened, the (n+1)th row reset signal RS<n+1>and RST<n+1>be opened too.
With reference to Fig. 4, every two corresponding two analog switches of row pixels meeting, in order to export predetermined column processing circuit by the pixel of predetermined color.In order to realize above-mentioned functions, the two analog switch has different conducting states at synchronization.Fig. 8 a and Fig. 8 b is the functional schematic of analog switch according to an embodiment of the invention.Fig. 9 a and Fig. 9 b is the functional schematic of another analog switch corresponding with the analog switch of Fig. 8 a and Fig. 8 b.As shown in Fig. 8 a, 8b, 9a and 9b, when the pixel of even number line address is read out, the analog switch being positioned at the such as analog switch MUX2 above Fig. 4 is in the state of Fig. 8 a, and below Fig. 4, the analog switch of such as analog switch MUX1 is in the state of Fig. 8 b.So, the signal of Gb and Gr pixel can be transferred to be positioned in the column circuits above Fig. 4 by analog switch MUX2, and the signal of B and R pixel is transferred to be positioned in the column circuits below Fig. 4 by analog switch MUX1.When the pixel of odd row address is read out, the analog switch being positioned at the such as analog switch MUX2 above Fig. 4 is in the state of Fig. 9 a, and below Fig. 4, the analog switch of such as analog switch MUX1 is in the state of Fig. 9 b.So, will ensure that the signal of Gb and Gr pixel can be transferred to be positioned in the column circuits above Fig. 4 by analog switch MUX2, and the signal of B and R pixel is transferred to be positioned in the column circuits below Fig. 4 by analog switch MUX1.
Figure 10 is the flow chart of formation method according to an embodiment of the invention.As shown in Figure 10, the formation method 1000 of the present invention, in step 1020, utilizes the pel array of imaging device to carry out imaging, and wherein this pel array is made up of the multiple pixels being arranged in rows and columns.In step 1040, by each pixel in row read pixel array；Wherein, it is read simultaneously more than the pixel of a line.In step 1060, the same column being read simultaneously but the read output signal of the pixel of different rows are transmitted by different pixel output line.In step 1080, the same column being read simultaneously but the read output signal of the pixel of different rows chosen after be output in different column circuits；The most according to one embodiment of present invention, described selection is color selecting.
Frame per second calculated examples
The technique effect of the present invention is further illustrated below by way of a concrete comparison example.Calculate the reading frame per second of different size of array in this example, and multirow will be used to read the frame per second of framework and the frame per second read according to normal framework compares simultaneously.
Table 1: the frame per second of general sense architecture:
| Array Size | 3Mpix | 5Mpix | 8Mpix | 12Mpix | 16Mpix |
| Format | 4/3 | 4/3 | 4/3 | 4/3 | 4/3 |
| Output cols | 2000 | 2580 | 3270 | 4000 | 4620 |
| Output rows | 1500 | 1940 | 2450 | 3000 | 3460 |
| ADC data(bit) | 10 | 10 | 10 | 12 | 12 |
| Ramp freq(MHz) | 200 | 200 | 200 | 200 | 200 |
| Memory freq(MHz) | 80 | 80 | 80 | 80 | 80 |
| Channel#(top+btm) | 4 | 4 | 4 | 8 | 8 |
| Row readout time(us) | 12.54 | 12.54 | 12.54 | 33.66 | 33.66 |
| Mem readout time(us) | 6.75 | 8.56 | 10.72 | 6.75 | 7.72 |
| Row time(us) | 12.54 | 12.54 | 12.54 | 33.66 | 33.66 |
| Frame rate(fps) | 53.16 | 41.11 | 32.55 | 9.9 | 8.59 |
Table 2: the frame per second of the sense architecture of the present invention:
| Array Size | 3Mpix | 5Mpix | 8Mpix | 12Mpix | 16Mpix |
| Format | 4/3 | 4/3 | 4/3 | 4/3 | 4/3 |
| Output cols | 2000 | 2580 | 3270 | 4000 | 4620 |
| Output rows | 1500 | 1940 | 2450 | 3000 | 3460 |
| ADC data(bit) | 10 | 10 | 10 | 12 | 12 |
| Ramp freq(MHz) | 200 | 200 | 200 | 200 | 200 |
| Memory freq(MHz) | 80 | 80 | 80 | 80 | 80 |
| Data path# | 4 | 4 | 4 | 8 | 8 |
| Row readout time(us) | 12.54 | 12.54 | 12.54 | 33.66 | 33.66 |
| Mem readout time(us) | 13.5 | 17.13 | 21.44 | 13.5 | 15.44 |
| Row time(us) | 13.5 | 17.13 | 21.44 | 33.66 | 33.66 |
| Frame rate(fps) | 98.77 | 60.2 | 38.08 | 19.81 | 17.17 |
| Mprovement% | 85.78% | 46.45% | 16.99% | 100.00% | 100.00% |
It can be seen that the pel array present invention for any size can improve frame per second significantly from table 1 and target contrast.And, for the biggest array, the lifting of frame per second is the most obvious.This is because the row of bigger array is easier to be occupied readout time by row for a long time, also hence in so that the advantage that reads of multirow is the most obvious simultaneously.
Above-described embodiment is used for illustrative purposes only, and is not limitation of the present invention, about the those of ordinary skill of technical field, without departing from the present invention, can also make a variety of changes and modification, therefore, the technical scheme of all equivalents also should belong to category disclosed by the invention.
Claims (17)
1. an imaging device, including:
Pel array, it includes the multiple pixels being arranged in rows and columns；And
Multiple pixel output line, the plurality of pixel of at least a part of which string corresponds to more than one pixel output line；
Wherein, in the described the plurality of pixel of at least string, more than one pixel reads via described more than one pixel output line simultaneously；Wherein, pixel adjacent in the described the plurality of pixel of at least string is read by different pixel output line,
Described imaging device farther includes, the digitized correction circuit after analog-digital converter, for for color is identical, the conversion gain of that read by different described pixel output line pixel is digitized revising.
2. imaging device as claimed in claim 1, wherein, the pixel simultaneously read shares TX holding wire.
3. imaging device as claimed in claim 2, wherein, the neighbor read time different shares electric charge storage region.
4. imaging device as claimed in claim 2, farther includes horizontal drive circuit, and what wherein said horizontal drive circuit started the pixel place that simultaneously reads simultaneously resets signal more than a line.
5. imaging device as claimed in claim 2, farther includes multiple analog switch, and the plurality of analog switch is connected with the plurality of pixel output line, selects with the output signal to the plurality of pixel output line.
6. imaging device as claimed in claim 5, wherein, the plurality of analog switch is connected to multiple process circuit, and different process circuit is arrived in the output after the plurality of analog switch selects of the output signal of the pixel simultaneously read.
7. imaging device as claimed in claim 1, wherein, the elemental area of imaging device accounts for the 80% of whole imaging device area.
8. imaging device as claimed in claim 1, wherein, applies BSI (BackSideIllumination) backlight technology in described imaging device.
9. a reading circuit, including:
Multiple pixel output line, in wherein said multiple pixel output line, more than one pixel output line is corresponding with string pixel, and wherein, at least in string pixel, more than one pixel reads via described more than one pixel output line simultaneously；
Multiple analog switches, it is connected with the plurality of pixel output line, selects the output signal of the pixel simultaneously read；And
Multiple process circuit, it is connected with multiple analog switches；
Wherein, the chosen output of described output signal of the pixel simultaneously read to different process circuit,
Described reading circuit still further comprises, the digitized correction circuit after analog-digital converter, for for color is identical, the conversion gain of that read by different described pixel output line pixel is digitized revising.
10. reading circuit as claimed in claim 9, wherein, described analog switch selects according to the color of the pixel read simultaneously.
11. reading circuits as claimed in claim 9, wherein, described pixel output line is connected to more than one described analog switch, and described analog switch has different connection status at synchronization.
12. 1 kinds of formation methods, including:
Pel array imaging, wherein said pel array is utilized to include the multiple pixels being arranged in rows and columns；And
Read multiple pixels of described pel array by row, wherein said multiple pixels read via multiple pixel output line more than one-row pixels simultaneously；
Wherein, at least the plurality of pixel of string corresponds to more than one pixel output line,
Described formation method farther includes, and after analog digital conversion, for color is identical, the conversion gain of that read by different described pixel output line pixel is digitized revising.
The formation method of 13. such as claim 12, the read output signal of the different rows pixel being wherein read simultaneously is by different pixel output line transmission.
The formation method of 14. such as claim 12, farther includes: the chosen output of read output signal of the different rows pixel simultaneously read is to different process circuit.
The formation method of 15. such as claim 14, wherein said selection is carried out according to pixel color.
The formation method of 16. such as claim 12, the different rows pixel the most simultaneously read is controlled by different reset signals, and described method farther includes: start the reset signal of the different rows pixel simultaneously read simultaneously.
The formation method of 17. such as claim 12, the pixel the most simultaneously read shares TX holding wire.
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| CN103051846A (en) * | 2011-10-11 | 2013-04-17 | 全视科技有限公司 | Multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination |
| CN202535464U (en) * | 2012-02-27 | 2012-11-14 | 徐辰 | Imaging device |
| CN103369253A (en) * | 2012-03-26 | 2013-10-23 | 徐辰 | Imaging device and imaging method |
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