CN103036511B - ADC (analog-to-digital converter) allowance amplifying circuit of infrared focal plane array detector readout circuit - Google Patents

ADC (analog-to-digital converter) allowance amplifying circuit of infrared focal plane array detector readout circuit Download PDF

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CN103036511B
CN103036511B CN201210541615.6A CN201210541615A CN103036511B CN 103036511 B CN103036511 B CN 103036511B CN 201210541615 A CN201210541615 A CN 201210541615A CN 103036511 B CN103036511 B CN 103036511B
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sampling
switch
operational amplifier
circuit
capacitance
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CN201210541615.6A
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CN103036511A (en
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吕坚
庹涛
孟祥笙
廖宝斌
杜一颖
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电子科技大学
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Abstract

The embodiment of the invention discloses an ADC (analog-to-digital converter) allowance amplifying circuit of an infrared focal plane array detector readout circuit. The ADC allowance amplifying circuit adopts a telescopic operation amplifier, a first capacitor C3 is added between an equivalent offset voltage source Vos and a first sampling capacitor C1, and a second capacitor C4 is added between the second input end in of the operation amplifier and a second sampling capacitor C2. Therefore, the influence of offset voltage of the operation amplifier on circuit performance can be eliminated and the influence of capacitor-to-voltage nonlinearity on the circuit performance is reduced.

Description

The ADC surplus amplifying circuit of infrared focal plane array seeker reading circuit

Technical field

The present invention relates to infrared focal plane array seeker field, especially relate to a kind of ADC surplus amplifying circuit of infrared focal plane array seeker reading circuit.

Background technology

All objects all launch the thermal radiation relevant with substance characteristics to its temperature, and the thermal radiation of near ambient temperature object is positioned at infrared band mostly, and wavelength is that 1 μm (micron) is to about 24 μm.Infrared radiation provides the abundant information of objective world, converts sightless infrared radiation to measurable signal, and making full use of these information is targets that people pursue.

Infrared focal plane array is the important photoelectric device obtaining scenery infrared light radiation information.Since first U.S.'s sieve door Air Development Center in 1973 proposes the silicide Schottky barrier detector array for infrared thermal imaging, infrared focal plane detector obtains and develops rapidly.Except being applied to traditional military imaging, be also widely used in the fields such as industrial automatic control, medical diagnosis, chemical process monitoring, infrared astronomy.

Micro-metering bolometer detector is most widely used a kind of infrared focal plane array, and it is a kind of thermistor detector.Its operation principle is that thermo-sensitive material is transformed into resistance variations the variations in temperature that the infrared radiation of incidence produces, by the size of measuring resistance change detection infrared radiation signal.Microbolometer FPA array utilizes micromachining technology to make heat insulating construction on silicon reading circuit, and form the micro-metering bolometer as detector cells in the above, realizes single chip architecture.Microbolometer FPA array is as the outstanding person of second generation non-refrigeration focal surface technology, with the uncooled infrared imaging system that it makes for core, there is compared with refrigerating infrared imaging system volume advantage little, low in energy consumption, and the ratio of performance to price of system is increased substantially, greatly facilitate infrared imaging system in a lot of fields in application.

Reading circuit is the integrated treatment circuit of a kind of special digital-to-analogue mixed signal, and before reading integrated circuit (ROIC) occurs, the hybrid circuit of preamplifier is made up of discrete resistance, electric capacity and transistor.Such as photovoltaic type, Extrinsic Silicon, platinum silicon very responsive to electromagnetic interference (EMI) with the high impedance detector of many photoconduction types, require that the impact of EMI is reduced in the place being placed on closely preamplifier.Use discrete component to require a large amount of areas, and in a given optical field of view, harsh restriction is proposed to the number of active lanes realized.ROIC helps to decrease EMI problem.Read the function that integrated circuit (ROIC) method also provides detector calorifics/mechanical interface, signal transacting and comprises mirror charge conversion and gain, frequency band limits and multipath conversion and output driving.Along with the development of integrated circuit technology and technology, the especially maturation of MOS Integrated-manufacturing Techniques and technique, makes ROIC obtain swift and violent development.

The function of reading circuit extracts the resistance variations of detector thermo-sensitive material, converts the signal of telecommunication to and the parallel/serial row carrying out pre-process (as integration, amplification, filtering and sampling/maintenances etc.) and signal is changed.Mainly contain CCD type reading circuit, CMOS type reading circuit at present.Along with continuous maturation, the perfect and development of CMOS technology, CMOS reading circuit becomes the main development direction of current reading circuit because of its numerous advantage.

In the integrated circuit that infrared focal plane read-out circuit is relevant, surplus amplifying circuit is widely used, and is mainly used in subtraction function, 2 times of gain functions, samplings keep function etc.But the performance of existing surplus amplifying circuit affects larger by the offset voltage of operational amplifier and the nonlinear of capacitance versus voltage.

Summary of the invention

An object of the present invention is to provide a kind of ADC surplus amplifying circuit can eliminating or reduce the infrared focal plane array seeker reading circuit of the impact of the offset voltage of operational amplifier.

An object of the present invention is to provide a kind of ADC surplus amplifying circuit that can reduce the infrared focal plane array seeker reading circuit of the non-linear impact on surplus amplifying circuit of capacitance versus voltage.

Disclosed in the embodiment of the present invention, technical scheme comprises:

A kind of ADC surplus amplifying circuit of infrared focal plane array seeker reading circuit, it is characterized in that, comprise: operational amplifier, described operational amplifier comprises first input end (ip), the second input (in), the first output (outp) and the second output (outn); First sampling capacitance (C1), the second sampling capacitance (C2), the first feedback capacity (C5), the second feedback capacity (C6), the first electric capacity (C3), the first sampling switch (P1), the second sampling switch (P1_d), the 3rd sampling switch (P1_FDOA), the first maintained switch (P2_d) and the second maintained switch (P2_dg), wherein: one end of described first electric capacity (C3) is connected to the described first input end (ip) of described operational amplifier, and by the first sampling switch (P1) shift voltage (Vsh) is connected to; The other end of described first electric capacity (C3) is connected to one end of described first sampling capacitance (C1) and described first feedback capacity (C5), and is connected to common-mode voltage (common-mode voltage (Vcm)) by described first sampling switch (P1); The other end of described first feedback capacity (C5) is connected to the first input signal end (Vinp) by described second sampling switch (P1_d), and is connected to described second output (outn) of described operational amplifier by described first maintained switch (P2_d); The other end of described first sampling capacitance (C1) is connected to described first input signal end (Vinp) by described second sampling switch (P1_d), and is connected to forward reference voltage (Vrefp) by described second maintained switch (P2_dg); One end of described second electric capacity (C4) is connected to described second input (in) of described operational amplifier, and is connected to shift voltage (Vsh) by described first sampling switch (P1); The other end of described second electric capacity (C4) is connected to one end of described second sampling capacitance (C2) and described second feedback capacity (C6), and is connected to common-mode voltage (common-mode voltage (Vcm)) by described first sampling switch (P1); The other end of described second feedback capacity (C6) is connected to the second input signal end (Vinn) by described second sampling switch (P1_d), and is connected to described first output (outp) of described operational amplifier by described first maintained switch (P2_d); The other end of described second sampling capacitance (C2) is connected to described second input signal end (Vinn) by described second sampling switch (P1_d), and is connected to negative sense reference voltage (Vrefn) by described second maintained switch (P2_dg).

Further, described first sampling switch (P1), described second sampling switch (P1_d) and the 3rd sampling switch (P1_FDOA) are closed, and described first maintained switch (P2_d) and described second maintained switch (P2_dg) disconnect.

Further, described first sampling switch (P1), described second sampling switch (P1_d) and the 3rd sampling switch (P1_FDOA) disconnect, and described first maintained switch (P2_d) and described second maintained switch (P2_dg) close.

Further, described operational amplifier is telescopic operational amplifier.

Further, the capacitance of described first sampling capacitance (C1) is identical with described first feedback capacity (C5), and the capacitance of described second sampling capacitance (C2) is identical with described second feedback capacity (C6).

In embodiments of the invention, ADC surplus amplifying circuit adopts telescopic OPAMP, has the advantages such as noise is little, low in energy consumption, conversion speed is fast.And by adding the first electric capacity C3 between equivalent offset voltage source Vos and the first sampling capacitance C1, the second electric capacity C4 is added between the second input in and the second sampling capacitance C2 of operational amplifier, the impact of operational amplifier offset voltage on circuit performance can be eliminated, and reduce the non-linear impact on circuit performance of capacitance versus voltage.

Accompanying drawing explanation

Fig. 1 is the structural representation of the ADC surplus amplifying circuit of the infrared focal plane array seeker reading circuit of one embodiment of the invention.

Fig. 2 is the equivalent circuit diagram of circuit under the sampling phase state of one embodiment of the invention.

Fig. 3 is the equivalent circuit diagram of circuit under the subtraction maintenance phase state of one embodiment of the invention.

Fig. 4 is the Control timing sequence schematic diagram of each switch of one embodiment of the invention.

Fig. 5 is the structural representation of the operational amplifier of one embodiment of the invention.

Embodiment

Fig. 1 is the ADC(analog to digital converter of the infrared focal plane array seeker reading circuit of one embodiment of the invention) structural representation of surplus amplifying circuit.As shown in Figure 1, in one embodiment of the present of invention, a kind of ADC surplus amplifying circuit of infrared focal plane array seeker reading circuit comprises: operational amplifier, the first sampling capacitance C1, the second sampling capacitance C2, the first feedback capacity C5, the second feedback capacity C6, the first electric capacity C3, the first sampling switch P1, the second sampling switch P1_d, the 3rd sampling switch P1_FDOA, the first maintained switch P2_d and the second maintained switch P2_dg.

As shown in Figure 1, this operational amplifier comprises first input end ip, the second input in, the first output outp and the second output outn.

One end of first electric capacity C3 is connected to the first input end ip of operational amplifier, and is connected to shift voltage Vsh by the first sampling switch P1; The other end of the first electric capacity C3 is connected to one end of the first sampling capacitance C1 and the first feedback capacity C5, and is connected to common-mode voltage Vcm by the first sampling switch P1.

The other end of the first feedback capacity C5 is connected to the first input signal end Vinp by the second sampling switch P1_d, and is connected to the second output outn of operational amplifier by the first maintained switch P2_d.

The other end of the first sampling capacitance C1 is connected to the first input signal end Vinp by the second sampling switch P1_d, and is connected to forward reference voltage Vref p by the second maintained switch P2_dg.

One end of second electric capacity C4 is connected to the second input in of operational amplifier, and is connected to shift voltage Vsh by the first sampling switch P1; The other end of the second electric capacity C4 is connected to one end of the second sampling capacitance C2 and the second feedback capacity C6, and is connected to common-mode voltage Vcm by the first sampling switch P1.

The other end of the second feedback capacity C6 is connected to the second input signal end Vinn by the second sampling switch P1_d, and is connected to the first output outp of operational amplifier by the first maintained switch P2_d.

The other end of the second sampling capacitance C2 is connected to the second input signal end Vinn by the second sampling switch P1_d, and is connected to negative sense reference voltage Vref n by the second maintained switch P2_dg.

In embodiments of the invention, in fact this ADC surplus amplifying circuit is equivalent to the offset voltage source Vos of the equivalence that further comprises between a first input end ip at operational amplifier and the first electric capacity C3.

In embodiments of the invention, wherein the capacitance of the first sampling capacitance C1 can be identical with the first feedback capacity C5, and the capacitance of the second sampling capacitance C2 can be identical with the second feedback capacity C6

In embodiments of the invention, this ADC surplus amplifying circuit can be operated in two states: sampling phase state and subtraction keep phase state.

Wherein under a kind of state, first sampling switch P1, the second sampling switch P1_d and the 3rd sampling switch P1_FDOA are closed, and the first maintained switch P2_d and the second maintained switch P2_dg disconnects, now, this ADC surplus amplifying circuit is operated in sampling phase state, and now the equivalent circuit diagram of this circuit as shown in Figure 2.

Now, first sampling capacitance C1 and the first feedback capacity C5 samples to the first input signal Vinp, and the second sampling capacitance C2 and the second feedback capacity C6 samples to the second input signal Vinn, respectively the first electric capacity C3 and the second electric capacity C4 is charged by common-mode voltage Vcm and shift voltage Vsh simultaneously.

Wherein under another kind of state, first sampling switch P1, the second sampling switch P1_d and the 3rd sampling switch P1_FDOA disconnect, and the first maintained switch P2_d and the second maintained switch P2_dg closes, now, this ADC surplus amplifying circuit is operated in subtraction and keeps phase state, and now the equivalent circuit diagram of this circuit as shown in Figure 3.

Now, first feedback capacity C5 is connected to the second output outn of operational amplifier, second feedback capacity C6 is connected to the first output outp of operational amplifier, first sampling capacitance C1 and the second sampling capacitance C2 is connected respectively to output forward reference voltage Vref p and the negative sense reference voltage Vref n of sub-DAC, and circuit enters subtraction and keeps the stage.Wherein, Vrefp and Vrefn is the output signal of sub-DAC, and to be the digital signal that received by sub-DAC carry out combination as the reference voltage of switch controlling signal antithetical phrase DAC inside and common-mode voltage is formed by stacking.

In embodiments of the invention, by controlling the disconnection of the first sampling switch P1, the second sampling switch P1_d, the 3rd sampling switch P1_FDOA, the first maintained switch P2_d and the second maintained switch P2_dg and closing, this ADC surplus amplifying circuit can be controlled and be operated in sampling phase state or subtraction maintenance phase state.Such as, in an embodiment, the sequential chart controlling the first sampling switch P1, the second sampling switch P1_d, the 3rd sampling switch P1_FDOA, the first maintained switch P2_d and the second maintained switch P2_dg can be as shown in Figure 4, conducting between each switch, opening time put life period and postpone, and its objective is the impact in order to eliminate charge injection.

In embodiments of the invention, first sampling switch P1, the second sampling switch P1_d, the 3rd sampling switch P1_FDOA, the first maintained switch P2_d and the second maintained switch P2_dg are suitable for the switch by any type herein, as long as it can switch between closed and disconnected two states.Wherein, " closing " herein refers to that the state that switch is in conducting electric current can be allowed to pass through, "off" are in switch the state that cut-out do not allow electric current to pass through.

In embodiments of the invention, wherein this operational amplifier can be telescopic operational amplifier.Such as, in an embodiment, telescopic operational amplifier as shown in Figure 5.

Compared with the folded operational amplifier generally adopted, telescopic operational amplifier has the advantages such as noise is little, low in energy consumption, conversion speed is fast.Because high-precision analog to digital converter needs the operational amplifier of high-gain, therefore therefore can adopt gainboost structural sleeve formula operational amplifier further in one embodiment of the invention, namely in common telescopic operational amplifier, two auxiliary operation amplifiers are added, to improve the gain of operational amplifier.

As shown in Figure 2, the first electric capacity C3 is connected between offset voltage source Vos and the first sampling capacitance C1, and the second electric capacity C4 is connected between the second input in of operational amplifier and the second sampling capacitance C2.In sampling phase state, by common-mode voltage Vcm and shift voltage Vsh, the first electric capacity C3 and the second electric capacity C4 is charged, its with voltage can raise the first sampling capacitance C1 in circuit, second sampling capacitance C2, the magnitude of voltage at right pole plate (pole plate on the right side namely in Fig. 2) place of the first feedback capacity C5 and the second feedback capacity C6, it is made to reach the common-mode voltage value of differential input voltage, when inputting differential voltage, can make the first sampling capacitance C1 and the first feedback capacity C5 and the second sampling capacitance C2 and the second feedback capacity C6 with magnitude of voltage equal and opposite in direction, polarity is contrary, its relation is shown below:

Wherein V incmthe common mode input of operational amplifier.

In switched-capacitor circuit, the dependence of couple capacitors voltage may introduce sizable distortion, and what the dependence of capacitance versus voltage produced is non-linearly shown below:

Wherein M, α 1for constant.

When differential input signals is transported to the first sampling capacitance C1, second sampling capacitance C2, the left pole plate of the first feedback capacity C5 and the second feedback capacity C6, now utilize on the first electric capacity C3 and the second electric capacity C4 store voltage can by the first sampling capacitance C1, second sampling capacitance C2, on the right pole plate of the first feedback capacity C5 and the second feedback capacity C6, voltage is lifted to the common-mode voltage value of differential input signals, make the first sampling capacitance C1 and the first feedback capacity C5 and the second sampling capacitance C2 and the second feedback capacity C6 value equal and opposite in direction with voltage, polarity is contrary, final differential output signal by get difference after, the quadratic term in output signal can be eliminated, also the non-linear impact that circuit performance is produced of electric capacity is just eliminated, the theoretical procedure of circuit for eliminating quadratic term is shown below:

As mentioned before, the first electric capacity C3 is connected between offset voltage source Vos and the first sampling capacitance C1, and the second electric capacity C4 is connected between operational amplifier second input in and the second sampling capacitance C2.Under sampling phase state, by common-mode voltage Vcm and shift voltage Vsh, the first electric capacity C3 and the second electric capacity C4 is charged, and keep the charge conservation carried in phase state in sampling phase state and subtraction according to electric capacity, i.e. the first sampling capacitance C1, first feedback capacity C5, first electric capacity C3 keeps the total electrical charge conservation carried in phase state in sampling phase state and subtraction, second sampling capacitance C2, second feedback capacity C6, second electric capacity C4 keeps the total electrical charge conservation carried in phase state in sampling phase state and subtraction, the offset voltage that operational amplifier produces can be eliminated thus.

In sampling phase state, the first sampling capacitance C1, the first feedback capacity C5, total amount of electric charge entrained by the first electric capacity C3 are , and C1=C5; Second sampling capacitance C2, the second feedback capacity C6, total amount of electric charge entrained by the second electric capacity C4 are , and C2=C6.Then , be calculated as follows shown in:

Wherein, operational amplifier two input terminal voltage is equal, i.e. V ip=V in.

Keep in phase state at subtraction, the first sampling capacitance C1, the first feedback capacity C5, total amount of electric charge entrained by the first electric capacity C3 are , and C1=C5; Second sampling capacitance C2, the second feedback capacity C6, total amount of electric charge entrained by the second electric capacity C4 are , and C2=C6.Then , be calculated as follows shown in:

Wherein, b is constant, and V ip=V in.

Charge conservation entrained in phase state is kept in sampling phase state and subtraction, then according to the electric capacity in integrated circuit = , = , opening relationships formula is as follows:

Relational expression is obtained as follows by abbreviation:

Final differential output voltage is that above two formulas get difference:

Can learn from above-mentioned result of calculation, the offset voltage Vos of operational amplifier is eliminated by the first electric capacity C3 of adding and the second electric capacity C4.

In sum, in the embodiment of the present invention, by aforementioned first electric capacity C3 and the second electric capacity C4 utilize its with voltage can raise the first sampling capacitance C1 and the second sampling capacitance C2 in the circuit of sampling phase state, and the first right polar plate voltage value of feedback capacity C5 and the second feedback capacity C6, it is made to reach the common-mode voltage value of differential input voltage, make the first sampling capacitance C1 and the first feedback capacity C5 and the second sampling capacitance C2 and the second feedback capacity C6 value equal and opposite in direction with voltage, polarity is contrary, thus when differential output signal subtraction, the quadratic term of input signal in outputing signal can be made to subtract each other, eliminate the non-linear impact caused to the performance of circuit of capacitance versus voltage.

First electric capacity C3 and the second electric capacity C4 completes charging in the sampling phase state of surplus amplifying circuit, and keep the charge conservation carried in phase state in sampling phase state and subtraction according to electric capacity, i.e. the first sampling capacitance C1, first feedback capacity C5, first electric capacity C3 keeps the total electrical charge conservation carried in phase state in sampling phase state and subtraction, second sampling capacitance C2, second feedback capacity C6, second electric capacity C4 keeps the total electrical charge conservation carried in phase state in sampling phase state and subtraction, the final offset voltage Vos eliminating amplifier in surplus amplifying circuit, whole circuit performance is got a promotion.

Therefore, in embodiments of the invention, ADC surplus amplifying circuit adopts telescopic OPAMP, has the advantages such as noise is little, low in energy consumption, conversion speed is fast.And by adding the first electric capacity C3 between equivalent offset voltage source Vos and the first sampling capacitance C1, the second electric capacity C4 is added between the second input in and the second sampling capacitance C2 of operational amplifier, the impact of operational amplifier offset voltage on circuit performance can be eliminated, and reduce the non-linear impact on circuit performance of capacitance versus voltage.

Described the present invention by specific embodiment above, but the present invention is not limited to these specific embodiments.It will be understood by those skilled in the art that and can also make various amendment, equivalent replacement, change etc. to the present invention, as long as these conversion do not deviate from spirit of the present invention, all should within protection scope of the present invention.In addition, " embodiment " described in above many places represents different embodiments, can certainly by its all or part of combination in one embodiment.

Claims (5)

1. an ADC surplus amplifying circuit for infrared focal plane array seeker reading circuit, is characterized in that, comprising:
Operational amplifier, described operational amplifier comprises first input end (ip), the second input (in), the first output (outp) and the second output (outn);
First sampling capacitance (C1), the second sampling capacitance (C2), the first feedback capacity (C5), the second feedback capacity (C6), the first electric capacity (C3), the first sampling switch (P1), the second sampling switch (P1_d), the 3rd sampling switch (P1_FDOA), the first maintained switch (P2_d) and the second maintained switch (P2_dg), wherein:
One end of described first electric capacity (C3) is connected to the described first input end (ip) of described operational amplifier, and is connected to shift voltage (Vsh) by the first sampling switch (P1); The other end of described first electric capacity (C3) is connected to one end of described first sampling capacitance (C1) and described first feedback capacity (C5), and is connected to common-mode voltage (common-mode voltage (Vcm)) by described first sampling switch (P1);
The other end of described first feedback capacity (C5) is connected to the first input signal end (Vinp) by described second sampling switch (P1_d), and is connected to described second output (outn) of described operational amplifier by described first maintained switch (P2_d);
The other end of described first sampling capacitance (C1) is connected to described first input signal end (Vinp) by described second sampling switch (P1_d), and is connected to forward reference voltage (Vrefp) by described second maintained switch (P2_dg);
One end of second electric capacity (C4) is connected to described second input (in) of described operational amplifier, and is connected to shift voltage (Vsh) by described first sampling switch (P1); The other end of described second electric capacity (C4) is connected to one end of described second sampling capacitance (C2) and described second feedback capacity (C6), and is connected to common-mode voltage (common-mode voltage (Vcm)) by described first sampling switch (P1);
The other end of described second feedback capacity (C6) is connected to the second input signal end (Vinn) by described second sampling switch (P1_d), and is connected to described first output (outp) of described operational amplifier by described first maintained switch (P2_d);
The other end of described second sampling capacitance (C2) is connected to described second input signal end (Vinn) by described second sampling switch (P1_d), and is connected to negative sense reference voltage (Vrefn) by described second maintained switch (P2_dg).
2. circuit as claimed in claim 1, it is characterized in that: described first sampling switch (P1), described second sampling switch (P1_d) and the 3rd sampling switch (P1_FDOA) are closed, and described first maintained switch (P2_d) and described second maintained switch (P2_dg) disconnect.
3. circuit as claimed in claim 1, it is characterized in that: described first sampling switch (P1), described second sampling switch (P1_d) and the 3rd sampling switch (P1_FDOA) disconnect, and described first maintained switch (P2_d) and described second maintained switch (P2_dg) close.
4. circuit as claimed in claim 1, is characterized in that: described operational amplifier is telescopic operational amplifier.
5. circuit as claimed in claim 1, it is characterized in that: the capacitance of described first sampling capacitance (C1) is identical with described first feedback capacity (C5), the capacitance of described second sampling capacitance (C2) is identical with described second feedback capacity (C6).
CN201210541615.6A 2012-12-14 2012-12-14 ADC (analog-to-digital converter) allowance amplifying circuit of infrared focal plane array detector readout circuit CN103036511B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1708983A (en) * 2002-11-07 2005-12-14 克塞尼克斯股份有限公司 Read-out circuit for infrared detectors
CN1801900A (en) * 2004-08-11 2006-07-12 美国博通公司 Operational amplifier for an active pixel sensor
US20060284603A1 (en) * 2005-06-17 2006-12-21 Oliver Nehrig Capacitance-to-voltage conversion method and apparatus
CN102818637A (en) * 2012-08-03 2012-12-12 中国科学院上海技术物理研究所 CTIA (Capacitive Transimpedance Amplifier) structure input stage applicable to readout circuit of IRFPA (Infrared Focus Plane Arrray)

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1708983A (en) * 2002-11-07 2005-12-14 克塞尼克斯股份有限公司 Read-out circuit for infrared detectors
CN1801900A (en) * 2004-08-11 2006-07-12 美国博通公司 Operational amplifier for an active pixel sensor
US20060284603A1 (en) * 2005-06-17 2006-12-21 Oliver Nehrig Capacitance-to-voltage conversion method and apparatus
CN102818637A (en) * 2012-08-03 2012-12-12 中国科学院上海技术物理研究所 CTIA (Capacitive Transimpedance Amplifier) structure input stage applicable to readout circuit of IRFPA (Infrared Focus Plane Arrray)

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