CN103000581B - Production method of thin film transistor (TFT) array substrate - Google Patents
Production method of thin film transistor (TFT) array substrate Download PDFInfo
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- CN103000581B CN103000581B CN201210545349.4A CN201210545349A CN103000581B CN 103000581 B CN103000581 B CN 103000581B CN 201210545349 A CN201210545349 A CN 201210545349A CN 103000581 B CN103000581 B CN 103000581B
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Abstract
The invention provides a production method of a TFT array substrate. A base substrate is provided, a metal film is formed on the base substrate, and a pattern containing grid lines is formed through a patterning process; a grid insulating layer, a semiconductor film, a doped semiconductor film and a data metal layer film are formed on the base substrate on which the figure containing the grid lines is formed; figures containing a patterned grid insulating layer, an active layer arranged on the grid insulating layer and a doped semiconductor layer and figures of a source electrode arranged on the doped semiconductor layer, a drain electrode and a data line are formed through the patterning process; a passivating layer is formed on the base substrate on which the patterns of the source electrode, the drain electrode and the data line are formed; and a transparent conducting film is formed on the base substrate on which the passivating layer is formed, a figure containing a pixel electrode is formed through the patterning process, and the pixel electrode is connected with the drain electrode through a first via hole penetrating the passivating layer. According to the production method, a mask plate process can be reduced, and the production cost of the array substrate can be reduced.
Description
Technical field
The present invention relates to technical field of liquid crystal display, refer to a kind of manufacture method of thin-film transistor array base-plate especially.
Background technology
In 4Mask (4 mask plates) technology, via hole technique is all by after carry out gluing on array base palte, the mask of employing mask plate successively, exposure, development, etching technics complete via hole again, and then utilize via hole to realize the good contact of the conductive film of different layers, the complexity that this technique compares in implementation process, operation compares many.In the completing of via hole technique, consume a large amount of funds, improve production cost greatly.The cost of such as, photoresist in gluing process, the mask plate in mask process, the solution in developing process and exposure, etching apparatus etc. is all very large.In the production process that operation is various, be easy to bring the management and control of technique bad, directly cause the bad display of the panel produced.In the panel detection and bad analysis of reality, a lot of bad displays is all due to when via hole technique, easily there is chamfering at via hole place, cross the technological problems generations such as quarter, carved or occurred to remain again in chamfering or etching process if produced, will cause short circuit or resistance excessive, directly cause display bad.And if management and control is bad in etching technics, occur the problem that above-mentioned problem will not be a just panel, but whole glass or a collection of glass all will be scrapped.Area on the other hand due to dry etching via hole is large, will affect the aperture opening ratio of liquid crystal panel like this, and the brightness of directly impact display, affects the quality of product.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method of thin-film transistor array base-plate, reduces by a mask plate technique, reduces the cost of manufacture of array base palte.
For solving the problems of the technologies described above, embodiments of the invention provide a kind of manufacture method of thin-film transistor array base-plate, comprise the following steps:
S11, provides a underlay substrate;
S12, described underlay substrate forms metallic film, is formed the figure comprising grid line by patterning processes;
S13, the underlay substrate of completing steps S12 is formed gate insulation layer, semiconductive thin film, doped semiconductor films and data metal layer film, formed the figure of the gate insulation layer comprising patterning, the active layer be positioned on gate insulation layer, doping semiconductor layer by patterning processes, and be positioned at the figure of source electrode, drain electrode and data wire on described doping semiconductor layer;
S14, the underlay substrate of completing steps S13 forms passivation layer;
S15, the underlay substrate of completing steps S14 forms transparent conductive film, is formed the figure comprising pixel electrode by patterning processes, and described pixel electrode is connected with described drain electrode by the first via hole running through described passivation layer; Described first via hole adopts laser punching welding procedure to be formed.
Wherein, described step S12 comprises:
Described underlay substrate forms metallic film;
Adopt normal masks plate to be processed described metallic film by patterning processes, form the figure comprising grid line.
Wherein, described step S13 comprises:
Described grid line forms gate insulation layer;
Described gate insulation layer is formed semiconductive thin film, doped semiconductor films and data metal layer film;
Halftoning or gray mask plate is adopted to be processed described gate insulation layer, semiconductive thin film, doped semiconductor films and data metal layer film by patterning processes, form the figure comprising the gate insulation layer of patterning, the active layer be positioned on gate insulation layer, doping semiconductor layer, and be positioned at the figure of source electrode, drain electrode and data wire on described doping semiconductor layer.
Wherein, described employing halftoning or gray mask plate are processed described gate insulation layer, semiconductive thin film, doped semiconductor films and data metal layer film by patterning processes, form the figure comprising the gate insulation layer of patterning, the active layer be positioned on gate insulation layer, doping semiconductor layer, and the step of the figure being positioned at source electrode, drain electrode and data wire on described doping semiconductor layer comprises:
Described data metal layer film applies one deck photoresist;
Halftoning or gray mask plate is adopted to remove by cineration technics the photoresist that region removed completely by photoresist;
Etch away described photoresist completely by etching technics and remove the data metal layer film in region, doped semiconductor layer film and active layer film completely, expose gate insulation layer, and etch away photoresist, data metal layer film, the doped semiconductor layer film of channel region completely, expose active layer;
Peel off remaining photoresist, expose the figure of the source electrode in this region, drain electrode and data wire.
Wherein, etch away described photoresist completely by etching technics and remove the data metal layer film in region, doped semiconductor layer film and active layer film completely, expose gate insulation layer, and etch away photoresist, data metal layer film, the doped semiconductor layer film of channel region completely, the step exposing active layer comprises:
The data metal layer film that region removed completely by described photoresist is etched away completely by first time etching technics;
Etched away the photoresist of described channel region by second time etching technics completely, expose data metal layer;
Etch away by third time etching technics doped semiconductor layer film and the active layer film that region removed completely by described photoresist completely, expose gate insulation layer;
Etched away the data metal layer of described channel region by the 4th etching technics completely, expose doping semiconductor layer;
Etched away the doping semiconductor layer of described channel region by the 5th etching technics completely, expose active layer.
Wherein, described step S14 comprises:
On the described gate insulation layer exposed, in described source electrode, on described drain electrode, raceway groove forms passivation layer.
Wherein, described step S15 comprises:
The underlay substrate of completing steps S14 forms transparent conductive film;
Adopt normal masks plate to be processed described transparent conductive film by patterning processes, form the figure comprising pixel electrode;
Wherein, described pixel electrode is connected with described drain electrode by the first via hole running through described passivation layer.
Wherein, also comprise when forming grid line: form public electrode wire;
When forming pixel electrode, also comprise: form public electrode;
Described public electrode is connected with described public electrode wire by the second via hole through described passivation layer and described gate insulation layer.
Wherein, described second via hole adopts laser punching welding procedure to be formed.
Wherein, described first via hole and described second via hole are all formed or are formed after the described transparent conductive film of formation after the described passivation layer of formation.
The beneficial effect of technique scheme of the present invention is as follows:
In such scheme, eliminate a mask plate in preparation technology, eliminate the gluing that traditional via hole technique is applied, mask, exposure, development, the a series of technique such as etching technics, substituting be laser drilling welding procedure, what complete from 4 mask plates to 3 mask plate technologies is excessive, reduce the production cost of array base palte, and employing laser drilling, hole area prepared by the mask plate technique that the area ratio of via hole is traditional is little many, therefore, the area of each sub-pix can also be increased, thus increase aperture opening ratio, improve the overall display brightness of panel, improve the quality of product.
Accompanying drawing explanation
Figure 1A is in the manufacture method of array base palte of the present invention, the plane graph after grid deposit metal films;
Figure 1B is in the manufacture method of array base palte of the present invention, the profile after grid deposit metal films;
Fig. 2 A is in the manufacture method of array base palte of the present invention, the plane graph of first time mask plate technique formation grid line;
Fig. 2 B is in the manufacture method of array base palte of the present invention, the profile of first time mask plate technique formation grid line;
Fig. 3 A is in the manufacture method of array base palte of the present invention, forms the plane graph of gate insulation layer, active layer, doping semiconductor layer and data metal layer;
Fig. 3 B is in the manufacture method of array base palte of the present invention, forms the profile of gate insulation layer, active layer, doping semiconductor layer and data metal layer;
Fig. 4 A is in the manufacture method of array base palte of the present invention, the plane graph after deposition photoresist;
Fig. 4 B is in the manufacture method of array base palte of the present invention, the profile after deposition photoresist;
Fig. 5 A is in the manufacture method of array base palte of the present invention, and second time mask plate technique forms the plane graph of the photoresist after ashing process;
Fig. 5 B is in the manufacture method of array base palte of the present invention, and second time mask plate technique forms the profile of the photoresist after ashing process;
Fig. 6 A is in the manufacture method of array base palte of the present invention, the plane graph after data metal layer first time etching;
Fig. 6 B is in the manufacture method of array base palte of the present invention, the profile after data metal layer first time etching;
Fig. 7 A is in the manufacture method of array base palte of the present invention, the plane graph after photoresist etching;
Fig. 7 B is in the manufacture method of array base palte of the present invention, the profile after photoresist etching;
Fig. 8 A is in the manufacture method of array base palte of the present invention, the plane graph after active layer first time etching;
Fig. 8 B is in the manufacture method of array base palte of the present invention, the profile after active layer first time etching;
Fig. 9 A is in the manufacture method of array base palte of the present invention, the plane graph after data metal layer second time etching;
Fig. 9 B is in the manufacture method of array base palte of the present invention, the profile after data metal layer second time etching;
Figure 10 A is in the manufacture method of array base palte of the present invention, the plane graph after doping semiconductor layer etching;
Figure 10 B is in the manufacture method of array base palte of the present invention, the profile after doping semiconductor layer etching;
Figure 11 A is in the manufacture method of array base palte of the present invention, the plane graph after photoresist removal;
Figure 11 B is in the manufacture method of array base palte of the present invention, the profile after photoresist removal;
Figure 12 A is in the manufacture method of array base palte of the present invention, the plane graph after deposit passivation layer;
Figure 12 B is in the manufacture method of array base palte of the present invention, the profile after deposit passivation layer;
Figure 13 A is in the manufacture method of array base palte of the present invention, the plane graph after deposit transparent conductive film;
Figure 13 B is in the manufacture method of array base palte of the present invention, the profile after deposit transparent conductive film;
Figure 14 A is in the manufacture method of array base palte of the present invention, the plane graph after utilizing laser to punch;
Figure 14 B is in the manufacture method of array base palte of the present invention, the profile after utilizing laser to punch;
Figure 15 A is in the manufacture method of array base palte of the present invention, by third time mask plate technique to transparent conductive film process, obtain the plane graph of pixel electrode;
Figure 15 B is in the manufacture method of array base palte of the present invention, by third time mask plate technique to transparent conductive film process, obtain the profile of pixel electrode.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
As shown in Figure 1A-Figure 15 B, embodiments of the invention provide a kind of manufacture method of thin-film transistor array base-plate, comprise the following steps:
S11, provides a underlay substrate 1;
S12, described underlay substrate forms metallic film, is formed the figure comprising grid line 2 by patterning processes;
S13, the underlay substrate of completing steps S12 is formed gate insulation layer, semiconductive thin film, doped semiconductor films and data metal layer film, formed the figure of the gate insulation layer 3 comprising patterning, the active layer 4 be positioned on gate insulation layer, doping semiconductor layer 5 by patterning processes, and be positioned at the figure 6 of source electrode, drain electrode and data wire on described doping semiconductor layer 5;
S14, the underlay substrate of completing steps S13 forms passivation layer 8;
S15, the underlay substrate of completing steps S14 forms transparent conductive film, is formed the figure comprising pixel electrode 9 by patterning processes, and described pixel electrode 9 is connected with described drain electrode by the first via hole 10 running through described passivation layer 8.
Wherein, described step S12 comprises:
Described underlay substrate is formed metallic film (as shown in FIG. 1A and 1B);
Adopt normal masks plate to be processed described metallic film by patterning processes, form the figure (as shown in Figure 2 A and 2 B) comprising grid line.
Wherein, described step S13 comprises:
S131, described grid line forms gate insulation layer;
S132, described gate insulation layer is formed semiconductive thin film, doped semiconductor films and data metal layer film (as shown in Figure 3 A and Figure 3 B);
S133, halftoning or gray mask plate is adopted to be processed described gate insulation layer, semiconductive thin film, doped semiconductor films and data metal layer film by patterning processes, form the figure comprising the gate insulation layer 3 of patterning, the active layer 4 be positioned on gate insulation layer, doping semiconductor layer 5, and be positioned at the figure 6 of source electrode, drain electrode and data wire on described doping semiconductor layer.
Wherein, step S133 comprises:
Step S1331, described data metal layer film applies one deck photoresist 7 (as shown in Figure 4 A and 4 B shown in FIG.);
Step S1332, adopts halftoning or gray mask plate to remove by cineration technics the photoresist (as fig. 5 a and fig. 5b) that region removed completely by photoresist;
Step S1333, etch away photoresist completely by etching technics and remove the data metal layer in region, doped semiconductor layer film and active layer completely, expose gate insulation layer, and etch away photoresist, data metal layer film, the doping semiconductor layer of channel region completely, expose active layer;
Step S1334, peels off remaining photoresist 7, exposes the figure (as seen in figs. 11 a and 11b) of the source electrode in this region, drain electrode and data wire.
Wherein, step S1333 comprises:
The data metal layer film (as shown in Figure 6 A and 6 B) that region removed completely by photoresist is etched away completely by first time etching technics;
Etched away the photoresist of channel region by second time etching technics completely, expose data metal layer (as shown in figures 7 a and 7b);
Etch away by third time etching technics doped semiconductor layer film and the active layer that region removed completely by photoresist completely, expose gate insulation layer (as shown in Figure 8 A and 8 B);
Etched away the data metal layer of channel region by the 4th etching technics completely, expose doping semiconductor layer (as shown in fig. 9 a and fig. 9b);
Etched away the doping semiconductor layer of channel region by the 5th etching technics completely, expose active layer (as shown in figs. 10 a and 10b).
Wherein, described step S14 comprises: on the described gate insulation layer exposed, described source electrode, described drain electrode, described raceway groove, form passivation layer (as illustrated in figs. 12 a and 12b).
Wherein, described step S15 comprises:
S151, the underlay substrate of completing steps S14 is formed transparent conductive film (as shown in figures 13 a and 13b);
S152, is adopted normal masks plate to be processed described transparent conductive film by patterning processes, forms the figure (as shown in fig. 15 a and fig. 15b) comprising pixel electrode;
In above-described embodiment, described pixel electrode is connected with described drain electrode by the first via hole running through described passivation layer; Described first via hole adopts laser to be formed by punching welding procedure, described first via hole can be formed after the described passivation layer of formation, concrete, after having deposited the transparent conductive film for the preparation of pixel electrode, form (as Figure 14 A and Figure 14 B); Also can be formed after completing the passivation layer shown in Figure 12 A and Figure 12 B.
In another embodiment of the invention, on the basis of above-mentioned steps S11-S15, also comprise when forming grid line: form public electrode wire; When forming pixel electrode, also comprise: form public electrode;
Described public electrode is connected with described public electrode wire by the second via hole through described passivation layer and described gate insulation layer.
This second via hole is the same with the first via hole, and adopt laser punching welding procedure to be formed, described second via hole also can be formed after the described passivation layer of formation; Concrete, after having deposited the transparent conductive film for the preparation of pixel electrode, form (as Figure 14 A and Figure 14 B); Also can be formed after completing the passivation layer shown in Figure 12 A and Figure 12 B.
The manufacture method of above-mentioned array base palte of the present invention, complete from 4 mask plate techniques to 3 mask plate techniques good excessively.Relative to existing by after carry out gluing on array base palte, then the via hole technique that the mask of employing mask plate successively, exposure, development, etching technics complete.Embodiments of the invention are welded by laser drilling, equally can realize the connection of the conductive film of different layers, realize path, and do not need processing step various like that.By this invention, can reduce array base palte prepared to become in 1 mask plate technique.So just greatly reduce the cost of technique.The cost of such as, photoresist in gluing process, the mask plate in mask process, the solution in developing process and exposure, etching apparatus etc. is all extremely considerable.In addition, the method of the laser drilling adopted in embodiments of the invention avoids the various drawback of the operation of traditional via hole technique, various due to operation in traditional via hole technique, such as coating technique, masking process, exposure technology, developing process, etching technics, just be easy to bring the management and control of technique bad in this series of technical process, also increase the probability that residual panel produces, directly cause the bad display of the panel produced.Further, due to much less than the area of via hole of laser drilling, the area of each sub-pix so just can be increased, thus increase aperture opening ratio, improve the overall display brightness of panel, improve the quality of product.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a manufacture method for thin-film transistor array base-plate, is characterized in that, comprises the following steps:
S11, provides a underlay substrate;
S12, described underlay substrate forms metallic film, is formed the figure comprising grid line by the first patterning processes;
S13, the underlay substrate of completing steps S12 is formed gate insulation layer, semiconductive thin film, doped semiconductor films and data metal layer film, formed the figure of the gate insulation layer comprising patterning, the active layer be positioned on gate insulation layer, doping semiconductor layer by the second patterning processes, and be positioned at the figure of source electrode, drain electrode and data wire on described doping semiconductor layer;
S14, the underlay substrate of completing steps S13 forms passivation layer;
S15, the underlay substrate of completing steps S14 forms transparent conductive film, forms by the 3rd patterning processes the figure comprising pixel electrode, and described pixel electrode is connected with described drain electrode by the first via hole running through described passivation layer; Described first via hole adopts laser punching welding procedure to be formed.
2. the manufacture method of thin-film transistor array base-plate according to claim 1, is characterized in that, described step S12 comprises:
Described underlay substrate forms metallic film;
Adopt normal masks plate to be processed described metallic film by patterning processes, form the figure comprising grid line.
3. the manufacture method of thin-film transistor array base-plate according to claim 1, is characterized in that, described step S13 comprises:
Described grid line forms gate insulation layer;
Described gate insulation layer is formed semiconductive thin film, doped semiconductor films and data metal layer film;
Halftoning or gray mask plate is adopted to be processed described gate insulation layer, semiconductive thin film, doped semiconductor films and data metal layer film by patterning processes, form the figure comprising the gate insulation layer of patterning, the active layer be positioned on gate insulation layer, doping semiconductor layer, and be positioned at the figure of source electrode, drain electrode and data wire on described doping semiconductor layer.
4. the manufacture method of thin-film transistor array base-plate according to claim 3, it is characterized in that, described employing halftoning or gray mask plate are processed described gate insulation layer, semiconductive thin film, doped semiconductor films and data metal layer film by patterning processes, form the figure comprising the gate insulation layer of patterning, the active layer be positioned on gate insulation layer, doping semiconductor layer, and the step of the figure being positioned at source electrode, drain electrode and data wire on described doping semiconductor layer comprises:
Described data metal layer film applies one deck photoresist;
Halftoning or gray mask plate is adopted to remove by cineration technics the photoresist that region removed completely by photoresist;
Etch away described photoresist completely by etching technics and remove the data metal layer film in region, doped semiconductor layer film and active layer film completely, expose gate insulation layer, and etch away photoresist, data metal layer film, the doped semiconductor layer film of channel region completely, expose active layer;
Peel off remaining photoresist, expose the figure of the source electrode in this region, drain electrode and data wire.
5. the manufacture method of thin-film transistor array base-plate according to claim 4, it is characterized in that, etch away described photoresist completely by etching technics and remove the data metal layer film in region, doped semiconductor layer film and active layer film completely, expose gate insulation layer, and etch away photoresist, data metal layer film, the doped semiconductor layer film of channel region completely, the step exposing active layer comprises:
The data metal layer film that region removed completely by described photoresist is etched away completely by first time etching technics;
Etched away the photoresist of described channel region by second time etching technics completely, expose data metal layer;
Etch away by third time etching technics doped semiconductor layer film and the active layer film that region removed completely by described photoresist completely, expose gate insulation layer;
Etched away the data metal layer of described channel region by the 4th etching technics completely, expose doping semiconductor layer;
Etched away the doping semiconductor layer of described channel region by the 5th etching technics completely, expose active layer.
6. the manufacture method of thin-film transistor array base-plate according to claim 1, is characterized in that, described step S14 comprises:
On the described gate insulation layer exposed, in described source electrode, on described drain electrode, raceway groove forms passivation layer.
7. the manufacture method of thin-film transistor array base-plate according to claim 1, is characterized in that, described step S15 comprises:
The underlay substrate of completing steps S14 forms transparent conductive film;
Adopt normal masks plate to be processed described transparent conductive film by patterning processes, form the figure comprising pixel electrode;
Wherein, described pixel electrode is connected with described drain electrode by the first via hole running through described passivation layer.
8. the manufacture method of the thin-film transistor array base-plate according to any one of claim 1-7, is characterized in that, also comprises when forming grid line: form public electrode wire;
When forming pixel electrode, also comprise: form public electrode;
Described public electrode is connected with described public electrode wire by the second via hole through described passivation layer and described gate insulation layer.
9. the manufacture method of thin-film transistor array base-plate according to claim 8, is characterized in that, described second via hole adopts laser punching welding procedure to be formed.
10. the manufacture method of thin-film transistor array base-plate according to claim 9, is characterized in that, described first via hole and described second via hole are all formed or formed after the described transparent conductive film of formation after the described passivation layer of formation.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1987622A (en) * | 2005-12-23 | 2007-06-27 | 京东方科技集团股份有限公司 | Array base board structure of thin film transistor liquid crystal display and its producing method |
| CN101666948A (en) * | 2008-09-03 | 2010-03-10 | 北京京东方光电科技有限公司 | TFT-LCD pixel structure, manufacturing method and broken wire repairing method |
| CN102436095A (en) * | 2012-01-06 | 2012-05-02 | 中国电子科技集团公司第五十五研究所 | Manufacturing method of transmission-type silicon-based liquid crystal display |
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| CN100517075C (en) * | 2006-03-09 | 2009-07-22 | 北京京东方光电科技有限公司 | Manufacturing method for array substrate of thin film transistor LCD |
| CN100549791C (en) * | 2007-01-31 | 2009-10-14 | 友达光电股份有限公司 | The method for making of array base palte |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1987622A (en) * | 2005-12-23 | 2007-06-27 | 京东方科技集团股份有限公司 | Array base board structure of thin film transistor liquid crystal display and its producing method |
| CN101666948A (en) * | 2008-09-03 | 2010-03-10 | 北京京东方光电科技有限公司 | TFT-LCD pixel structure, manufacturing method and broken wire repairing method |
| CN102436095A (en) * | 2012-01-06 | 2012-05-02 | 中国电子科技集团公司第五十五研究所 | Manufacturing method of transmission-type silicon-based liquid crystal display |
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