CN102981591A - Method for reducing power consumption of computer system in sleep mode and system - Google Patents
Method for reducing power consumption of computer system in sleep mode and system Download PDFInfo
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- CN102981591A CN102981591A CN2011102610855A CN201110261085A CN102981591A CN 102981591 A CN102981591 A CN 102981591A CN 2011102610855 A CN2011102610855 A CN 2011102610855A CN 201110261085 A CN201110261085 A CN 201110261085A CN 102981591 A CN102981591 A CN 102981591A
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Abstract
The invention relates to a method for reducing power consumption of a computer system working in a sleep mode and a relevant computer system. Before the computer system goes into the sleep mode from a normal mode, state information is written into a memorizer of the computer system. After the computer goes into the sleep mode, a first output voltage is provided to the memorizer and electricity is not supplied components in the computer system is stopped. Before the computer system goes back to the normal mode, a second output voltage is provided to the memorizer, wherein a value output by the first output voltage is smaller than a value output by the second output voltage. Power consumption can be further reduced in the sleep mode, and therefore sleep and standby time is prolonged.
Description
Technical field
The present invention relates to a kind of method and correlative computer system that reduces the computer system power consumption, espespecially a kind of method and correlative computer system of power consumption when reducing computer system and under sleep pattern, moving.
Background technology
ACPI (Advanced Configuration and Power Interface, ACPI) be that purpose is to allow operating system can directly manage the situation that various devices utilize power supply by the common computer power management specification of formulating of the manufacturers such as Intel, Microsoft, Phoenix, HP and Toshiba.
Existing ACPI framework is given a definition and computer system different conditions and the electric source modes in when running: normal operating conditions G0 comprises the S0 pattern, and sleep state G1 comprises S1～S4 pattern, and open state G2 comprises the S5 pattern.Following summary power supply situation of primary clustering in the computer system under S0～S5 pattern:
The S0 pattern: the operating system of computer system and application program are all being carried out, and continued power is to all component;
The S1 pattern: CPU (central processing unit) (central processing unit, CPU) stops to carry out instruction, but still continued power is to CPU and other assembly;
S2 pattern: stop power supply to CPU, but still continued power is given other assembly;
The S3 pattern: only continued power is to storer, but stops power supply to other assembly;
S4 pattern: memory data is write hard disk, stop power supply to all component;
S5 pattern: close all component fully.
The S3 pattern can be referred to as again STR (Suspend to RAM) pattern, in the XP of Microsoft or (SuSE) Linux OS, be called holding state (stand-by), in the Vista of Microsoft or Mac OS X operating system, then be called sleep state (sleep).Under the S3 pattern, computer system can be written into storer with the data of keeping in, and allows storer part in addition all quit work.Therefore, if the user temporarily need not use, can allow computer system enter the S3 pattern saving energy, and when needs use, also can reply immediately fast the computer state.
In the computer system under the ACPI framework, do not do the power saving design for the S3 pattern in addition in the prior art, the power supply situation of storer is not optimization, therefore still might cause unnecessary energy consumption.
Summary of the invention
The invention provides a kind of method of power consumption when reducing a computer system and moving under a sleep pattern, it writes a storer in this computer system with a data before being included in and entering this sleep pattern from a normal mode; After entering this sleep pattern, one first output voltage is powered to this storer, and stop power supply to other assembly in this computer system; And before entering this normal mode from this sleep pattern, one second output voltage is powered to this storer, wherein the value of this first output voltage is less than the value of this second output voltage.
The present invention provides a kind of computer system that reduces power consumption under the sleep pattern in addition, and it comprises a storer; One CPU (central processing unit) is used for before entering this sleep pattern from a normal mode data being write this storer; One power supply supply; An and microprocessor, being used for adjusting this power supply supply powers one first output voltage to this storer it under this sleep pattern, and before getting back to this normal mode from this sleep pattern, one second output voltage is powered to this storer, wherein the value of this first output voltage is less than the value of this second output voltage.
In the present invention, storer only needs small self-refreshing electric current can keep data under sleep pattern, the power supply supply is only powered to storer by carrying out the required minimum voltage of self-refreshing, can further reduce the power consumption under the sleep pattern, uses to promote the sleep stand-by time.
Description of drawings
Fig. 1 is the synoptic diagram of a low power consuming computer system among the present invention.
Process flow diagram when Fig. 2 is computer system operation of the present invention.
Wherein
10-CPU 20-power supply supply 30-storer
40-microprocessor 100-computer system
Embodiment
Fig. 1 is the synoptic diagram of a low power consuming computer system 100 among the present invention.Computer system 100 comprises a CPU 10, power supply supply 20, one storer 30, and a microprocessor 40, can switch between a normal mode and a sleep pattern.
Process flow diagram when Fig. 2 is computer system 100 operation of the present invention, it comprises the following step:
Step 210: power to computer system 100 interior all components under normal mode, to operate execution in step 220.
Step 220: judge whether to enter sleep pattern: if, execution in step 230; If not, execution in step 210.
Step 230: with data write store 30, execution in step 240.
Step 240: one first output voltage is powered to storer 30, and stop power supply to computer system 100 interior other assemblies to enter sleep pattern, execution in step 250.
Step 250: judge whether to leave sleep pattern: if, execution in step 260; If not, execution in step 240.
Step 260: one second output voltage is powered execution in step 210 to storer 30.
In an embodiment of the present invention, normal mode can be the S0 pattern of ACPI, and namely power supply supply 20 can be powered to all component in the computer system 100 in step 210.Can see through data bus between CPU 10 and the storer 30 this moment and transmit, and then executive operating system and application program.
In an embodiment of the present invention, sleep pattern can be the S3 pattern of ACPI, if in step 220, judge and to enter sleep pattern, this moment, CPU 10 meetings will be referred in step 230 in the data write stories 30 such as state of operating system, all application programs and the archives that are unlocked, so when after get back to normal mode after, computer system 100 can return back to rapidly and enter the front original state of sleep pattern.
In step 240, CPU 10 can be closed after starting microprocessor 40, and stops power supply to computer system 100 interior other assemblies to enter sleep pattern.Under sleep pattern, microprocessor 40 can be adjusted power supply supply 20 can provide the first output voltage to storer 30.If judge in step 250 and need leave sleep pattern, microprocessor 40 can be adjusted power supply supply 20 can provide the second output voltage to storer 30.
In the present invention's embodiment, storer 30 can be a kind of volatile memory (volatile memory), dynamic RAM (Dynamic Random Access Memory for example, DRAM), main action principle is that the binary bit that how much represents of utilizing capacitor memory to deposit electric charge is 1 or 0.In actual applications, electric capacity has the electric leakage situation unavoidablely.Affect the integrality of data for fear of charge escaping, storer 30 must periodically be carried out the charging action of self-refreshing (self refresh).
In the present invention, power supply supply 20 is only powered to storer 30 by carrying out the required minimum voltage of self-refreshing after entering sleep pattern, before leaving sleep pattern, power to storer 30 with normal output voltage again, therefore can further reduce the power consumption under the sleep pattern, use promoting the sleep stand-by time.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. the method for a power consumption can reduce a computer system and under a sleep pattern, move the time, its step comprises:
Before entering this sleep pattern from a normal mode, a data is write a storer in this computer system;
After entering this sleep pattern, one first output voltage is powered to this storer, and stop power supply to other assembly in this computer system;
And before entering this normal mode from this sleep pattern, one second output voltage is powered to this storer, wherein the value of this first output voltage is less than the value of this second output voltage.
2. the method for claim 1 is characterized in that, also be included in enter this normal mode after, continued power is given all component in this computer system.
3. the method for claim 1 is characterized in that, but also comprises the value that decides this first output voltage according to the operating voltage range of this storer when the charging of carrying out a self-refreshing is moved.
4. the method for claim 1 is characterized in that, but also comprises the value that decides this first output voltage according to this reservoir required minimum operating voltage when the charging of carrying out a self-refreshing is moved.
5. the method for claim 1 is characterized in that, this normal mode is the S0 pattern under an ACPI (ACPI) framework, and this sleep pattern is the S3 pattern under this ACPI framework.
6. the method for claim 1 is characterized in that, judging whether needs to enter this sleep pattern from this normal mode, or enters this normal mode from this sleep pattern.
7. the method for claim 1 is characterized in that, this data relates under this normal mode the be unlocked state of archives of an operating system, an application program or in this computer system.
8. computer system that can reduce power consumption under the sleep pattern, it comprises:
One storer:
One CPU (central processing unit) is used for before entering this sleep pattern from a normal mode data being write this storer:
One power supply supply; And
One microprocessor, being used for adjusting this power supply supply powers one first output voltage to this storer it under this sleep pattern, and before getting back to this normal mode from this sleep pattern, one second output voltage is powered to this storer, wherein the value of this first output voltage is less than the value of this second output voltage.
9. computer system as claimed in claim 8 is characterized in that, this microprocessor is controlled this power supply supply and made it stop power supply to this CPU (central processing unit) in order to after entering this sleep pattern.
10. computer system as claimed in claim 9 is characterized in that, adopts an ACPI framework, and this normal mode is the S0 pattern under this ACPI framework, and this sleep pattern is the S3 pattern under this ACPI framework.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011102610855A CN102981591A (en) | 2011-09-05 | 2011-09-05 | Method for reducing power consumption of computer system in sleep mode and system |
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| CN2011102610855A CN102981591A (en) | 2011-09-05 | 2011-09-05 | Method for reducing power consumption of computer system in sleep mode and system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9348770B1 (en) | 2014-11-20 | 2016-05-24 | Industrial Technology Research Institute | Non-volatile semiconductor memory device with temporary data retention cells and control method thereof |
| CN106560761A (en) * | 2015-10-01 | 2017-04-12 | 联想企业解决方案(新加坡)有限公司 | Computer system and method for providing both main power and auxiliary power on a single power bus |
| CN106775491A (en) * | 2016-12-30 | 2017-05-31 | 北京联想核芯科技有限公司 | Data processing method and storage device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060198225A1 (en) * | 2005-03-04 | 2006-09-07 | Seagate Technology Llc | Reducing power consumption in a data storage system |
| US20080082845A1 (en) * | 2006-09-29 | 2008-04-03 | Kabushiki Kaisha Toshiba | Information processing apparatus and system state control method |
| CN101581962A (en) * | 2009-06-19 | 2009-11-18 | 北京红旗胜利科技发展有限责任公司 | Method for reducing CPU power consumption and CPU |
| US20100250981A1 (en) * | 2009-03-30 | 2010-09-30 | Lenova (Singapore) Pte. Ltd. | Dynamic memory voltage scaling for power management |
| CN101916138A (en) * | 2010-08-06 | 2010-12-15 | 北京中星微电子有限公司 | Method and device for switching working state and sleep state of central processing unit |
-
2011
- 2011-09-05 CN CN2011102610855A patent/CN102981591A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060198225A1 (en) * | 2005-03-04 | 2006-09-07 | Seagate Technology Llc | Reducing power consumption in a data storage system |
| US20080082845A1 (en) * | 2006-09-29 | 2008-04-03 | Kabushiki Kaisha Toshiba | Information processing apparatus and system state control method |
| US20100250981A1 (en) * | 2009-03-30 | 2010-09-30 | Lenova (Singapore) Pte. Ltd. | Dynamic memory voltage scaling for power management |
| CN101581962A (en) * | 2009-06-19 | 2009-11-18 | 北京红旗胜利科技发展有限责任公司 | Method for reducing CPU power consumption and CPU |
| CN101916138A (en) * | 2010-08-06 | 2010-12-15 | 北京中星微电子有限公司 | Method and device for switching working state and sleep state of central processing unit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9348770B1 (en) | 2014-11-20 | 2016-05-24 | Industrial Technology Research Institute | Non-volatile semiconductor memory device with temporary data retention cells and control method thereof |
| CN106560761A (en) * | 2015-10-01 | 2017-04-12 | 联想企业解决方案(新加坡)有限公司 | Computer system and method for providing both main power and auxiliary power on a single power bus |
| CN106775491A (en) * | 2016-12-30 | 2017-05-31 | 北京联想核芯科技有限公司 | Data processing method and storage device |
| CN106775491B (en) * | 2016-12-30 | 2019-05-31 | 北京联想核芯科技有限公司 | Data processing method and storage equipment |
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Application publication date: 20130320 |