CN102931828A - Power factor correction circuit and method for improving power factor - Google Patents

Power factor correction circuit and method for improving power factor Download PDF

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Publication number
CN102931828A
CN102931828A CN2012103187063A CN201210318706A CN102931828A CN 102931828 A CN102931828 A CN 102931828A CN 2012103187063 A CN2012103187063 A CN 2012103187063A CN 201210318706 A CN201210318706 A CN 201210318706A CN 102931828 A CN102931828 A CN 102931828A
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output
circuit
signal
connects
resistance
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CN102931828B (en
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谢小高
叶美盼
王栋
姚丰
吴建兴
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Hangzhou Silan Microelectronics Co Ltd
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Hangzhou Silan Microelectronics Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00Climate change mitigation technologies for sector-wide applications
    • Y02P80/10Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

The invention provides a power factor correction circuit and a method for improving a power factor. The power factor correction circuit comprises a main circuit, an error amplifier, a signal tracking circuit, a summing circuit and a driving pulse signal generating circuit, wherein the error amplifier performs error amplification on output current/voltage of the main circuit and then generates a first signal; the signal tracking circuit is used for generating a second signal the frequency and phase of which are same as those of a sine half-wave signal generated by rectification in the main circuit; the summing circuit is used for summing the first signal and the second signal to generate a third signal; and the driving pulse signal generating circuit generates a driving pulse signal according to the third signal, and the driving pulse signal is used for controlling the on/off of a switch tube in the main circuit. According to the invention, the power factor of the power factor correction circuit can be improved.

Description

Circuit of power factor correction and improve the method for power factor
Technical field
The present invention relates to a kind of circuit of power factor correction and improve the method for power factor.
Background technology
At present, non-linear element in most of power consumption equipments and energy-storage travelling wave tube can make the input AC current waveform that serious distortion occurs, cause net side input power factor very low, in order to satisfy the harmonic requirement of international standard IEC61000-3-2, must in these power consumption equipments, add power factor correcting (PFC).General boost (Boost) topology, buck (Buck-boost) topology or voltage-dropping type (Buck) topology of adopting of traditional APFC.Wherein, the Boost topology has control easily, drives simple and can carry out the characteristics such as switch in whole power frequency period, and the power factor of input current can be close to 1.But the Boost topology has the high shortcoming of output voltage, and under wide region input (90Vac-265Vac) condition, can be than the low 1-3% of high pressure section (220Vac-265Vac) in the efficient of low-voltage section (90Vac-110Vac).
The Buck topology can keep greater efficiency in whole input voltage range, therefore have certain advantage in non-isolation applications occasion, so Buck type pfc circuit also receives increasing concern in recent years.Yet the Buck topology is applied to pfc circuit, the input voltage V after rectification InLess than output voltage V oThe interval in, inductive current i LWith input current i AcBe zero, as shown in Figure 1.This section Dead Time has increased Harmonics of Input largely, has affected net side input power factor.When especially input voltage was low, Buck topological circuit harmonic content was larger, relatively is difficult to by some international standards.The control technology of a kind of improved Buck-PFC of being applicable to is disclosed in the prior art, can reduce harmonic content, yet sort circuit need to increase the voltage waveform that an auxiliary winding gathers inductance at the inductance of Buck circuit, increase the design complexities of inductance, thereby increased circuit cost.
In the isolation applications occasion, middle low power application scenario especially, the Buck-boost(Flyback of isolated form) pfc circuit is most widely used a kind of structure.If adopt the discontinuous mode control mode, can realize in theory exchanging the inlet wire input power factor is 1, yet discontinuous mode control mode current stress is large, and main circuit switch is operated in the hard switching state, and loss is larger.Therefore, what application was more at present is critical continuous conduction mode control, the control mode that wherein can realize critical continuous conduction mode control has two kinds substantially, and a kind of is with the Power Factor Correction Control of multiplier with the input feedforward, and another kind of control mode is to adopt permanent ON time control.No matter be the critical discontinuous mode Buck-boost(Flyback that adopts which kind of control mode to realize) circuit structure, the normalized input current waveform in its half power frequency period all as shown in Figure 2, s=V wherein o'/V Ac, V o' be that output voltage is converted transformer primary side amplitude afterwards, V AcBe the AC-input voltage effective value, s is the ratio coefficient of the two.As seen from Figure 2, along with s diminishes, namely the input voltage amplitude increases, and the wave distortion of input current is more severe, and power factor is lower.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of circuit of power factor correction and improves the method for power factor, can improve the power factor of circuit of power factor correction, this technical scheme can either be applicable to Buck type circuit of power factor correction, is applicable to again Buck-Boost(or the Flyback of critical continuous conduction mode) the type circuit of power factor correction.
For solving the problems of the technologies described above, the invention provides a kind of circuit of power factor correction, comprising:
Main circuit;
Error amplifier carries out producing first signal after error is amplified to the output current/voltage of described main circuit;
Signal tracking circuit, for generation of secondary signal, the half-sinusoid signal that rectifier produces in described secondary signal and the described main circuit is with the frequency homophase;
Add circuit will produce the 3rd signal after described first signal and the secondary signal addition;
The drive pulse signal circuit for generating produces drive pulse signal according to described the 3rd signal, and described drive pulse signal is used for controlling the conducting of the switching tube of described main circuit/shutoff.
Alternatively, described signal tracking circuit comprises:
Peak-detector circuit, the peak envelope line that is used for obtaining the electric current that flows through described switching tube is with as described secondary signal.
Alternatively, described peak-detector circuit comprises:
The first switch, its input are as the positive input terminal of described peak-detector circuit, and its output is as the output of described peak-detector circuit;
The first electric capacity, its first end connects the output of described the first switch, its second end ground connection and as the negative input end of described peak-detector circuit.
Alternatively, described peak-detector circuit comprises:
The first diode, its anode are as the positive input terminal of described peak-detector circuit, and its negative electrode is as the output of described peak-detector circuit;
The second electric capacity, its first end connects the negative electrode of described the first diode, its second end ground connection and as the negative input end of described peak-detector circuit.
Alternatively, described signal tracking circuit comprises: low pass filter, the mean value that is used for obtaining the electric current that flows through described switching tube is with as described secondary signal.
Alternatively, described low pass filter comprises the resistance-capacitance low-pass filter circuit of one-level or plural serial stage.
Alternatively, described signal tracking circuit comprises:
Low pass filter, its positive input terminal receives described drive pulse signal, its negative input end ground connection;
Peak-detector circuit, its positive input terminal connects the output of described low pass filter, its negative input end ground connection;
The first resistance, its first end connects the output of described low pass filter;
The second resistance, its first end connects the output of described peak-detector circuit;
The 3rd resistance, its first end connect the second end of described the second resistance, its second end ground connection;
The first operational amplifier, its positive input terminal connects the second end of described the first resistance, its negative input end connects the second end of described the second resistance, and its output connects the negative input end of described the first operational amplifier via the 4th resistance, and its output is exported described secondary signal.
Alternatively, described circuit of power factor correction also comprises: ratio circuit, described secondary signal transfer to described add circuit after zooming in or out via described ratio circuit.
Alternatively, described main circuit comprises:
Rectifier bridge carries out rectification and produces described half-sinusoid signal input signal;
Switching tube, its input connects the positive output end of described rectifier bridge, and its control end receives described drive pulse signal;
The second diode, its negative electrode connects the output of described switching tube, the negative output terminal of the described rectifier bridge of its anodic bonding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
Inductance, its first end connect the second end of described sampling resistor;
Output capacitance, its first end connect the second end of described inductance, and its second end connects the negative output terminal of described rectifier bridge.
Alternatively, described error amplifier comprises:
The 5th resistance, its first end connects the output of described switching tube;
The second operational amplifier, its negative input end connect the second end of described the 5th resistance, and its output connects the negative input end of described the second operational amplifier via the 4th electric capacity, and its output is exported described first signal;
The first reference voltage source, the one end connects the positive input terminal of described the second operational amplifier, other end ground connection.
Alternatively, stating the drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input connects the first end of described output capacitance, and the voltage at described output capacitance two ends is carried out zero passage detection;
Saw-tooth wave generating circuit is for generation of sawtooth signal;
The first comparator, its negative input end receive the 3rd signal of described add circuit output, and its positive input terminal receives described sawtooth signal;
Rest-set flip-flop, its set input connects the output of described zero cross detection circuit, and its RESET input connects the output of described the first comparator, and its positive output end is connected to the control end of described switching tube via driver module.
Alternatively, described zero cross detection circuit comprises:
The 6th resistance, its first end connects the first end of described output capacitance;
The 7th resistance, its first end connect the second end of described the 6th resistance, its second end ground connection;
The second comparator, its negative input end connect the second end of described the 6th resistance, and its output connects the set input of described rest-set flip-flop;
The second reference voltage source, the one end connects the positive input terminal of described the second comparator, other end ground connection.
Alternatively, described saw-tooth wave generating circuit comprises:
Current source;
The 5th electric capacity, its first end connects the output of described current source, its second end ground connection;
Second switch, with described the 5th Capacitance parallel connection, its control end connects the negative output terminal of described rest-set flip-flop.
Alternatively, described main circuit comprises:
Rectifier bridge carries out rectification and produces described half-sinusoid signal input signal;
Transformer, the Same Name of Ends of its former limit winding connects the positive output end of described rectifier bridge, the Same Name of Ends ground connection of its secondary winding;
Switching tube, its input connect the different name end of described former limit winding,
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
The 3rd diode, the different name end of the secondary winding of the described transformer of its anodic bonding;
Output capacitance, its first end connects the negative electrode of described the 3rd diode, its second end ground connection.
Alternatively, described error amplifier comprises:
The 8th resistance, its first end connects the first end of described output capacitance;
The 9th resistance, its first end connect the second end of described the 8th resistance, its second end ground connection;
The tenth resistance, its first end connects the first end of described output capacitance;
The 6th electric capacity, its first end connect the second end of described the 8th resistance;
Three end adjustable shunt reference sources, its plus earth, its negative electrode connects the second end of described the 6th electric capacity, and its control end connects the second end of described the 8th resistance;
Optocoupler, its first pin connects the second end of described the tenth resistance, and its crus secunda connects the second end of described the 6th electric capacity, and its tripod is exported described first signal, its 4th pin ground connection.
Alternatively, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input is connected with the different name end of the auxiliary winding of described transformer, the Same Name of Ends ground connection of described auxiliary winding;
The input voltage sample circuit is sampled to the half-sinusoid signal of described rectifier bridge output;
Multiplier, its first input end connects the output of described input voltage sample circuit, and the second input receives described the 3rd signal;
The 3rd comparator, its negative input end connects the output of described multiplier, and its positive input terminal connects the output of described switching tube;
Rest-set flip-flop, its RESET input connects the output of described the 3rd comparator, and its set input connects the output of described zero cross detection circuit, and its positive output end connects the control end of described switching tube via driver module.
Alternatively, described zero cross detection circuit comprises:
The 11 resistance, its first end connect the different name end of the ancillary coil of described transformer;
The 12 resistance, its first end connects the second end of described the 11 resistance, its second end ground connection;
The 4th comparator, its negative input end connects the second end of described the 11 resistance, and its positive input terminal connects the first end of the 3rd reference voltage source, and its output connects the set input of described rest-set flip-flop, the second end ground connection of described the 3rd reference voltage source.
Alternatively, described input voltage sample circuit comprises:
The 13 resistance, its first end connects the positive output end of described rectifier bridge, and its second end connects the first input end of described multiplier;
The 14 resistance, its first end connects the second end of described the 13 resistance, its second end ground connection.
The present invention also provides a kind of method of improving the power factor of circuit of power factor correction, and described circuit of power factor correction comprises: main circuit; Error amplifier carries out producing first signal after error is amplified to the output current/voltage of described main circuit; The drive pulse signal circuit for generating, for generation of drive pulse signal, described drive pulse signal is used for controlling the conducting of the switching tube of described main circuit/shutoff; Described method comprises:
Obtain with described main circuit in the half-sinusoid signal that produces of rectifier with the secondary signal of homophase frequently;
Described first signal and secondary signal stack are produced the 3rd signal;
Described the 3rd signal is transferred to described drive pulse signal circuit for generating, so that described drive pulse signal produces according to described the 3rd signal.
Alternatively, described main circuit comprises:
Rectifier bridge carries out rectification and produces described half-sinusoid signal input signal;
Switching tube, its input connects the positive output end of described rectifier bridge, and its control end receives described drive pulse signal;
The second diode, its negative electrode connects the output of described switching tube, the negative output terminal of the described rectifier bridge of its anodic bonding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
Inductance, its first end connect the second end of described sampling resistor;
Output capacitance, its first end connect the second end of described inductance, and its second end connects the negative output terminal of described rectifier bridge;
Described error amplifier comprises:
The 5th resistance, its first end connects the output of described switching tube;
The second operational amplifier, its negative input end connect the second end of described the 5th resistance, and its output connects the negative input end of described the second operational amplifier via the 4th electric capacity, and its output is exported described first signal;
The first reference voltage source, the one end connects the positive input terminal of described the second operational amplifier, other end ground connection;
Wherein, the inductive current of described inductance of flowing through transfers to described error amplifier, compare with the output voltage of described the first reference voltage source, after being exaggerated, error between the output voltage of the mean value of described inductive current and described the first reference voltage source produces described first signal, when output current diminishes, the mean value of described inductive current is corresponding to be reduced, it is large that described first signal becomes, the 3rd signal that produces after described first signal and the secondary signal stack transfers to described drive pulse signal circuit for generating, after described drive pulse signal circuit for generating is regulated, increase so that transfer to the duty ratio of drive pulse signal of the switch controlled end of described main circuit, so that described output current increases, otherwise when described output current becomes large, the duty ratio of described drive pulse signal reduces, so that described output current reduces.
Alternatively, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input connects the first end of described output capacitance, and the voltage at described output capacitance two ends is carried out zero passage detection;
Saw-tooth wave generating circuit is for generation of sawtooth signal;
The first comparator, its negative input end receive the 3rd signal of described add circuit output, and its positive input terminal receives described sawtooth signal;
Rest-set flip-flop, its set input connects the output of described zero cross detection circuit, and its RESET input connects the output of described the first comparator, and its positive output end is connected to the control end of described switching tube via driver module;
Described saw-tooth wave generating circuit comprises:
Current source;
The 5th electric capacity, its first end connects the output of described current source, its second end ground connection;
Second switch, with described the 5th Capacitance parallel connection, its control end connects the negative output terminal of described rest-set flip-flop;
Wherein, when described sawtooth signal rises to described the 3rd signal, the output level of described the first comparator turn to high level by low level, the drive pulse signal that the positive output end of described rest-set flip-flop is exported is reset to low level, the high level of the simultaneously negative output terminal of described rest-set flip-flop output is controlled described switching tube conducting, with the charge discharging resisting to 0 on described the 5th electric capacity, the level at described the 5th electric capacity two ends is lower than described the 3rd signal, the output level of described the first comparator turn to low level by high level, through twice upset, the output signal of described the first comparator is a narrow pulse signal.
Alternatively, described zero cross detection circuit comprises:
The 6th resistance, its first end connects the first end of described output capacitance;
The 7th resistance, its first end connect the second end of described the 6th resistance, its second end ground connection;
The second comparator, its negative input end connect the second end of described the 6th resistance, and its output connects the set input of described rest-set flip-flop;
The second reference voltage source, the one end connects the positive input terminal of described the second comparator, other end ground connection;
Wherein, shutoff at described switching tube is interval, described inductive current descends, inductive drop is high level, when described inductive current drops to after zero, described inductive drop descends, described inductive drop is transferred to the negative input end of described the second comparator after described the 6th resistance and the 7th electric resistance partial pressure and the voltage of described the second reference voltage source output compares, be lower than the voltage of described the second reference voltage source output when the inductive drop behind described the 6th resistance and the 7th electric resistance partial pressure, the output level of described the second comparator turn to high level by low level, and be high level with the positive output end set of described rest-set flip-flop, so that described switching tube conducting; The voltage that is higher than described the second reference voltage source output when the inductive drop behind described the 6th resistance and the 7th electric resistance partial pressure, the output level of described the second comparator turn to low level by high level, and the output pulse signal of described rest-set flip-flop is transferred to the control end of described switching tube Q1 after driver module amplifies.
Alternatively, described main circuit comprises:
Rectifier bridge carries out rectification and produces described half-sinusoid signal input signal;
Transformer, the Same Name of Ends of its former limit winding connects the positive output end of described rectifier bridge, the Same Name of Ends ground connection of its secondary winding;
Switching tube, its input connect the different name end of described former limit winding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
The 3rd diode, the different name end of the secondary winding of the described transformer of its anodic bonding;
Output capacitance, its first end connects the negative electrode of described the 3rd diode, its second end ground connection;
Wherein, when output voltage diminishes, the first signal of described error amplifier output becomes large, the 3rd signal that produces after described first signal and secondary signal and the secondary signal stack transfers to described drive pulse signal circuit for generating, after described drive pulse signal circuit for generating is regulated so that the duty ratio of described drive pulse signal increase so that the increase of described output voltage; Otherwise, when described output voltage becomes large, after described drive pulse signal circuit for generating is regulated so that the duty ratio of described drive pulse signal reduce so that described output voltage reduces.
Alternatively, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input is connected with the different name end of the auxiliary winding of described transformer, the Same Name of Ends ground connection of described auxiliary winding;
The input voltage sample circuit is sampled to the half-sinusoid signal of described rectifier bridge output;
Multiplier, its first input end connects the output of described input voltage sample circuit, and the second input receives described the 3rd signal;
The 3rd comparator, its negative input end connects the output of described multiplier, and its positive input terminal connects the output of described switching tube;
Rest-set flip-flop, its RESET input connects the output of described the 3rd comparator, and its set input connects the output of described zero cross detection circuit, and its positive output end connects the control end of described switching tube via driver module;
Wherein, the flow through voltage signal that produces behind the described sampling resistor of the electric current of described former limit winding reaches the output signal of described multiplier, the output level of described the 3rd comparator turn to high level by low level, the drive pulse signal that the positive output end of rest-set flip-flop is exported is reset to low level, the electric current of described former limit winding descends afterwards, the voltage signal that produces after the electric current of described former limit winding is flowed through described sampling resistor is lower than the output signal of described multiplier, the output level of described the 3rd comparator turn to low level by high level, through twice upset, the output signal of described the 3rd comparator is a narrow pulse signal.
Alternatively, described zero cross detection circuit comprises:
The 11 resistance, its first end connect the different name end of the ancillary coil of described transformer;
The 12 resistance, its first end connects the second end of described the 11 resistance, its second end ground connection;
The 4th comparator, its negative input end connects the second end of described the 11 resistance, and its positive input terminal connects the first end of the 3rd reference voltage source, and its output connects the set input of described rest-set flip-flop, the second end ground connection of described the 3rd reference voltage source;
Wherein, shutoff at the switching tube of described main circuit is interval, the electric current of described secondary winding descends, the voltage of the auxiliary winding of described transformer is high level, when the electric current of described secondary winding drops to after zero, the voltage of described auxiliary winding is transferred to the negative input end of described the 4th comparator after described the 11 resistance and the 12 electric resistance partial pressure and the voltage of described the 3rd reference voltage source output compares, be lower than the voltage of described the 3rd reference voltage source output when the voltage of voltage behind described the 11 resistance and the 12 electric resistance partial pressure of described auxiliary winding, the output level of described the 4th comparator turn to high level by low level, and be high level with the positive output end set of rest-set flip-flop, so that the switching tube conducting of described main circuit; The voltage Vdc that is higher than described the 3rd reference voltage source output when the voltage of voltage behind described the 11 resistance and the 12 electric resistance partial pressure of described auxiliary winding, the output level of described the 4th comparator turn to low level by high level, and the drive pulse signal of described rest-set flip-flop output transfers to the control end of described main circuit switch pipe after driver module amplifies.
Compared with prior art, the present invention has the following advantages:
The circuit of power factor correction of the embodiment of the invention and improving in the method for power factor, the half-sinusoid signal that at first produces after acquisition and the main circuit rectification is with the secondary signal of frequency homophase, the afterwards first signal stack with this secondary signal and error amplifier generation produces the 3rd signal, and use the 3rd signal to replace the output signal of error amplifier in the traditional power factor correction circuit, the 3rd signal is transferred to the drive pulse signal circuit for generating, so that the conducting of control main circuit switch pipe/drive pulse signal of shutoff is based on the 3rd signal and produces, and the first signal of unconventional error amplifier output.The technical scheme of the embodiment of the invention can be improved the power factor of circuit of power factor correction, and can be applicable to Buck-Boos(or the Flyback of Buck type and critical continuous conduction mode) the type circuit of power factor correction.
Description of drawings
Fig. 1 is the working waveform figure of a kind of Buck type circuit of power factor correction in the prior art;
Fig. 2 is Buck-Boost(or the Flyback of a kind of critical continuous conduction mode in the prior art) normalized input current waveform figure in half power frequency period of type circuit of power factor correction;
Fig. 3 is traditional Buck type circuit of power factor correction and the input current waveform comparison diagram of the Buck type circuit of power factor correction after the embodiment of the invention improvement;
Fig. 4 is Buck-Boost(or the Flyback of traditional critical continuous conduction mode) Buck-Boost(or the Flyback of critical continuous conduction mode after type circuit of power factor correction and the embodiment of the invention are improved) the input current waveform comparison diagram of type circuit of power factor correction;
Fig. 5 shows a kind of signal tracking circuit of the embodiment of the invention;
Fig. 6 shows a kind of circuit structure of the peak-detector circuit shown in Fig. 5;
Fig. 7 shows the another kind of circuit structure of the peak-detector circuit shown in Fig. 5;
Fig. 8 shows the another kind of signal tracking circuit of the embodiment of the invention;
Fig. 9 shows a kind of circuit structure of the low pass filter shown in Fig. 8;
Figure 10 shows the another kind of circuit structure of the low pass filter shown in Fig. 8;
Figure 11 shows the third signal tracking circuit of the embodiment of the invention;
Figure 12 is the circuit diagram of the circuit of power factor correction of first embodiment of the invention;
Figure 13 is the working waveform figure of circuit of power factor correction shown in Figure 12;
Figure 14 is the circuit diagram of the circuit of power factor correction of second embodiment of the invention.
Figure 15 is the working waveform figure of circuit of power factor correction shown in Figure 14.
Embodiment
The invention will be further described below in conjunction with specific embodiments and the drawings, but should not limit protection scope of the present invention with this.
Present embodiment provides a kind of method of improving the power factor of circuit of power factor correction, wherein circuit of power factor correction comprises main circuit, error amplifier and drive pulse signal circuit for generating, error amplifier carries out producing first signal after error is amplified to the output voltage/electric current of main circuit, the drive pulse signal circuit for generating for generation of drive pulse signal with the conducting of the switching tube in the control main circuit/shutoff.In traditional circuit of power factor correction, the first signal of error amplifier output is directly inputted into the drive pulse signal circuit for generating in order to produce drive pulse signal, and in the method for improving power factor of present embodiment, at first obtain secondary signal, the half-sinusoid signal that produces behind over commutation in this secondary signal and the main circuit is with the frequency homophase, the afterwards first signal stack with secondary signal and error amplifier output produces the 3rd signal, again the 3rd signal is transferred to the drive pulse signal circuit for generating, in order to produce drive pulse signal, namely adopt the 3rd signal to replace first signal and transfer to the drive pulse signal circuit for generating.
With reference to figure 3 and Fig. 4, curve 30 is the current on line side waveforms that adopt traditional circuit to obtain among Fig. 3, and curve 31 is the current on line side waveforms that adopt the circuit of power factor correction behind the method improvement that improves power factor of present embodiment to obtain; Curve 40 is the current on line side waveforms that adopt traditional circuit to obtain among Fig. 4, and curve 41 is the current on line side waveforms that adopt the circuit of power factor correction behind the method improvement that improves power factor of present embodiment to obtain.By Fig. 3 and Fig. 4 as seen, adopt the method for improving power factor of present embodiment, Buck-Boost(Flyback for Buck type circuit of power factor correction and critical continuous conduction mode) type circuit of power factor correction, can both change current waveform, so that the more approaching sine wave of net side input current waveform (especially when low input), thereby reduced the harmonic content in the electric current, improved net side power factor.
Furthermore, adopt in the present embodiment signal tracking circuit obtain with main circuit in the half-sinusoid signal that produces of rectification with the secondary signal of homophase frequently.With reference to figure 5, in a specific embodiment, this signal tracking circuit can comprise peak-detector circuit 101, the peak envelope line that is used for obtaining the current i p that flows through the main circuit switch pipe is with as secondary signal vs, for example this peak-detector circuit 101 can be connected to the two ends of sampling resistor Rsen, and this sampling resistor Rsen connects with switching tube.Wherein, the current i p that flows through the main circuit switch pipe can be former limit switching current in Flyback type circuit of power factor correction, can be the electric current that flows through switching tube or flow through inductance in Buck type and Buck-Boost type circuit of power factor correction.
With reference to figure 6, Fig. 6 shows a kind of particular circuit configurations of peak-detector circuit 101, comprising: the first switch S c, its input are as the positive input terminal of peak-detector circuit 101, and its output is as the output of peak-detector circuit 101; The first capacitor C c, its first end connects the output of the first switch S c, its second end ground connection, and as the negative input end of peak-detector circuit 101.
With reference to figure 7, Fig. 7 shows the another kind of particular circuit configurations of peak-detector circuit 101, comprising: the first diode Dc, its anode are as the positive input terminal of peak-detector circuit 101, and its negative electrode is as the output of peak-detector circuit 101; The second capacitor C c, its first end connects the negative electrode of the first diode Dc, its second end ground connection, and as the negative input end of peak-detector circuit 101.
With reference to figure 8, in another specific embodiment, signal tracking circuit can comprise: low pass filter 102 is used for obtaining the mean value of the electric current of the switching tube that flows through main circuit, with as secondary signal Vs.For example low pass filter 102 can be connected to sampling resistor Rsen two ends, and this sampling resistor Rsen connects with switching tube.The current i p that wherein flows through switching tube can be the former limit switching current in the Flyback type circuit of power factor correction, or flows through the electric current of switching tube in Buck type and the Buck-Boost type circuit of power factor correction or flow through the electric current of inductance.
With reference to figure 9, Fig. 9 shows a kind of particular circuit configurations of low pass filter 102, comprise one-level resistance-capacitance low-pass filter circuit, more specifically, this resistance-capacitance low-pass filter circuit comprises: resistance R L, its first end is the positive input terminal of low pass filter 102, and its second end connects the first end of capacitor C L; Capacitor C L, the second end of its first end contact resistance RL, its second end ground connection and as the negative input end of low pass filter 102.
With reference to Figure 10, Figure 10 shows the another kind of particular circuit configurations of low pass filter 102, comprises two-stage resistance-capacitance low-pass filter circuit, and more specifically, this low pass filter 102 comprises: resistance R L1, its first end are the positive input terminal of low pass filter 102; Capacitor C L1, its first end connect the second end of described resistance R L1, its second end ground connection and as the negative input end of low pass filter 102; Resistance R L2, the second end of its first end contact resistance RL1, its second end is as the output of low pass filter 102; Capacitor C L2, the second end of its first end contact resistance RL2, its second end ground connection.
Fig. 9 and low pass filter 102 shown in Figure 10 comprise respectively one-level and two-stage resistance-capacitance low-pass filter circuit, but it will be appreciated by those skilled in the art that low pass filter 102 also can comprise the resistance-capacitance low-pass filter circuit of more multistage mutual cascade.
With reference to Figure 11, in another specific embodiment, signal tracking circuit can comprise: low pass filter 104, and its positive input terminal receives the drive pulse signal Vg that offers main circuit switch pipe control end, its negative input end ground connection; Peak-detector circuit 103, its positive input terminal connects the output of low pass filter 104, its negative input end ground connection; The first resistance R s1, its first end connects the output of low pass filter 104; The second resistance R s2, its first end connects the output of peak-detector circuit 103; The 3rd resistance R s3, its first end connect the second end of the second resistance R s2, its second end ground connection; The first operational amplifier Us, its positive input terminal connects the second end of the first resistance R s1, its negative input end connects the second end of the second resistance R s2, and its output is via the negative input end of the 4th resistance R s4 concatenation operation amplifier Us, and its output is exported secondary signal Vs.
Its operation principle is as follows; Drive pulse signal Vg is through after low pass filter 104 filtering, obtain with main circuit in half-sinusoid signal after the rectification with frequently, anti-phase low frequency signal, this low frequency signal is through obtaining the maximum of this low frequency signal behind the peak-detector circuit 103, the first resistance R s1, the second resistance R s2, the 3rd resistance R s3, the 4th resistance R s4 and the first operational amplifier Us consist of differential amplifier circuit, the output signal of low pass filter 104 and peak-detector circuit 103 is through after this differential amplifier circuit, obtain with the main circuit rectification after the half-sinusoid signal with frequently, the secondary signal Vs of homophase.
Wherein, the particular circuit configurations of low pass filter 104 and peak-detector circuit 103 can with reference to figure 6, Fig. 7, Fig. 9 and Figure 10, repeat no more here.
The secondary signal that signal tracking circuit produces transfers to add circuit, and with the rear tertiary circuit that produces of first signal stack that error amplifier produces, wherein add circuit can be the adder of any structure in the prior art.In addition, the secondary signal that signal tracking circuit produces can at first zoom in or out via ratio circuit, the amplitude of secondary signal is adjusted to transfer in the add circuit after the suitable scope again superpose with first signal.
With reference to Figure 12, Figure 12 shows the circuit structure of the circuit of power factor correction of the first embodiment, this circuit of power factor correction is the Buck type, comprises main circuit, error amplifier 201, signal tracking circuit 204, ratio circuit 205, add circuit 206, drive pulse signal circuit for generating.
Wherein, main circuit comprises: AC power Vac; Rectifier bridge 200 carries out rectification and produces half-sinusoid signal Vin input signal; Switching tube Q 1, its input connects the positive output end of rectifier bridge 200, and its control end receives drive pulse signal; The second diode Do, the output of its negative electrode connecting valve pipe Q1, the negative output terminal of its anodic bonding rectifier bridge 200; Sampling resistor Rsen, the output of its first end connecting valve pipe Q1, its second end ground connection; Inductance L, its first end connects the second end of sampling resistor Rsen; Output capacitance Co, its first end connects the second end of inductance L, and its second end connects the negative output terminal of rectifier bridge 200, and output capacitance Co is configured in parallel with load Rload.
Rectifier bridge 200 comprises: diode D 1, D 2, D 3And D 4, wherein, diode D 1The positive pole of anodic bonding AC power Vac, the input of its negative pole connecting valve pipe Q1; Diode D 2The negative pole of anodic bonding AC power Vac, the input of its negative pole connecting valve pipe Q1; Diode D 3Negative electrode connect the positive pole of AC power Vac; Diode D 4Negative electrode connect the negative pole of AC power Vac, its anodic bonding diode D 3Anode, and as the negative output terminal of rectifier bridge 200.
Error amplifier 201 comprises: the 5th resistance R _ f, the output of its first end connecting valve pipe Q1; The second operational amplifier Uf, its negative input end connect the second end of the 5th resistance R _ f, and its output connects the negative input end of this second operational amplifier Uf via the 4th capacitor C f, its output output first signal Vcomp; The first reference voltage source Vref, the one end connects the positive input terminal of the second operational amplifier Uf, other end ground connection.
The drive pulse signal circuit for generating comprises: zero cross detection circuit 202, and its input connects the first end of output capacitance Co, and the voltage at output capacitance Co two ends is carried out zero passage detection; Saw-tooth wave generating circuit 203 is for generation of sawtooth signal Vsaw; The first comparator Uc1, its negative input end receives the 3rd signal Vcomp2 of add circuit 206 outputs, and its positive input terminal receives sawtooth signal Vsaw; Rest-set flip-flop U RS, its set input connects the output of zero cross detection circuit 202, and its RESET input connects the output of the first comparator Uc1, and its positive output end is connected to the control end of switching tube Q1 via driver module Drv.
Wherein, zero cross detection circuit 202 comprises: the 6th resistance R K2, its first end connects the first end of output capacitance Co; The 7th resistance R K1, its first end connects the 6th resistance R K2The second end, its second end ground connection; The second comparator U C2, its negative input end connects the 6th resistance R K2The second end, its output connects rest-set flip-flop U RSSet input; The second reference voltage source Vdc, one end connect the second comparator U C2Positive input terminal, other end ground connection.
Saw-tooth wave generating circuit 203 comprises: current source I 1The 5th capacitor C 1, its first end connects current source I 1Output, its second end ground connection; Second switch S 1, with the 5th capacitor C 1Parallel connection, its control end connects rest-set flip-flop U RSNegative output terminal.
In the present embodiment, signal tracking circuit 204 comprises low pass filter, its positive input terminal connecting valve pipe Q 1Output, its negative input end ground connection transfers to add circuit 206 after the secondary signal Vs of low pass filter output zooms in or out via ratio circuit 205.Wherein the concrete structure of low pass filter 204 please refer to previously described content.
The working waveform figure of this circuit of power factor correction is elaborated to the operation principle of this circuit of power factor correction below in conjunction with Figure 12 and Figure 13 as shown in figure 13.
Error amplifier 201 is used for realizing the constant current control of output current: the inductive current ip of the main circuit inductance L of flowing through transfers to error amplifier 201, compare error signal (the being first signal) Vcomp that output is amplified after error amplifier 201 amplifies of the error between the mean value of inductive current ip and the first reference voltage source Vref with the first reference voltage source Vref that sets.Because the mean value of inductive current ip equals output current, when output current diminishes, the mean value of inductive current ip also can correspondingly reduce, error between the reference voltage V ref of the mean value of inductive current ip and the first reference voltage source Vref output is amplified through error amplifier 201, so that the output signal Vcomp of error amplifier 201 becomes large, after the drive pulse signal circuit for generating is regulated, so that the duty ratio of the gate driving pulse signal of main circuit switch pipe Q1 increases, thereby so that output current increases, finish closed-loop adjustment, otherwise, when output current becomes large, closed-loop adjustment through error amplifier 201 and drive pulse signal circuit for generating can make output current turn down equally.
Low pass filter 204 and ratio circuit 205 are mainly used to produce the 3rd signal that improves circuit power factor: inductive current ip is after low pass filter 204 filtering, voltage Vin after rectifier bridge 200 rectifications that obtain forming with diode D1, D2, D3 and D4 is with half-sinusoid signal (the being secondary signal) Vs of frequency, homophase, and the error signal Vcomp with error amplifier 201 outputs after ratio circuit 103 zooms in or out produces the 3rd signal Vcomp2 after add circuit 206 stacks.
The saw-tooth wave generating circuit 203 main sawtooth signal Vsaw that produce: 1 charging produces sawtooth signal Vsaw to current source I1 to the 5th capacitor C, touches the 3rd signal Vcomp2, the first comparator U when sawtooth signal Vsaw rises to C1Output level turn to high level by low level, with rest-set flip-flop U RSThe drive pulse signal of anode (Q end) output be reset to low level, U simultaneously RSNegative terminal ( End) the high level control switch pipe Q1 conducting of output is with the 5th capacitor C 1On charge discharging resisting to 0, the 5th capacitor C 1The level at two ends is lower than the 3rd signal Vcomp2, the first comparator U C1Output level turn to low level by high level; So through twice switching process, the first comparator U C1Output signal be a narrow pulse signal.
Zero cross detection circuit 202 is used for detecting the zero crossing of output current, and at the near zero-crossing point of output current that the switching tube Q1 of main circuit is open-minded: the shutoff at main circuit switch pipe Q1 is interval, and inductive current ip descends, inductive drop u LBe high level, as shown in figure 13.When inductive current ip drops to after zero inductive drop u LDescend the voltage u at the inductance L two ends of main circuit LThrough resistance R K2And resistance R K1Be transferred to the second comparator U after the dividing potential drop C2Negative input end and the voltage of reference voltage source Vdc output compare, when through resistance R K2And resistance R K1Inductive drop u after the dividing potential drop LBe lower than the voltage Vdc of reference voltage source Vdc output, comparator U C2Output level turn to high level by low level, and with rest-set flip-flop U RSPositive output end (Q end) set is high level so that main circuit switch pipe Q1 is open-minded; When through resistance R K2And resistance R K1Inductive drop after the dividing potential drop is higher than the voltage Vdc of reference voltage source Vdc output, the second comparator U C2Output level turn to low level by high level; Rest-set flip-flop U RSOutput pulse signal after driver module Drv amplifies, be transferred to the grid (being control end) of main circuit switch pipe Q1 as drive pulse signal.
Such as Figure 12 and shown in Figure 13, if do not have low pass filter 204, ratio circuit 205 and add circuit 206, circuit shown in Figure 12 is the Buck type circuit of power factor correction of the critical continuous conduction mode of traditional permanent ON time control, can realize basic power factor emendation function equally, but the net side input current iac that obtains is shown in the i ' ac among Figure 13, i ' ac has larger harmonic content, causes net side power factor lower.Adopt the circuit structure of present embodiment, by introducing low pass filter 204, ratio circuit 205 and add circuit 206, so that the signal of comparing with saw-tooth wave generating circuit 203 has become the 3rd signal Vcomp2 by first signal Vcomp, drive pulse signal is so that the mode of operation of switching tube Q1 no longer is permanent ON time, but along with input voltage waveform changes, has larger ON time at the crest place, the net side input current iac that obtain this moment is shown in the iac among Figure 13, current waveform approaches sinusoidal, current harmonic content is lower, and net side power factor is improved.
Although in the first embodiment shown in Figure 12, what signal tracking circuit adopted is low pass filter 204, it will be appreciated by those skilled in the art that Fig. 5, Fig. 8 and signal tracking circuit shown in Figure 11 all are applicable to circuit of power factor correction shown in Figure 12.
Figure 14 shows the circuit diagram of the circuit of power factor correction of the second embodiment, this circuit of power factor correction is the anti-excited power factor correcting circuit of single-stage of critical continuous conduction mode control, comprises main circuit, error amplifier 301, signal tracking circuit 304, ratio circuit 305, add circuit 306, drive pulse signal circuit for generating.
Wherein, main circuit comprises: rectifier bridge B 1, input signal is carried out rectification and produces the half-sinusoid signal; Input capacitance Cin, the one end connects rectifier bridge B 1Positive output end, the other end connects rectifier bridge B 1Negative output terminal; Transformer T, the Same Name of Ends of its former limit winding connects rectifier bridge B 1Positive output end, the Same Name of Ends ground connection of its secondary winding; Switching tube Q 1, its input connects the different name end of former limit winding; Sampling resistor Rsen, its first end connecting valve pipe Q 1Output, its second end ground connection; The 3rd diode Do, the different name end of the secondary winding of its anodic bonding transformer; Output capacitance Co, its first end connects the negative electrode of the 3rd diode Do, its second end ground connection, output capacitance Co is configured in parallel with load Rload.
Error amplifier 301 comprises: the 8th resistance R H1, its first end connects the first end of output capacitance Co; The 9th resistance R H2, its first end connects the 8th resistance R H1The second end, its second end ground connection; The tenth resistance R H3, its first end connects the first end of output capacitance Co; The 6th capacitor C K1, its first end connects the 8th resistance R H1The second end; Three end adjustable shunt reference source TL, its plus earth, its negative electrode connects the 6th capacitor C K1The second end, its control end connects the 8th resistance R H1The second end, in the present embodiment, the model of three end adjustable shunt reference source TL is TL431; Optocoupler U K1, its first pin connects the tenth resistance R H3The second end, its crus secunda connects the 6th capacitor C K1The second end, its tripod output first signal Vcomp, its 4th pin ground connection.
The drive pulse signal circuit for generating comprises: zero cross detection circuit 303, and its input is connected with the different name end of the auxiliary winding of transformer T, the Same Name of Ends ground connection of this auxiliary winding; Input voltage sample circuit 302 is to rectifier bridge B 1The half-sinusoid signal of output is sampled; Multiplier U K2, its first input end connects the output of input voltage sample circuit 302, and the second input receives the 3rd signal Vcomp2 of add circuit 306 outputs; The 3rd comparator U C1, its negative input end connects multiplier U K2Output, the output of its positive input terminal connecting valve pipe Q1; Rest-set flip-flop U RS, its RESET input connects the 3rd comparator U C1Output, its set input connects the output of zero cross detection circuit 303, its positive output end is via driver module Drv connecting valve pipe Q 1Control end.
Zero cross detection circuit 303 comprises: the 11 resistance R K2, the different name end of the ancillary coil of its first end connection transformer T; The 12 resistance R K1, its first end connects the 11 resistance R K2The second end, its second end ground connection; The 4th comparator U C2, its negative input end connects the 11 resistance R K2The second end, its positive input terminal connects the first end of the 3rd reference voltage source Vdc, its output connects rest-set flip-flop U RSSet input, the second end ground connection of the 3rd reference voltage source Vdc.
Input voltage sample circuit 302 comprises: the 13 resistance R T1, its first end connects rectifier bridge B 1Positive output end, its second end connects multiplier U K2First input end; The 14 resistance R T2, its first end connects the 13 resistance R T1The second end, its second end ground connection.
In this embodiment, signal tracking circuit 304 comprises peak-detector circuit, its positive input terminal connecting valve pipe Q 1Output, its negative input end ground connection transfers to add circuit 306 after the secondary signal Vs of peak-detector circuit 304 output zooms in or out via ratio circuit 305.Wherein the concrete structure of peak-detector circuit 304 please refer to previously described content.
The working waveform figure of circuit of power factor correction shown in Figure 14 is elaborated to the operation principle of this circuit of power factor correction below in conjunction with Figure 14 and Figure 15 as shown in figure 15.
In Figure 14, error amplifier 301 is used for detecting output voltage, and the variation of output voltage is amplified for voltage stabilizing control.Peak-detector circuit 304 is used for obtaining the envelope of primary current peak value, and error amplification signal (the being first signal) Vcomp of the secondary signal Vs that obtains after ratio circuit 305 ratios zoom in or out and error amplifier 301 outputs superposes by add circuit 306 and obtains the 3rd signal Vcomp2.Input voltage sample circuit 302 is used for obtaining the rectifier bridge B of main circuit 1Half-sinusoid signal after the rectification; Multiplier U K2The half-sinusoid signal of input voltage sample circuit 302 outputs and the 3rd signal Vcomp2 of add circuit 306 outputs are multiplied each other, obtain the reference signal multi that primary current signal ip follows.
Flow through voltage signal that sampling resistor Rsen induces of primary current signal ip reaches the output signal multi of multiplier Uk2, the 3rd comparator U C1Output level turn to high level by low level, with rest-set flip-flop U RSThe drive pulse signal of anode (Q end) output be reset to low level, after this primary current signal ip descends, when flow through voltage signal that sampling resistor Rsen induces of primary current signal ip is lower than the output signal multi of multiplier Uk2, the 3rd comparator U C1Output level turn to low level by high level; So through twice switching process, the 3rd comparator U C1Output signal be a narrow pulse signal.
Zero cross detection circuit 303 is used for detecting the zero crossing of output current, and at the near zero-crossing point of output current that the switching tube Q1 of main circuit is open-minded: the shutoff at main circuit switch pipe Q1 is interval, and secondary current is descends, the auxiliary winding voltage u of transformer AuxBe high level, as shown in figure 15.When secondary current is drops to after zero, transformer is assisted winding voltage u AuxThrough resistance R K2And resistance R K1Be transferred to the 4th comparator U after the dividing potential drop C2Negative input end and the voltage of reference voltage source Vdc output compare, as auxiliary winding voltage u AuxThrough resistance R K2And resistance R K1Voltage after the dividing potential drop is lower than the voltage Vdc of reference voltage source Vdc output, the 4th comparator U C2Output level turn to high level by low level, and with rest-set flip-flop U RSPositive output end (Q end) set is high level so that main circuit switch pipe Q1 is open-minded; As auxiliary winding voltage u AuxThrough resistance R K2And resistance R K1Inductive drop after the dividing potential drop is higher than the voltage Vdc of reference voltage source Vdc output, the 4th comparator U C2Output level turn to low level by high level; Rest-set flip-flop U RSOutput pulse signal after driver module Drv amplifies, be transferred to the grid (being control end) of main circuit switch pipe Q1 as drive pulse signal.
When output voltage diminishes, it is large that the output signal Vcomp of error amplifier 301 becomes, after the drive pulse signal circuit for generating is regulated so that the duty ratio of the drive pulse signal of the grid of the switching tube Q1 of main circuit increase, thereby so that closed-loop adjustment is finished in the output voltage increase; Otherwise when output voltage became large, the closed-loop adjustment through error amplifier 301 and drive pulse signal circuit for generating can make output voltage diminish equally.
As shown in figure 14, if do not have peak-detector circuit 304, ratio circuit 305 and add circuit 306, circuit shown in Figure 14 is that traditional critical continuous conduction mode anti-swashs pfc circuit, can realize basic power factor emendation function equally, but when input voltage is low, net side input current i ' ac will have larger harmonic content, causes net side power factor lower, as shown in figure 15.Adopt the circuit structure of present embodiment, by introducing peak-detector circuit 304, ratio circuit 305 and add circuit 306, can be so that net side input current iac waveform more approaching sine wave when input voltage is low especially, thereby reduction current harmonic content, improve net side power factor, as shown in figure 15.
Although in the second embodiment shown in Figure 14, what signal tracking circuit adopted is peak-detector circuit 204, but it will be appreciated by those skilled in the art that Fig. 5, Fig. 8 and signal tracking circuit shown in Figure 11 all are applicable to circuit of power factor correction shown in Figure 14.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.

Claims (25)

1. a circuit of power factor correction is characterized in that, comprising:
Main circuit;
Error amplifier carries out producing first signal after error is amplified to the output current/voltage of described main circuit;
Signal tracking circuit, for generation of secondary signal, the half-sinusoid signal that rectifier produces in described secondary signal and the described main circuit is with the frequency homophase;
Add circuit will produce the 3rd signal after described first signal and the secondary signal addition;
The drive pulse signal circuit for generating produces drive pulse signal according to described the 3rd signal, and described drive pulse signal is used for controlling the conducting of the switching tube of described main circuit/shutoff.
2. circuit of power factor correction according to claim 1 is characterized in that, described signal tracking circuit comprises:
Peak-detector circuit, the peak envelope line that is used for obtaining the electric current that flows through described switching tube is with as described secondary signal.
3. circuit of power factor correction according to claim 2 is characterized in that, described peak-detector circuit comprises:
The first switch, its input are as the positive input terminal of described peak-detector circuit, and its output is as the output of described peak-detector circuit;
The first electric capacity, its first end connects the output of described the first switch, its second end ground connection and as the negative input end of described peak-detector circuit.
4. circuit of power factor correction according to claim 2 is characterized in that, described peak-detector circuit comprises:
The first diode, its anode are as the positive input terminal of described peak-detector circuit, and its negative electrode is as the output of described peak-detector circuit;
The second electric capacity, its first end connects the negative electrode of described the first diode, its second end ground connection and as the negative input end of described peak-detector circuit.
5. circuit of power factor correction according to claim 1 is characterized in that, described signal tracking circuit comprises:
Low pass filter, the mean value that is used for obtaining the electric current that flows through described switching tube is with as described secondary signal.
6. circuit of power factor correction according to claim 5 is characterized in that, described low pass filter comprises the resistance-capacitance low-pass filter circuit of one-level or plural serial stage.
7. circuit of power factor correction according to claim 1 is characterized in that, described signal tracking circuit comprises:
Low pass filter, its positive input terminal receives described drive pulse signal, its negative input end ground connection;
Peak-detector circuit, its positive input terminal connects the output of described low pass filter, its negative input end ground connection;
The first resistance, its first end connects the output of described low pass filter;
The second resistance, its first end connects the output of described peak-detector circuit;
The 3rd resistance, its first end connect the second end of described the second resistance, its second end ground connection;
The first operational amplifier, its positive input terminal connects the second end of described the first resistance, its negative input end connects the second end of described the second resistance, and its output connects the negative input end of described the first operational amplifier via the 4th resistance, and its output is exported described secondary signal.
8. each described circuit of power factor correction in 7 according to claim 1 is characterized in that, also comprises:
Ratio circuit, described secondary signal transfer to described add circuit after zooming in or out via described ratio circuit.
9. circuit of power factor correction according to claim 1 is characterized in that, described main circuit comprises:
Rectifier bridge carries out rectification and produces described half-sinusoid signal input signal;
Switching tube, its input connects the positive output end of described rectifier bridge, and its control end receives described drive pulse signal;
The second diode, its negative electrode connects the output of described switching tube, the negative output terminal of the described rectifier bridge of its anodic bonding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
Inductance, its first end connect the second end of described sampling resistor;
Output capacitance, its first end connect the second end of described inductance, and its second end connects the negative output terminal of described rectifier bridge.
10. circuit of power factor correction according to claim 9 is characterized in that, described error amplifier comprises:
The 5th resistance, its first end connects the output of described switching tube;
The second operational amplifier, its negative input end connect the second end of described the 5th resistance, and its output connects the negative input end of described the second operational amplifier via the 4th electric capacity, and its output is exported described first signal;
The first reference voltage source, the one end connects the positive input terminal of described the second operational amplifier, other end ground connection.
11. circuit of power factor correction according to claim 9 is characterized in that, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input connects the first end of described output capacitance, and the voltage at described output capacitance two ends is carried out zero passage detection;
Saw-tooth wave generating circuit is for generation of sawtooth signal;
The first comparator, its negative input end receive the 3rd signal of described add circuit output, and its positive input terminal receives described sawtooth signal;
Rest-set flip-flop, its set input connects the output of described zero cross detection circuit, and its RESET input connects the output of described the first comparator, and its positive output end is connected to the control end of described switching tube via driver module.
12. circuit of power factor correction according to claim 11 is characterized in that, described zero cross detection circuit comprises:
The 6th resistance, its first end connects the first end of described output capacitance;
The 7th resistance, its first end connect the second end of described the 6th resistance, its second end ground connection;
The second comparator, its negative input end connect the second end of described the 6th resistance, and its output connects the set input of described rest-set flip-flop;
The second reference voltage source, the one end connects the positive input terminal of described the second comparator, other end ground connection.
13. circuit of power factor correction according to claim 11 is characterized in that, described saw-tooth wave generating circuit comprises:
Current source;
The 5th electric capacity, its first end connects the output of described current source, its second end ground connection;
Second switch, with described the 5th Capacitance parallel connection, its control end connects the negative output terminal of described rest-set flip-flop.
14. circuit of power factor correction according to claim 1 is characterized in that, described main circuit comprises:
Rectifier bridge carries out rectification and produces described half-sinusoid signal input signal;
Transformer, the Same Name of Ends of its former limit winding connects the positive output end of described rectifier bridge, the Same Name of Ends ground connection of its secondary winding;
Switching tube, its input connect the different name end of described former limit winding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
The 3rd diode, the different name end of the secondary winding of the described transformer of its anodic bonding;
Output capacitance, its first end connects the negative electrode of described the 3rd diode, its second end ground connection.
15. circuit of power factor correction according to claim 14 is characterized in that, described error amplifier comprises:
The 8th resistance, its first end connects the first end of described output capacitance;
The 9th resistance, its first end connect the second end of described the 8th resistance, its second end ground connection;
The tenth resistance, its first end connects the first end of described output capacitance;
The 6th electric capacity, its first end connect the second end of described the 8th resistance;
Three end adjustable shunt reference sources, its plus earth, its negative electrode connects the second end of described the 6th electric capacity, and its control end connects the second end of described the 8th resistance;
Optocoupler, its first pin connects the second end of described the tenth resistance, and its crus secunda connects the second end of described the 6th electric capacity, and its tripod is exported described first signal, its 4th pin ground connection.
16. circuit of power factor correction according to claim 14 is characterized in that, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input is connected with the different name end of the auxiliary winding of described transformer, the Same Name of Ends ground connection of described auxiliary winding;
The input voltage sample circuit is sampled to the half-sinusoid signal of described rectifier bridge output;
Multiplier, its first input end connects the output of described input voltage sample circuit, and the second input receives described the 3rd signal;
The 3rd comparator, its negative input end connects the output of described multiplier, and its positive input terminal connects the output of described switching tube;
Rest-set flip-flop, its RESET input connects the output of described the 3rd comparator, and its set input connects the output of described zero cross detection circuit, and its positive output end connects the control end of described switching tube via driver module.
17. circuit of power factor correction according to claim 16 is characterized in that, described zero cross detection circuit comprises:
The 11 resistance, its first end connect the different name end of the ancillary coil of described transformer;
The 12 resistance, its first end connects the second end of described the 11 resistance, its second end ground connection;
The 4th comparator, its negative input end connects the second end of described the 11 resistance, and its positive input terminal connects the first end of the 3rd reference voltage source, and its output connects the set input of described rest-set flip-flop, the second end ground connection of described the 3rd reference voltage source.
18. circuit of power factor correction according to claim 16 is characterized in that, described input voltage sample circuit comprises:
The 13 resistance, its first end connects the positive output end of described rectifier bridge, and its second end connects the first input end of described multiplier;
The 14 resistance, its first end connects the second end of described the 13 resistance, its second end ground connection.
19. a method of improving the power factor of circuit of power factor correction, described circuit of power factor correction comprises: main circuit; Error amplifier carries out producing first signal after error is amplified to the output current/voltage of described main circuit; The drive pulse signal circuit for generating, for generation of drive pulse signal, described drive pulse signal is used for controlling the conducting of the switching tube of described main circuit/shutoff; It is characterized in that described method comprises:
Obtain with described main circuit in the half-sinusoid signal that produces of rectifier with the secondary signal of homophase frequently;
Described first signal and secondary signal stack are produced the 3rd signal;
Described the 3rd signal is transferred to described drive pulse signal circuit for generating, so that described drive pulse signal produces according to described the 3rd signal.
20. method according to claim 19 is characterized in that, described main circuit comprises:
Rectifier bridge carries out rectification and produces described half-sinusoid signal input signal;
Switching tube, its input connects the positive output end of described rectifier bridge, and its control end receives described drive pulse signal;
The second diode, its negative electrode connects the output of described switching tube, the negative output terminal of the described rectifier bridge of its anodic bonding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
Inductance, its first end connect the second end of described sampling resistor;
Output capacitance, its first end connect the second end of described inductance, and its second end connects the negative output terminal of described rectifier bridge;
Described error amplifier comprises:
The 5th resistance, its first end connects the output of described switching tube;
The second operational amplifier, its negative input end connect the second end of described the 5th resistance, and its output connects the negative input end of described the second operational amplifier via the 4th electric capacity, and its output is exported described first signal;
The first reference voltage source, the one end connects the positive input terminal of described the second operational amplifier, other end ground connection;
Wherein, the inductive current of described inductance of flowing through transfers to described error amplifier, compare with the output voltage of described the first reference voltage source, after being exaggerated, error between the output voltage of the mean value of described inductive current and described the first reference voltage source produces described first signal, when output current diminishes, the mean value of described inductive current is corresponding to be reduced, it is large that described first signal becomes, the 3rd signal that produces after described first signal and the secondary signal stack transfers to described drive pulse signal circuit for generating, after described drive pulse signal circuit for generating is regulated, increase so that transfer to the duty ratio of drive pulse signal of the switch controlled end of described main circuit, so that described output current increases, otherwise when described output current becomes large, the duty ratio of described drive pulse signal reduces, so that described output current reduces.
21. method according to claim 19 is characterized in that, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input connects the first end of described output capacitance, and the voltage at described output capacitance two ends is carried out zero passage detection;
Saw-tooth wave generating circuit is for generation of sawtooth signal;
The first comparator, its negative input end receive the 3rd signal of described add circuit output, and its positive input terminal receives described sawtooth signal;
Rest-set flip-flop, its set input connects the output of described zero cross detection circuit, and its RESET input connects the output of described the first comparator, and its positive output end is connected to the control end of described switching tube via driver module;
Described saw-tooth wave generating circuit comprises:
Current source;
The 5th electric capacity, its first end connects the output of described current source, its second end ground connection;
Second switch, with described the 5th Capacitance parallel connection, its control end connects the negative output terminal of described rest-set flip-flop;
Wherein, when described sawtooth signal rises to described the 3rd signal, the output level of described the first comparator turn to high level by low level, the drive pulse signal that the positive output end of described rest-set flip-flop is exported is reset to low level, the high level of the simultaneously negative output terminal of described rest-set flip-flop output is controlled described switching tube conducting, with the charge discharging resisting to 0 on described the 5th electric capacity, the level at described the 5th electric capacity two ends is lower than described the 3rd signal, the output level of described the first comparator turn to low level by high level, through twice upset, the output signal of described the first comparator is a narrow pulse signal.
22. method according to claim 21 is characterized in that, described zero cross detection circuit comprises:
The 6th resistance, its first end connects the first end of described output capacitance;
The 7th resistance, its first end connect the second end of described the 6th resistance, its second end ground connection;
The second comparator, its negative input end connect the second end of described the 6th resistance, and its output connects the set input of described rest-set flip-flop;
The second reference voltage source, the one end connects the positive input terminal of described the second comparator, other end ground connection;
Wherein, shutoff at described switching tube is interval, described inductive current descends, inductive drop is high level, when described inductive current drops to after zero, described inductive drop descends, described inductive drop is transferred to the negative input end of described the second comparator after described the 6th resistance and the 7th electric resistance partial pressure and the voltage of described the second reference voltage source output compares, be lower than the voltage of described the second reference voltage source output when the inductive drop behind described the 6th resistance and the 7th electric resistance partial pressure, the output level of described the second comparator turn to high level by low level, and be high level with the positive output end set of described rest-set flip-flop, so that described switching tube conducting; The voltage that is higher than described the second reference voltage source output when the inductive drop behind described the 6th resistance and the 7th electric resistance partial pressure, the output level of described the second comparator turn to low level by high level, and the output pulse signal of described rest-set flip-flop is transferred to the control end of described switching tube Q1 after driver module amplifies.
23. method according to claim 19 is characterized in that, described main circuit comprises:
Rectifier bridge carries out rectification and produces described half-sinusoid signal input signal;
Transformer, the Same Name of Ends of its former limit winding connects the positive output end of described rectifier bridge, the Same Name of Ends ground connection of its secondary winding;
Switching tube, its input connect the different name end of described former limit winding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
The 3rd diode, the different name end of the secondary winding of the described transformer of its anodic bonding;
Output capacitance, its first end connects the negative electrode of described the 3rd diode, its second end ground connection;
Wherein, when output voltage diminishes, the first signal of described error amplifier output becomes large, the 3rd signal that produces after described first signal and secondary signal and the secondary signal stack transfers to described drive pulse signal circuit for generating, after described drive pulse signal circuit for generating is regulated so that the duty ratio of described drive pulse signal increase so that the increase of described output voltage; Otherwise, when described output voltage becomes large, after described drive pulse signal circuit for generating is regulated so that the duty ratio of described drive pulse signal reduce so that described output voltage reduces.
24. method according to claim 23 is characterized in that, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input is connected with the different name end of the auxiliary winding of described transformer, the Same Name of Ends ground connection of described auxiliary winding;
The input voltage sample circuit is sampled to the half-sinusoid signal of described rectifier bridge output;
Multiplier, its first input end connects the output of described input voltage sample circuit, and the second input receives described the 3rd signal;
The 3rd comparator, its negative input end connects the output of described multiplier, and its positive input terminal connects the output of described switching tube;
Rest-set flip-flop, its RESET input connects the output of described the 3rd comparator, and its set input connects the output of described zero cross detection circuit, and its positive output end connects the control end of described switching tube via driver module;
Wherein, the flow through voltage signal that produces behind the described sampling resistor of the electric current of described former limit winding reaches the output signal of described multiplier, the output level of described the 3rd comparator turn to high level by low level, the drive pulse signal that the positive output end of rest-set flip-flop is exported is reset to low level, the electric current of described former limit winding descends afterwards, the voltage signal that produces after the electric current of described former limit winding is flowed through described sampling resistor is lower than the output signal of described multiplier, the output level of described the 3rd comparator turn to low level by high level, through twice upset, the output signal of described the 3rd comparator is a narrow pulse signal.
25. method according to claim 24 is characterized in that, described zero cross detection circuit comprises:
The 11 resistance, its first end connect the different name end of the ancillary coil of described transformer;
The 12 resistance, its first end connects the second end of described the 11 resistance, its second end ground connection;
The 4th comparator, its negative input end connects the second end of described the 11 resistance, and its positive input terminal connects the first end of the 3rd reference voltage source, and its output connects the set input of described rest-set flip-flop, the second end ground connection of described the 3rd reference voltage source;
Wherein, shutoff at the switching tube of described main circuit is interval, the electric current of described secondary winding descends, the voltage of the auxiliary winding of described transformer is high level, when the electric current of described secondary winding drops to after zero, the voltage of described auxiliary winding is transferred to the negative input end of described the 4th comparator after described the 11 resistance and the 12 electric resistance partial pressure and the voltage of described the 3rd reference voltage source output compares, be lower than the voltage of described the 3rd reference voltage source output when the voltage of voltage behind described the 11 resistance and the 12 electric resistance partial pressure of described auxiliary winding, the output level of described the 4th comparator turn to high level by low level, and be high level with the positive output end set of rest-set flip-flop, so that the switching tube conducting of described main circuit; The voltage Vdc that is higher than described the 3rd reference voltage source output when the voltage of voltage behind described the 11 resistance and the 12 electric resistance partial pressure of described auxiliary winding, the output level of described the 4th comparator turn to low level by high level, and the drive pulse signal of described rest-set flip-flop output transfers to the control end of described main circuit switch pipe after driver module amplifies.
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CN106329906A (en) * 2016-09-18 2017-01-11 浙江芯迈电子科技有限公司 Voltage conversion circuit realizing automatic power factor correction

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