CN102800639A - Mixed integrated packaging structure - Google Patents
Mixed integrated packaging structure Download PDFInfo
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- CN102800639A CN102800639A CN2012101756036A CN201210175603A CN102800639A CN 102800639 A CN102800639 A CN 102800639A CN 2012101756036 A CN2012101756036 A CN 2012101756036A CN 201210175603 A CN201210175603 A CN 201210175603A CN 102800639 A CN102800639 A CN 102800639A
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
The invention discloses a mixed integrated packaging structure. An IC package includes a substrate and an inserter which is arranged on the substrate and is provided with multiple silicon through holes (TSV). An IC bare chip is arranged on the inserter. The IC bare chip is coupled to the substrate via the multiple TSV and a lead bonding assembly.
Description
Technical field
The present invention relates to the integrated circuit encapsulation.
Background technology
Integrated circuit (IC) encapsulation typically comprises the IC nude film that is placed on the substrate.Signal from the IC nude film routes to external circuit through said substrate.Usually, the IC nude film that is installed on the substrate is electrically coupled to said substrate through lead-in wire bonding or upside-down mounting connection.In the lead-in wire bonding, use the electric wire of aluminium, copper or gold that the IC nude film is connected to said substrate.Usually, the side that IC nude film or chip are fabricated at chip has connection gasket, for example soldering projection.
Usually, in wire bond package, route to said substrate via long bonding electric wire from said IC nude film from the signal of IC nude film.The electric wire of this length has higher inductance and crosstalks and signal jitter when signal possibly increase when said IC nude film transfers to external circuit via said lead-in wire bonding connection.Flip-chip packaged has been eliminated the needs that the long electric wire from the IC chip to substrate connects.Do not have long electric wire and connect the total inductance that has reduced in encapsulating, crosstalk and signal jitter thereby reduced by what said higher inductance caused.
For further reduce the power supply noise and to said chip do not hope signal, (on-package decoupling, OPD) the capacitor placement encapsulates interior IC nude film near IC typically will encapsulate decoupling zero.Yet, since make limit, OPD can not put too close said nude film.Therefore, in the time of in more OPD are placed on the IC encapsulation, need bigger substrate to hold all OPD.
Summary of the invention
Therefore, need have and a kind ofly can hold IC nude film and other passive blocks and need not to increase the IC encapsulating structure of the size of said substrate.And, need a kind of encapsulating structure with accurate high speed transmission of signals.Following embodiment has described hybrid integrated circuit (IC) encapsulating structure with inserter.
Should understand this example embodiment can implement with many modes, such as flow process, device, system or equipment.Some creative embodiment of the present invention are described below.
In one embodiment, a kind of IC encapsulation is disclosed.This IC encapsulation comprises substrate and is arranged on the inserter on the substrate.Said inserter has a plurality of silicon through holes (TSV).The IC nude film is arranged on this inserter.This IC nude film is coupled to said substrate through a plurality of TSV with lead-in wire bonding assembly.
In another embodiment, another kind of IC encapsulation is disclosed.This IC encapsulation comprises substrate and inserter.Said inserter has at a plurality of contact mats of first side with from a plurality of TSV of its extension.The first of a plurality of contact mats is coupled to said substrate and a plurality of contact mats through said TSV second portion is coupled to said substrate through lead-in wire bonding assembly.
The method of a kind of IC of encapsulation is disclosed In yet another embodiment.This method comprises inserter is placed on the top surface of substrate.This inserter has a plurality of TSV of a plurality of contact mats that more than first contact mat on the top surface of said inserter are coupled to the basal surface of said inserter.The IC nude film is arranged on the top surface of said inserter then.More than first signal from said IC nude film routes to said substrate through more than first contact mat on the top surface of said inserter.More than second signal from said IC nude film routes to said substrate through more than second contact mat on the top surface of said inserter.Use a plurality of electric wires that more than second contact mat on the top surface of said inserter is coupled to said substrate.
The describing below and combine accompanying drawing, other aspects of the present invention will become obvious of principle of example embodiment is shown through the mode by example.
Description of drawings
Can understand embodiment best with reference to following description in conjunction with the drawings.
Fig. 1 means exemplary and shows lead-in wire bonding IC encapsulation according to an embodiment of the invention without limitation;
Fig. 2 means exemplary and shows the upside-down mounting IC encapsulation with chip capacitor according to an embodiment of the invention without limitation;
Fig. 3 means exemplary and shows the mixing IC encapsulation with inserter according to an embodiment of the invention without limitation;
Fig. 4 means exemplary and unrestricted, and it is the top view of mixing IC according to an embodiment of the invention encapsulation;
Fig. 5 means exemplary and shows exemplary technological process according to an embodiment of the invention without limitation.
Embodiment
Following embodiment has described hybrid integrated circuit (IC) encapsulation with inserter.
Can not need some or whole these details and implement present embodiment yet to those skilled in the art, it is obvious that.In other example, will can not describe known operation in detail in order to avoid unnecessarily fuzzy the present invention.
The embodiments described herein provides the technology of the mixing IC encapsulating structure that is used to comprise inserter.The IC nude film that this inserter comprises the passive block (for example capacitor) of embedding and will be arranged on said inserter one side is coupled to the silicon through hole (TSV) of the substrate that is arranged on said inserter opposite side.In one embodiment, also can use electric wire that said inserter is coupled to said substrate.In this embodiment, the signal from the IC nude film transfers to said substrate through TSV with lead-in wire bonding assembly.
In an example embodiment, the high-speed communication between IC nude film and the said substrate can the communication of relative low speed can be passed through said TSV through going between the bonding assembly.Example embodiment described herein provides the encapsulating structure that mixes, and wherein utilizes lead-in wire bonding assembly and TSV through said inserter the IC nude film to be coupled to said substrate and to have eliminated the needs that the size that increases said nude film is held this function simultaneously.In one embodiment, said mixed structure allows said IC encapsulation to have the density that reduces the improvement of crosstalking
Fig. 1 means exemplary and shows lead-in wire bonding IC encapsulation 100 according to an embodiment of the invention without limitation.IC 102 is arranged on the side of substrate 108.IC 102 uses binding agent 112 to be attached at substrate 108.Binding agent 112 can be the scolder of conductive adhesive or paste form.Molding compounds 115 (for example epoxy resin) sealing IC 102 isolates with other assemblies and moisture and outer member with protection IC 102 with electric wire 110.
A plurality of contact lead-wires or soldered ball 104 can be arranged on the opposite side of said substrate 108.Signal from IC 102 can use soldered ball 104 to be sent to the assembly of IC encapsulation 100 outsides.
Fig. 2 means exemplary and shows the upside-down mounting IC encapsulation 200 with chip capacitor 230 according to an embodiment of the invention without limitation.Should understand other known assemblies (for example, lid, thermal interfacial material (TIM)) and not shown in order to avoid fuzzy present embodiment.
Unlike wire bond package 100, flip-chip packaged 200 can not increased the influence of inductance.Yet, since make limit, a plurality of capacitors 230 can not place too close IC 202.So and since signal required transfer to the inductance of the increase that distance produced of a plurality of capacitors 230 from IC 202, the signals in the IC encapsulation 200 possibly experience shake.
Fig. 3 means exemplary and shows the mixing IC encapsulation 300 with inserter 310 according to an embodiment of the invention without limitation.IC 202 is coupled to substrate 108 through inserter 310.In one embodiment, IC 202 can be microprocessor or programmable logic device (PLD).Said inserter 310 has a plurality of TSV 320 that the IC on the top surface that is arranged on said inserter 310 202 are coupled to said substrate 108.
In one embodiment, the top surface of said inserter 310 has a plurality of contact mats that contact with soldering projection 118.In this embodiment, the basal surface of said inserter 310 comprises the other a plurality of contact mats that contact with soldering projection or contact lead-wire 325.Route to said substrate 108 from the signal of IC 202 through said soldering projection 118, TSV 320 and soldering projection 325.In the embodiments of figure 3, said inserter 310 can comprise the passive block 315 shown in the dotted line, for example capacitor, impedance matching network, equalizing network etc.In exemplary embodiment, said passive block 315 can be the electric capacity of the embedding that is made of metal.According to an embodiment, said passive block 315 can be the film that is placed on the embedding in the inserter 310 as layer.
Still with reference to Fig. 3, the quality of signal possibly passed through TSV 320 and deterioration along with them.In one embodiment, the signal of low bandwidth to Medium-bandwidth can route to said substrate 108 from IC202 through TSV 320.In the mixed structure of Fig. 3, high speed signal (for example HSSI High-Speed Serial Interface (HSSI) signal) can need not to route to said substrate 108 through TSV 320 from said inserter 310 through electric wire 318.In certain embodiments, electric wire 318 is short relatively electric wires, and it is long for example to be less than 3mm.In one embodiment, electric wire 318 can be approximately 1mm length.Short electric wire can help via the high-speed communication of said inserter 310 between IC202 and substrate 108 so that reduce Signal Degrade.
Fig. 4 means exemplary and unrestricted, and it is that the mixing IC as another embodiment according to the present invention encapsulates 300 top view.As shown in the figure, IC 202 is arranged on the inserter 310.The basal surface that should understand said inserter 310 comprises the projection or the contact lead-wire 325 that can be connected directly to said substrate 108.In one embodiment, said inserter 310 comprises the contact mat 402 that is arranged on its top surface, and said top surface faces is arranged on the basal surface of the IC 202 on the said inserter 310.The basal surface that should understand said IC 202 comprises the soldering projection or the contact lead-wire that can be connected directly to said inserter 310, the for example soldering projection among Fig. 2 118.Said pad 402 is used for said inserter 310 is coupled to said substrate 108 with electric wire 318.
In an example embodiment, electric wire 318 is that the lead-in wire bonding connects and helps communicating by letter between IC 202 and said substrate 108 with contact mat 402 with combining, and vice versa.Shown in the embodiment of Fig. 4, the surf zone of inserter 310 can be bigger than the surf zone of IC 202.Therefore, electric wire 318 can be bonded in said inserter 310 top surface the periphery and can be connected to said substrate 108 further.In one embodiment, the thickness of said inserter 310 can be significantly less than the thickness of IC 202.And, the thickness of said inserter 310 can be significantly less than the thickness of said electric wire 318.
Fig. 5 means exemplary and shows without limitation according to the simplification technological process 500 as another embodiment of the present invention.Flow process 500 starts from operating 510, inserter is placed on the top surface of substrate.In one embodiment, said inserter comprises the capacitor of embedding.Said inserter can also comprise the first groups of contact pad on the top surface of said inserter and a plurality of TSV in the corresponding contact pad coupling of the basal surface of said inserter.In step 520, the IC nude film is arranged on the top surface of said inserter.In one embodiment, the IC nude film is the upside-down mounting IC nude film that is similar to the IC 202 shown in the exemplary embodiment of Fig. 3.
In step 530, use one or more parts of the first groups of contact pad and a plurality of TSV that first group of signal routed to said substrate from the IC nude film.In one embodiment, TSV directly is coupled to said substrate with said IC nude film.
In step 540, second group of signal routed to said substrate from the IC nude film.Said second group of signal is through the second groups of contact pad route on the top surface that is arranged on said inserter.In an exemplary embodiment, the said second groups of contact pad can be placed on the periphery of the top surface of said inserter.In step 550, use a plurality of electric wires that the said second groups of contact pad is connected to said substrate then.In one embodiment, be used for the second groups of contact pad on the said inserter is connected to the relative weak point of a plurality of electric wires of said substrate, it is long promptly to be shorter than 3mm.In another embodiment, route to said substrate from the high speed signal of IC nude film through the electric wire that connects said inserter, more the signal of low speed then routes to said substrate through TSV.
It will be understood by those skilled in the art that the flip-chip packaged with BGA is provided in the exemplary of Fig. 2-4.Yet; The use of BGA does not mean restriction, because technology described herein can be applied to other encapsulating structure, and radiator BGA (heat spreader ball grid array for example; HSBGA), little external form BGA (low profile ball grid array; LBGA), thin little spacing BGA (thin fine pitch ball grid array, TFBGA), the encapsulation of flip-chip level (flip chip chip-scale package, FCCSP) etc.
Therefore, up to the present embodiment about integrated circuit has been described.Method and apparatus described herein can merge the circuit that into is fit to arbitrarily.For example, said method and apparatus can merge into the many type equipment such as microcontroller or programmable logic device.Exemplary programmable logic device comprises programmable logic array (PAL), programmable logic array (PLA), field programmable logic array (FPLA), electrically programmable logical device (EPLD), electrically erasable logical device (EEPLD), logical cell array (LCA), field programmable gate array (FPGA), Application Specific Standard Product (ASSP), application-specific integrated circuit (ASIC) (ASIC).Only list some above.
Although described the operation of this method by particular order; But should understand the operation that between the operation described, can carry out other; Can adjust the operation described makes them occur or the operation described that can in system, distribute with slightly different number of times; In said system, as long as the processing of said overlap-add operation can be carried out with the mode of expectation, system promptly allows said processing operation to occur according to the various intervals relevant with said processing.
Although the purpose of understanding from clarification, with some details aforesaid invention has been described, it is obvious that can implement some variation and modification within the scope of the appended claims.Therefore, present embodiment should be regarded as exemplary and nonrestrictive, and the present invention should not be limited to details given here, and can within the scope of said claim and equivalent scope thereof, modify.
Claims (20)
1. IC encapsulation comprises:
Substrate;
Be arranged on the inserter on the said substrate, said inserter comprises a plurality of silicon through hole TSV that extend to the basal surface of said inserter from the top surface of said inserter; And
Be arranged on the IC nude film on the said inserter, wherein said IC nude film is coupled to said substrate through said a plurality of TSV with lead-in wire bonding assembly.
2. integrated circuit encapsulation according to claim 1 further comprises:
Be arranged on a plurality of contact mats on the top surface of said inserter; The first of wherein said a plurality of contact mats is coupled to the corresponding a plurality of contact mats on the basal surface of said inserter through at least one of said a plurality of TSV, and the second portion of wherein said a plurality of contact mats is coupled to said substrate through said lead-in wire bonding assembly.
3. integrated circuit encapsulation according to claim 1, wherein said lead-in wire bonding assembly operationally is used for a plurality of HSSI High-Speed Serial Interface HS of route SI I/O I/O signal between said IC nude film and said substrate.
4. integrated circuit encapsulation according to claim 1, wherein said inserter comprises passive block, wherein said passive block operationally is used for said IC nude film is electrically coupled to said a plurality of TSV.
5. integrated circuit encapsulation according to claim 4, wherein said passive block is selected from the group of following composition: capacitor, impedance matching network and equalizing network, and wherein said passive block is embedded in the said inserter as layer.
6. integrated circuit encapsulation according to claim 1 wherein uses among said a plurality of TSV or the bonding assembly that goes between will route to said substrate from the signal of said IC nude film through said inserter.
7. integrated circuit encapsulation according to claim 1, the surf zone of wherein said inserter is greater than the surf zone of said IC nude film.
8. IC encapsulation comprises:
Substrate;
Inserter; Be included in a plurality of contact mats and a plurality of silicon through hole TSV of first side; Wherein the first of said a plurality of contact mats is coupled to said substrate, and wherein the second portion of said a plurality of contact mats is coupled to said substrate through lead-in wire bonding assembly through said a plurality of TSV.
9. according to Claim 8 integrated circuit encapsulation, wherein said inserter comprises capacitor, wherein said capacitor operationally is used for the IC nude film is electrically coupled to said a plurality of TSV.
10. according to Claim 8 integrated circuit encapsulation further comprises:
Be arranged on the IC nude film of first side of said inserter, wherein said IC nude film be coupled to said substrate through said a plurality of contact mats, said a plurality of TSV and said lead-in wire bonding assembly.
11. integrated circuit encapsulation according to claim 10; Wherein will route to said substrate from the signal with first speed of said IC nude film through said lead-in wire bonding assembly; And wherein through the signal with second speed of said a plurality of TSV routes from said IC nude film, and wherein said first speed is faster than said second speed.
12. the encapsulation of integrated circuit according to Claim 8 further comprises:
Through said TSV a plurality of contact mats on second side of said inserter are coupled to a plurality of contact mats on said first side.
13. the integrated circuit encapsulation according to claim 12 wherein couples directly to said substrate through a plurality of soldering projections with the said a plurality of contact mats on second side of said inserter.
14. the encapsulation of integrated circuit according to Claim 8, wherein said lead-in wire bonding assembly comprises at least one electric wire that is shorter in length than 3mm.
15. the method for an encapsulated integrated circuit IC comprises:
On the top surface of substrate, inserter is set, said inserter comprises a plurality of silicon through hole TSV that are used for more than first contact mat on the top surface of said inserter is coupled to a plurality of contact mats of the basal surface that is arranged on said inserter;
The IC nude film is arranged on the top surface of said inserter;
More than first contact mat through on the top surface of said inserter routes to said substrate with more than first signal from said IC nude film;
More than second contact mat through on the top surface of said inserter routes to said substrate with more than second signal from said IC nude film;
Use a plurality of electric wires that said more than second contact mat on the top surface of said inserter is coupled to said substrate.
16. method according to claim 15 comprises:
In said inserter, embed capacitor.
17. method according to claim 15, wherein said more than second signal are a plurality of high speed I/O I/O signals.
18. it is long that method according to claim 15, each of wherein said a plurality of electric wires are no more than 3mm.
19. method according to claim 15, wherein said a plurality of TSV directly are coupled to said substrate with said IC nude film.
20. method according to claim 15 further comprises: layer is inserted said inserter, and wherein said layer comprises a plurality of passive block networks.
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| US201113117898A | 2011-05-27 | 2011-05-27 | |
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| CN104882417A (en) * | 2014-02-27 | 2015-09-02 | 德州仪器公司 | Integrated Passive Flip Chip Package |
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| CN102800639B (en) | 2016-12-14 |
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