CN102800631B - Method for forming complementary metal oxide semiconductor (CMOS) transistor - Google Patents

Method for forming complementary metal oxide semiconductor (CMOS) transistor Download PDF

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CN102800631B
CN102800631B CN201110139436.5A CN201110139436A CN102800631B CN 102800631 B CN102800631 B CN 102800631B CN 201110139436 A CN201110139436 A CN 201110139436A CN 102800631 B CN102800631 B CN 102800631B
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cmos
ion
territory
formation method
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CN102800631A (en
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三重野文健
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中芯国际集成电路制造(上海)有限公司
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Abstract

The invention discloses a method for forming a complementary metal oxide semiconductor (CMOS) transistor. The method comprises the following steps of: supplying a semiconductor substrate, wherein the semiconductor substrate comprises an N-channel metal oxide semiconductor (NMOS) region, a P-channel metal oxide semiconductor (PMOS) region and an isolation structure for isolating the NMOS region and the PMOS region; forming a dielectric layer with openings on the surface of the semiconductor substrate, wherein the openings are respectively formed in the NMOS region and the PMOS region and expose partial surfaces of the NMOS region and the PMOS region; forming gate dielectric layers on the side walls and at the bottoms of the openings; and doping N-type ions at an interface of the gate dielectric layer in the NMOS region and the semiconductor substrate. By the method for forming the CMOS transistor, threshold voltage of the NMOS transistor can be reduced, and the process is simple and easy to implement.

Description

The transistorized formation method of CMOS

Technical field

Embodiments of the invention relate to semiconductor applications, particularly the transistorized formation method of CMOS.

Background technology

Along with the development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more less.Constantly dwindle in situation in MOS transistor characteristic size, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gates is introduced in MOS transistor.

For the impact on other structures of transistor of the metal material of avoiding metal gates, the gate stack structure of described metal gates and high K gate dielectric layer conventionally adopts grid to substitute (replacement gate) technique and makes.In this technique, before source-drain area injects, first form the sacrificial gate being formed by polysilicon in gate location to be formed, form the source, the drain region that are positioned at described sacrificial gate both sides taking described sacrificial gate as mask.And after forming source-drain area, can remove described sacrificial gate and form gate openings in the position of sacrificial gate, afterwards, then in described gate openings, fill successively high K gate dielectric layer and metal gates.Because metal gates is made after source-drain area has injected again, this is reduced the quantity of subsequent technique, has avoided metal material to be unsuitable for carrying out the problem of high-temperature process.

In actual applications, the device property of PMOS transistor AND gate nmos pass transistor is not identical, and therefore its grid structure need to the threshold voltage demand based on different design.Therefore, in the time adopting described gate replacement technique to make CMOS transistor, need to form respectively the grid of PMOS transistor AND gate nmos pass transistor, that is, CMOS transistor fabrication technique need to be carried out twice grid and be replaced technique, to realize the replacement of sacrificial gate.

US Patent No. 6171910 discloses a kind of employing grid and has replaced the transistorized method of technique making CMOS.Referring to figs. 1 to Fig. 5, show the part flow process of this manufacture method.

As shown in Figure 1, Semiconductor substrate 101 is provided, PMOS district 103 in described Semiconductor substrate 101 forms respectively sacrificial gate electrode structure 107 and source-drain area with nmos area 105, and described sacrificial gate electrode structure comprises pseudo-gate dielectric layer 109, sacrificial gate 111 and hard mask layer 113.

As shown in Figure 2, in described Semiconductor substrate 101, form dielectric protection layer 115, dielectric protection layer 115 described in planarization, until expose sacrificial gate 111 surfaces.

As shown in Figure 3, form the first photoresist layer 117 in described Semiconductor substrate 101, graphical described the first photoresist layer 117, exposes the sacrificial gate surface in PMOS district 103, afterwards, removes described sacrificial gate to form first grid opening 119.

As shown in Figure 4, in described first grid opening, fill grid dielectric material and metal gate material; Afterwards, carry out planarization, the metal gate material retaining at described first grid opening forms the transistorized grid of PMOS, and grid dielectric material forms gate dielectric layer; Meanwhile, described planarization is exposed sacrificial gate 111 surfaces in sacrificial gate electrode structure 107 on nmos area 105.

As shown in Figure 5, the formation technique that is next similar to PMOS transistor gate is made the grid of nmos pass transistor.

But the transistorized threshold voltage of the CMOS forming by said method is larger, a kind of method that reduces threshold voltage is, between gate dielectric layer and gate electrode layer, form function metal level, but the transistorized threshold voltage of CMOS forming is by this method still not little.

Summary of the invention

The problem that embodiments of the invention solve is to provide a kind of transistorized formation method of CMOS, to reduce the threshold voltage of nmos pass transistor.

For addressing the above problem, embodiments of the invention provide a kind of transistorized formation method of CMOS, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises territory, nmos area, PMOS region, the isolation structure of isolating territory, described nmos area and PMOS region;

Form the dielectric layer that contains opening at described semiconductor substrate surface, described opening lays respectively at territory, nmos area and PMOS region, and exposes the part surface in territory, nmos area and PMOS region;

Gate dielectric layer is formed on sidewall and bottom at described opening;

Mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

The step of alternatively, mixing N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate comprises:

Form successively the first function metal level, etching barrier layer, diffusion impervious layer on the surface of described gate dielectric layer;

Form the photoresist layer of filling the opening that is completely positioned at PMOS region;

Mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

Alternatively, the material Nitrogen element of described the first function metal level.

Alternatively, the material of described the first function metal level is titanium nitride, and the material of etching barrier layer is silicon tantalum nitride, and the material of diffusion impervious layer is titanium nitride.

Alternatively, the method of mixing N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate is, adopt bombardment technique to bombard the first function metal level, etching barrier layer, diffusion impervious layer, by the part nitrogen Ions Bombardment in the first function metal level, etching barrier layer, diffusion impervious layer to gate dielectric layer and Semiconductor substrate interface.

Alternatively, described bombardment technique is inert ion bias sputtering technique, bias voltage inert ion plasma bombardment technique or the technique of injecting inert ion.

Alternatively, described inert ion is argon ion.

Alternatively, the parameter of the technique of described inert ion bias sputtering is, frequency 13-14MHz, power 23-27W, air pressure 0.8-1.2mtorr, substrate bias 18-22V.

Alternatively, the parameter of described bias voltage inert ion plasma bombardment technique is frequency 13-14MHz, power 48-52W, air pressure 0.08-0.12torr, argon flow amount 280-320sccm.

Alternatively, adopt and inject the technique of argon ion and bombard the parameter of the first function metal level, etching barrier layer, diffusion impervious layer and be, Implantation Energy 1.8-2.2KeV, implantation dosage 4.8-5.2E13/ square centimeter.

Alternatively, adopt the mode of injecting N-type ion to mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

Alternatively, the N-type ion injecting is any one of As, P, Sb.

Alternatively, the N-type ion injecting is As ion, and the energy of injection is 1.8-2.2KeV, and the dosage of injection is 7.5-8.5E12/ square centimeter.

The step of alternatively, mixing N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate comprises:

Form successively the first function metal level, etching barrier layer, diffusion impervious layer on the surface of described gate dielectric layer;

Form the photoresist layer of filling the opening that is completely positioned at PMOS region;

Removal is positioned at etching barrier layer, the diffusion impervious layer in territory, nmos area;

Mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

Alternatively, the material of described the first function metal level is nitrogenous.

Alternatively, the material of described the first function metal level is that the material of titanium nitride, etching barrier layer is that the material of silicon tantalum nitride, diffusion impervious layer is titanium nitride.

Alternatively, the method of mixing N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate is, adopt bombardment technique to bombard the first function metal level, by the part nitrogen Ions Bombardment in the first function metal level to gate dielectric layer and Semiconductor substrate interface.

Alternatively, described bombardment technique is inert ion bias sputtering technique, bias voltage inert ion plasma bombardment technique or the technique of injecting argon ion.

Alternatively, the inert ion adopting is argon ion.

Alternatively, the parameter of described inert ion bias sputtering technique is, frequency 13-14MHz, power 23-27W, air pressure 0.8-1.2mtorr, substrate bias 18-22V.

Alternatively, the parameter that adopts bias voltage inert ion plasma bombardment technique to bombard the first function metal level is frequency 13-14MHz, power 48-52W, air pressure 0.08-0.12torr, argon flow amount 280-320sccm.

Alternatively, adopt and inject the mode of argon ion and bombard the parameter of the first function metal level and be, Implantation Energy 1.8-2.2KeV, implantation dosage 4.8-5.2E13/ square centimeter.

Alternatively, adopt the mode of injecting N-type ion to mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

Alternatively, the N-type ion injecting is any one of As, P, Sb.

Alternatively, the N-type ion injecting is As ion, and the energy of injection is 1.8-2.2KeV, and the dosage of injection is 7.5-8.5E12/ square centimeter.

Alternatively, also comprise: remove etching barrier layer, the diffusion impervious layer on the gate dielectric layer surface that is positioned at territory, nmos area, and form the second function metal level at the first function layer on surface of metal in territory, nmos area.

Alternatively, be also included in the first function layer on surface of metal that is positioned at territory, nmos area and form the second function metal level, the technique and the inert ion bias sputtering technique that form described the second function metal level are carried out in same equipment.

Alternatively, the material of the second function metal level is nitrogen titanium aluminide.

Compared with prior art, embodiments of the invention have the following advantages: in embodiments of the invention, be positioned at the gate dielectric layer in territory, nmos area and N-type ion is mixed in the interface of Semiconductor substrate, described N-type ion can reduce the electron trap in gate dielectric layer, thereby reduces threshold voltage;

Secondly, embodiments of the invention adopt the method for bombardment to be arranged in the nitrogen Ions Bombardment containing N structure on gate dielectric layer surface to the interface of gate dielectric layer and Semiconductor substrate, and technique is simple, efficiency is high;

The method of embodiments of the invention employing Implantation is the interface to gate dielectric layer and Semiconductor substrate by N-type Implantation, and technique is simple, efficiency is high.

Brief description of the drawings

Fig. 1 to Fig. 5 is the existing generalized section of utilizing grid to replace the transistorized method of technique making CMOS;

Fig. 6 is the schematic flow sheet of the transistorized formation method of CMOS that provides of the first embodiment of the present invention;

Fig. 7 to Figure 11 is the generalized section of the transistorized formation method of CMOS that provides of the first embodiment of the present invention;

Figure 12 is the schematic flow sheet of the transistorized formation method of CMOS that provides of the second embodiment of the present invention.

Embodiment

From background technology, utilize existing technique to be difficult to reduce the transistorized threshold voltage of CMOS, inventor studies this, and provide in an embodiment of the present invention a kind of transistorized formation method of CMOS, comprise: Semiconductor substrate is provided, described Semiconductor substrate is divided into territory, nmos area and PMOS region, between adjacent area, separates with isolation structure; Form the dielectric layer that contains opening at described semiconductor substrate surface, the position of described opening is corresponding with the position of the grid of follow-up formation; Gate dielectric layer is formed on sidewall and bottom at described opening; Mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in detail.

Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.

The first embodiment

Fig. 6 is the schematic flow sheet of the transistorized formation method of CMOS that provides of the first embodiment of the present invention, comprising:

Step S101, provides Semiconductor substrate, and described Semiconductor substrate comprises territory, nmos area, PMOS region, the isolation structure of isolating territory, described nmos area and PMOS region;

Step S102, forms the dielectric layer that contains opening at described semiconductor substrate surface, described opening lays respectively at territory, nmos area and PMOS region, and exposes the part surface in territory, nmos area and PMOS region;

Step S103, forms gate dielectric layer, the first function metal level, etching barrier layer, diffusion impervious layer successively in sidewall and the bottom of described opening;

Step S104, forms the photoresist layer of filling the opening that is completely positioned at PMOS region;

Step S105, mixes N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

With reference to figure 7, Semiconductor substrate 200 is provided, described Semiconductor substrate comprises territory, nmos area 20, PMOS region 10, isolates the isolation structure in territory, described nmos area 20 and PMOS region 10.

In the present embodiment, described Semiconductor substrate 200 is existing Semiconductor substrate, such as silicon substrate, and SOI substrate etc.

In the present embodiment, between adjacent area, separate with fleet plough groove isolation structure, in territory, described nmos area 20, be formed with p-type dopant well, and be positioned at source, the drain region of p-type dopant well N-shaped; In described PMOS region 10, be formed with N-shaped dopant well, and be positioned at p-type source, the drain region of N-shaped dopant well.

With reference to figure 8, form on described Semiconductor substrate 200 surfaces the dielectric layer 210 that contains opening 30 and 40, described opening 30 and 40 lays respectively at PMOS region 10 and territory, nmos area 20, and exposes the part surface in territory, nmos area 20 and PMOS region 10;

In the present embodiment, the material of described dielectric layer 210 is silicon dioxide, and described opening can utilize existing grid to replace technique and form.Particularly, comprising: form respectively replacement gate structure and source, drain region in territory, nmos area 20 and PMOS region 10; Form the dielectric layer that covers described replacement gate structure at semiconductor substrate surface, and described dielectric layer is carried out to planarization, until expose described replacement gate structure; Remove the replacement gate structure forming, form opening, its split shed 30 is positioned at PMOS region 10, and opening 40 is positioned at territory, nmos area 20.Because grid is replaced technique and is well known to those skilled in the art, so be not described in detail in this.

With reference to figure 9, form successively gate dielectric layer 220, the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250 in sidewall and the bottom of described opening 30,40.

In the present embodiment, the material of described gate dielectric layer 220 is high k materials, and as an embodiment, the material of described gate dielectric layer 220 is hafnium oxide.Form the problem that gate dielectric layer can prevent from forming in the corner of the metal gates of follow-up formation leakage current in the sidewall of opening and bottom.In other embodiments, described gate dielectric layer 220 also can only be formed on the bottom of opening.

In the present embodiment, the material of described the first function metal level 230 is titanium nitrides, and described the first function metal level 230 is for regulating the transistorized threshold voltage of PMOS.

In the present embodiment, the material of described etching barrier layer 240 is silicon tantalum nitride (TaSiN), and the effect of described etching barrier layer 240 is in the time that follow-up removal is positioned at the diffusion impervious layer in territory, nmos area, and the first function metal level 230 is protected.

In the present embodiment, the material of described diffusion impervious layer 250 is titanium nitrides, the thickness of described diffusion impervious layer 250 need to regulate according to technique, in the process of follow-up formation grid, described diffusion impervious layer 250 prevents that the technogenic influence that forms grid is to the first function metal level 230, and prevents that with this technogenic influence that forms grid is to threshold voltage.

In other embodiments, the material of described the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250 can need to be selected according to technique, only need to meet function as described above.

With reference to Figure 10, form photoresist layer 260 in PMOS region 10, described photoresist layer 260 is filled the opening 30 that is completely positioned at PMOS region 10.

In subsequent technique, will be positioned at the gate dielectric layer 210 in territory, nmos area 20 and N-type ion is mixed in the interface of Semiconductor substrate 220, described photoresist layer 260 forms protection to PMOS region 10, prevents from mixing N-type ion in PMOS region 10.

With reference to Figure 11, be positioned at the gate dielectric layer 220 in territory, nmos area 20 and N-type ion is mixed in the interface of Semiconductor substrate 200.

In one embodiment of the invention, in the method that is positioned at the gate dielectric layer 220 in territory, nmos area 20 and the interface of Semiconductor substrate 200 and mixes N-type ion be, adopt bombardment technique to bombard the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250, the interface by the part nitrogen Ions Bombardment in the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250 to gate dielectric layer 220 and Semiconductor substrate 200.But above-mentioned by the part nitrogen Ions Bombardment in the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250 in the technique of the interface of gate dielectric layer 220 and Semiconductor substrate 200, if the energy of inert ion is too small, the energy that may obtain because of nitrogen ion is too small, and cannot arrive the position of expection; If the energy of inert ion is excessive, may cause damage to gate dielectric layer, so need the strict parameter of controlling technique.

In optional embodiment of the present invention, adopt argon ion bias sputtering technique to bombard the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250.The parameter of the technique of described argon ion bias sputtering is, frequency 13-14MHz, power 23-27W, air pressure 0.8-1.2mtorr, substrate bias 18-22V.As an embodiment, the parameter of the technique of described argon ion bias sputtering is, frequency 13.56MHz, power 25W, air pressure 1mtorr, substrate bias 20V.

In another alternative embodiment of the invention, adopt bias voltage argon ion plasma bombardment the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250.The parameter of described bias voltage argon plasma bombardment technique is frequency 13-14MHz, power 48-52W, air pressure 0.08-0.12torr, argon flow amount 280-320sccm.As an embodiment, the parameter of described bias voltage argon ion plasma bombardment technique is that frequency is 13.56MHZ, power 50W, air pressure 0.1Torr, argon flow amount 300sccm.

In another alternative embodiment of the invention, adopt the technique of injecting argon ion to bombard the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250, injecting the parameter of argon ion is, Implantation Energy 1.8-2.2KeV, implantation dosage 4.8-5.2E13/ square centimeter.As an embodiment, inject the parameter of argon ion and be, Implantation Energy 2keV, implantation dosage 5E13/ square centimeter.

In an embodiment of the present invention, selecting inert element ion the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250, is because the stable chemical nature of inert element, not can with the material generation chemical reaction of substrate surface; Selecting argon ion is because the quality of argon ion is relatively large, can effectively bombard the nitrogen ion in the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250, and meanwhile, technique is simple, and efficiency is high.

It should be noted that, in technical process, must strictly control technological parameter, to guarantee through aforementioned technique, nitrogen ion in the first function metal level 230, etching barrier layer 240, diffusion impervious layer 250 is mainly mixed in the gate dielectric layer 220 in territory, nmos area 20 and the interface of Semiconductor substrate 200, because if too much nitrogen ion is mixed at gate dielectric layer 210, may have influence on the performance of gate dielectric layer 210.

In other embodiments of the invention, can also adopt the method for Implanted n-Type ion to mix N-shaped ion at the gate dielectric layer 220 in territory, nmos area 20 and the interface of Semiconductor substrate 200, such as in an embodiment of the present invention, can inject any one of the N-shaped ions such as As, P, Sb, the parameter of injecting is 1.8-2.2KeV, and the dosage of injection is 7.5-8.5E12/ square centimeter.

As an embodiment, the N-shaped ion injecting is As ion, and the energy of injection is 2KeV, and the dosage of injection is 8E12/ square centimeter.

It should be noted that in the technique of Implanted n-Type ion, need the strict technological parameter of controlling, the N-shaped ion being injected to guarantee is mainly positioned at the interface of gate dielectric layer 220 and Semiconductor substrate 200.

In subsequent technique, also comprise: etching barrier layer 240, the diffusion impervious layer 250 of removing gate dielectric layer 220 surfaces that are positioned at territory, nmos area 20, and form the second function metal level on first function metal level 230 surfaces in territory, nmos area 20, then remove the photoresist layer 260 that is positioned at PMOS region, form the metal gates of filling full described opening 30 and 40.

In optional embodiment of the present invention, can also first remove the photoresist layer 260 that is positioned at PMOS region and etching barrier layer 240, the diffusion impervious layer 250 that is positioned at gate dielectric layer 220 surfaces in territory, nmos area 20, then in a step process on diffusion impervious layer 250 surfaces that are positioned at PMOS region 10, and the first function metal level 230 surface that is positioned at territory, nmos area 20 forms the second function metal levels.Described the first function metal level 230 can regulate the transistorized threshold voltage of PMOS; Described the second function metal level can regulate the threshold voltage of nmos pass transistor.

As an embodiment, the technique and the inert ion bias sputtering technique that form described the second function metal level are carried out in same equipment.

As an embodiment, the material of the second function metal level is nitrogen titanium aluminide.In other embodiments, the material of described the second function metal level can also be other materials that can regulate the threshold voltage of nmos pass transistor.

The second embodiment

Figure 12 is the schematic flow sheet of the transistorized formation method of CMOS that provides of the second embodiment of the present invention, comprising:

Step S201, provides Semiconductor substrate, and described Semiconductor substrate comprises territory, nmos area, PMOS region, the isolation structure of isolating territory, described nmos area and PMOS region;

Step S202, forms the dielectric layer that contains opening at described semiconductor substrate surface, described opening lays respectively at territory, nmos area and PMOS region, and exposes the part surface in territory, nmos area and PMOS region;

Step S203, forms gate dielectric layer, the first function metal level, etching barrier layer, diffusion impervious layer successively in sidewall and the bottom of described opening;

Step S204, forms the photoresist layer of filling the opening that is completely positioned at PMOS region;

Step S205, removes the etching barrier layer, the diffusion impervious layer that are positioned at territory, nmos area;

Step S206, mixes N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

The difference of described the first embodiment and the second embodiment is: in the first embodiment, first mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate, then remove the etching barrier layer, the diffusion impervious layer that are positioned at territory, nmos area; In a second embodiment, first remove the etching barrier layer, the diffusion impervious layer that are positioned at territory, nmos area, then mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.

Other steps of the second embodiment can, with reference to the first embodiment, not repeat them here.

In a second embodiment, in the time that N-type ion is mixed in the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate, only has the first function metal level on gate dielectric layer surface, doping ion is in the process of interface that is impregnated in gate dielectric layer and Semiconductor substrate, the comparison of resistance that need to overcome is little, so the efficiency of doping is higher.

To sum up, embodiments of the invention have the following advantages: in embodiments of the invention, be positioned at the gate dielectric layer in territory, nmos area and N-type ion is mixed in the interface of Semiconductor substrate, described N-type ion can reduce the electron trap in gate dielectric layer, thereby reduces threshold voltage;

Secondly, embodiments of the invention adopt the method for inert element bombardment to be arranged in the nitrogen Ions Bombardment containing N structure on gate dielectric layer surface to the interface of gate dielectric layer and Semiconductor substrate, and technique is simple, efficiency is high;

The method of embodiments of the invention employing Implantation is the interface to gate dielectric layer and Semiconductor substrate by N-type Implantation, and technique is simple, efficiency is high.

Although embodiments of the invention with preferred embodiment openly as above, but it is not for limiting embodiments of the invention, any those skilled in the art are not departing from the spirit and scope of embodiments of the invention, can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to embodiments of the invention technical scheme, therefore, every content that does not depart from embodiments of the invention technical scheme, any simple modification of above embodiment being done according to the technical spirit of embodiments of the invention, equivalent variations and modification, all belong to the protection range of embodiments of the invention technical scheme.

Claims (25)

1. the transistorized formation method of CMOS, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises territory, nmos area, PMOS region, the isolation structure of isolating territory, described nmos area and PMOS region;
Form the dielectric layer that contains opening at described semiconductor substrate surface, described opening lays respectively at territory, nmos area and PMOS region, and exposes the part surface in territory, nmos area and PMOS region;
Gate dielectric layer is formed on sidewall and bottom at described opening;
Mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate, the step of mixing N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate comprises: form successively the first function metal level, etching barrier layer, diffusion impervious layer on the surface of described gate dielectric layer; Form the photoresist layer of filling the opening that is completely positioned at PMOS region; Mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.
2. according to the transistorized formation method of CMOS claimed in claim 1, it is characterized in that, the material of described the first function metal level is titanium nitride, and the material of etching barrier layer is silicon tantalum nitride, and the material of diffusion impervious layer is titanium nitride.
3. according to the transistorized formation method of CMOS claimed in claim 2, it is characterized in that, the method of mixing N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate is, adopt bombardment technique to bombard the first function metal level, etching barrier layer, diffusion impervious layer, by the part nitrogen Ions Bombardment in the first function metal level, etching barrier layer, diffusion impervious layer to gate dielectric layer and Semiconductor substrate interface.
4. according to the transistorized formation method of CMOS claimed in claim 3, it is characterized in that, described bombardment technique is inert ion bias sputtering technique, bias voltage inert ion plasma bombardment technique or the technique of injecting inert ion.
5. according to the transistorized formation method of CMOS claimed in claim 4, it is characterized in that, described inert ion is argon ion.
6. according to CMOS claimed in claim 5 transistorized formation method, it is characterized in that, the parameter of described inert ion bias sputtering technique is, frequency 13-14MHz, power 23-27W, air pressure 0.8-1.2mtorr, substrate bias 18-22V.
7. according to the transistorized formation method of CMOS claimed in claim 5, it is characterized in that, the parameter of described bias voltage inert ion plasma bombardment technique is frequency 13-14MHz, power 48-52W, air pressure 0.08-0.12torr, argon flow amount 280-320sccm.
8. according to the transistorized formation method of CMOS claimed in claim 5, it is characterized in that, adopt the technological parameter that injects argon ion to be, Implantation Energy 1.8-2.2KeV, implantation dosage 4.8-5.2E13/ square centimeter.
9. according to the transistorized formation method of CMOS claimed in claim 1, it is characterized in that, adopt the mode of injecting N-type ion to mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.
10. according to the transistorized formation method of CMOS claimed in claim 9, it is characterized in that, the N-type ion injecting is any one of As, P, Sb.
11. according to the transistorized formation method of CMOS claimed in claim 10, it is characterized in that, the N-type ion injecting is As ion, and the energy of injection is 1.8-2.2KeV, and the dosage of injection is 7.5-8.5E12/ square centimeter.
12. according to CMOS claimed in claim 1 transistorized formation method, it is characterized in that, the step of mixing N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate comprises:
Form successively the first function metal level, etching barrier layer, diffusion impervious layer on the surface of described gate dielectric layer;
Form the photoresist layer of filling the opening that is completely positioned at PMOS region;
Removal is positioned at etching barrier layer, the diffusion impervious layer in territory, nmos area;
Mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.
13. according to the transistorized formation method of the CMOS described in claim 12, it is characterized in that, the material of described the first function metal level is that the material of titanium nitride, etching barrier layer is that the material of silicon tantalum nitride, diffusion impervious layer is titanium nitride.
14. according to the transistorized formation method of the CMOS described in claim 13, it is characterized in that, the method of mixing N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate is, adopt bombardment technique to bombard the first function metal level, by the part nitrogen Ions Bombardment in the first function metal level to gate dielectric layer and Semiconductor substrate interface.
15. according to the transistorized formation method of the CMOS described in claim 14, it is characterized in that, described bombardment technique is inert ion bias sputtering technique, bias voltage inert ion plasma bombardment technique or the technique of injecting argon ion.
16. according to the transistorized formation method of the CMOS described in claim 15, it is characterized in that, the inert ion adopting is argon ion.
17. according to the transistorized formation method of the CMOS described in claim 16, it is characterized in that, the parameter of described inert ion bias sputtering technique is, frequency 13-14MHz, power 23-27W, air pressure 0.8-1.2mtorr, substrate bias 18-22V.
18. according to the transistorized formation method of the CMOS described in claim 16, it is characterized in that, the parameter that adopts bias voltage inert ion plasma bombardment technique to bombard the first function metal level is frequency 13-14MHz, power 48-52W, air pressure 0.08-0.12torr, argon flow amount 280-320sccm.
19. according to the transistorized formation method of the CMOS described in claim 16, it is characterized in that, adopts to inject the mode of argon ion and bombard the parameter of the first function metal level and be, Implantation Energy 1.8-2.2KeV, implantation dosage 4.8-5.2E13/ square centimeter.
20. according to the transistorized formation method of the CMOS described in claim 12, it is characterized in that, adopts the mode of injecting N-type ion to mix N-type ion to the gate dielectric layer in territory, nmos area and the interface of Semiconductor substrate.
21. according to the transistorized formation method of the CMOS described in claim 20, it is characterized in that, the N-type ion injecting is any one of As, P, Sb.
22. according to the transistorized formation method of the CMOS described in claim 20, it is characterized in that, the N-type ion injecting is As ion, and the energy of injection is 1.8-2.2KeV, and the dosage of injection is 7.5-8.5E12/ square centimeter.
23. according to the transistorized formation method of CMOS claimed in claim 1, it is characterized in that, also comprise: remove etching barrier layer, the diffusion impervious layer on the gate dielectric layer surface that is positioned at territory, nmos area, and form the second function metal level at the first function layer on surface of metal in territory, nmos area.
24. according to the transistorized formation method of the CMOS described in claim 4 or 15, it is characterized in that, also be included in the first function layer on surface of metal that is positioned at territory, nmos area and form the second function metal level, the technique and the inert ion bias sputtering technique that form described the second function metal level are carried out in same equipment.
25. according to the transistorized formation method of the CMOS described in claim 24, it is characterized in that, the material of the second function metal level is nitrogen titanium aluminide.
CN201110139436.5A 2011-05-26 2011-05-26 Method for forming complementary metal oxide semiconductor (CMOS) transistor CN102800631B (en)

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