CN102799249B - A kind of computing machine and power control thereof - Google Patents
A kind of computing machine and power control thereof Download PDFInfo
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- CN102799249B CN102799249B CN201110135859.XA CN201110135859A CN102799249B CN 102799249 B CN102799249 B CN 102799249B CN 201110135859 A CN201110135859 A CN 201110135859A CN 102799249 B CN102799249 B CN 102799249B
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Abstract
The embodiment of the invention discloses a kind of computing machine and power control thereof, described computing machine comprises: circuit system, the power control providing the supply unit of power supply supply, connect described supply unit and described circuit system, described power control is used for connecting the power supply supply of described supply unit to described circuit system when starting-up signal produces, and cuts off the power supply supply of described supply unit to described circuit system when off signal produces.According to the technical scheme of the embodiment of the present invention, after computer shutdown, zero electric energy loss can be reached or close to zero electric energy loss.
Description
Technical field
The present invention relates to computer electric power management field, particularly a kind of computing machine and power control thereof.
Background technology
Along with development and the growth in the living standard of science and technology, computing machine has become life, work requisite instrument, and along with the raising of environmental consciousness, and how the power consumption of effective supervisory computer also becomes the field paid close attention to the most.
After computer shutdown, if also insert external power supply, because computing machine also needs to safeguard basic enable logic, then computer system also can consume the electric energy of 0.5W to 10W.In order to better energy-conservation, after being typically employed in shutdown in prior art, pull out external electric supply socket, or by special time-delay closing power supply, the socket that time-delay closing is connected with external power supply after computing machine cuts out.
Inventor finds in the process realizing embodiment of the present invention technical scheme, at least there is following shortcoming in prior art:
Need user's conscious operation when pulling out supply socket after shutdown, all will opening socket power in closedown defensive position dynamic circuit breaker at every turn, not reaching energy-saving effect because often forgeing.Adopt special time-delay closing power source design not to be suitable for the computing machine being provided with common power, if the common power in computing machine is replaced by time-delay closing power supply, then cost is higher.
Summary of the invention
The embodiment of the present invention proposes a kind of computing machine and power control thereof, after computer shutdown, can reach zero electric energy loss or close to zero electric energy loss.
The technical scheme of the embodiment of the present invention is achieved in that
A kind of computing machine, the supply unit comprising circuit system He provide power supply to supply, wherein, also comprises:
Connect the power control of described supply unit and described circuit system, described power control is used for connecting the power supply supply of described supply unit to described circuit system when starting-up signal produces, and cuts off the power supply supply of described supply unit to described circuit system when off signal produces.
Above-mentioned computing machine, wherein, described power control comprises:
Transistor switching circuit, when described transistor switching circuit is opened, connects the power supply supply of described supply unit to described circuit system, when described transistor switching circuit is closed, cuts off the power supply supply of described supply unit to described circuit system;
Control logic circuit, for when starting-up signal produces, controls described transistor switching circuit and opens, and when off signal produces, controls described transistor switching circuit and closes.
Above-mentioned computing machine, wherein, described transistor switching circuit comprises:
4th resistance;
First PMOS transistor, its grid connects the output terminal of described control logic circuit on the one hand, and be connected to described supply unit by described 4th resistance on the other hand, its source electrode connects described supply unit, and its drain electrode connects described circuit system.
Above-mentioned computing machine, wherein, described control logic circuit comprises:
First PNP transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the first resistance, the second resistance and the 3rd resistance;
Described first PNP transistor, its base stage is connected with systematically signal by a switching-on/switching-off device on the one hand, be connected with described supply unit by described first resistance on the other hand, its collector is connected with described supply unit by described second resistance, and its emitter passes through described 3rd resistance and is connected with systematically signal;
Described second nmos pass transistor, its grid is connected with the emitter of described first PNP transistor, and its source electrode is connected with systematically signal, and its drain electrode is connected, as the output terminal of described control logic circuit with the drain electrode of described 3rd nmos pass transistor;
Described 3rd nmos pass transistor, its source electrode is connected with systematically signal, its grid provides system control signal by described circuit system, when described system control signal is high level signal, described 3rd nmos pass transistor is opened, when described system control signal is low level signal, described 3rd nmos pass transistor is closed.
Above-mentioned computing machine, wherein, described circuit system comprises:
System control signal providing unit, for the grid providing system control signal to arrive described 3rd nmos pass transistor, when starting-up signal produces, described system control signal is high level signal, when off signal produces, described system control signal is low level signal.
Above-mentioned computing machine, wherein, described system control signal providing unit is embedded controller EC.
A power control for computing machine, the supply unit that described computing machine comprises circuit system and provides power supply to supply, described power control comprises:
Transistor switching circuit, when described transistor switching circuit is opened, connects the power supply supply of described supply unit to described circuit system, when described transistor switching circuit is closed, cuts off the power supply supply of described supply unit to described circuit system;
Control logic circuit, for when starting-up signal produces, controls described transistor switching circuit and opens, and when off signal produces, controls described transistor switching circuit and closes.
Above-mentioned power control, wherein, described transistor switching circuit comprises:
4th resistance;
First PMOS transistor, its grid connects the output terminal of described control logic circuit on the one hand, and be connected to described supply unit by described 4th resistance on the other hand, its source electrode connects described supply unit, and its drain electrode connects described circuit system.
Above-mentioned power control, wherein, described control logic circuit comprises:
First PNP transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the first resistance, the second resistance and the 3rd resistance;
Described first PNP transistor, its base stage is connected with systematically signal by a switching-on/switching-off device on the one hand, be connected with described supply unit by described first resistance on the other hand, its collector is connected with described supply unit by described second resistance, and its emitter passes through described 3rd resistance and is connected with systematically signal;
Described second nmos pass transistor, its grid is connected with the emitter of described first PNP transistor, and its source electrode is connected with systematically signal, and its drain electrode is connected, as the output terminal of described control logic circuit with the drain electrode of described 3rd nmos pass transistor;
Described 3rd nmos pass transistor, its source electrode is connected with systematically signal, its grid provides system control signal by described circuit system, when described system control signal is high level signal, described 3rd nmos pass transistor is opened, when described system control signal is low level signal, described 3rd nmos pass transistor is closed.
Embodiments of the invention are by arranging power control in a computer, described power control switches on power when starting-up signal produces the power supply supply of device to circuit system, to cut off the electricity supply when off signal produces the power supply supply of device to circuit system, make computing machine after shutdown, zero electric energy loss can be reached or close to zero electric energy loss.And the technical scheme of the embodiment of the present invention does not need the operating habit changing user, also without the need to changing existing power supply architecture, only need to increase a set of motherboard circuit at computing machine, there is the advantage that cost is low, be easy to realization.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the computing machine of the embodiment of the present invention;
Fig. 2 is the structural representation of the power control of the embodiment of the present invention;
Fig. 3 is the physical circuit figure of the power control of the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
With reference to Fig. 1, the computing machine of the embodiment of the present invention comprises, supply unit 10, power control 20 and circuit system 30, wherein:
Described supply unit 10, for providing power supply supply.
Described power control 20, for connecting the power supply supply of described supply unit 10 to described circuit system 30 when starting-up signal produces, cuts off the power supply supply of described supply unit 10 to described circuit system 30 when off signal produces.
Circuit system 30, starts working after providing power supply supply by described supply unit 10.
In the prior art, supply unit is directly connected with circuit system, after computer shutdown, owing to also needing to safeguard basic enable logic, therefore supply unit does not stop providing power supply supply to circuit system, and is to provide a 5Vstandby voltage to described circuit system, carries out work with the enable logic part maintained in circuit system, like this, certain electric energy will be expended.
And the technique scheme of the embodiment of the present invention, also power control is connected with in supply unit and circuit system, after computer shutdown, described power control has cut off the power supply supply of described supply unit to described circuit system, reaches zero electric energy loss or close to zero electric energy loss.Further, after computer booting, the power supply supply of described supply unit to described circuit system connected by described power control, and like this, the enable logic part in circuit system can be resumed work, and completes the normal startup of computing machine.
With reference to Fig. 2, the power control 20 of the embodiment of the present invention comprises:
Transistor switching circuit 22, when described transistor switching circuit 22 is opened, connect the power supply supply of described supply unit 10 to described circuit system 30, when described transistor switching circuit 22 is closed, cut off the power supply supply of described supply unit 10 to described circuit system 30;
Control logic circuit 21, for when starting-up signal produces, controls described transistor switching circuit 22 and opens, and when off signal produces, controls described transistor switching circuit 22 and closes.
Being more than a kind of specific implementation of power control 20, in this implementation, is control switching on or off between supply unit 10 and circuit system 30 by a transistor switching circuit 22.And opening or closing of transistor switching circuit 22 is controlled by control logic circuit 21, particularly, control logic circuit 21 can be monitored the machine open/close signal of system, when monitoring starting-up signal, control described transistor switching circuit 22 to open, when monitoring off signal, controlling described transistor switching circuit 22 and closing.
Fig. 3 is the physical circuit figure of the power control of the embodiment of the present invention.With reference to Fig. 3, in this physical circuit, described transistor switching circuit 22 comprises:
4th resistance SR4;
First PMOS transistor PQ1, the output terminal of its grid one side connection control logical circuit 21, be connected to described supply unit 10 by described 4th resistance SR4 on the other hand, its source electrode connects described supply unit 10, and its drain electrode connects described circuit system 30.
Its principle of work is: when the output terminal of control logic circuit 21 is low level signal, then the grid of the first PMOS transistor PQ1 is provided with low level signal, so the first PMOS transistor PQ1 opens (conducting), supply unit 10 starts to carry out power supply supply to circuit system 30;
When the output terminal of control logic circuit 21 is high level signal, then the grid of the first PMOS transistor PQ1 is provided with high level signal, so the first PMOS transistor PQ1 closes, and supply unit 10 stops carrying out power supply supply to circuit system 30.
Continue with reference to Fig. 3, in this physical circuit, described control logic circuit 21 comprises:
First PNP transistor SQ1, the second nmos pass transistor SQ2, the 3rd nmos pass transistor SQ3, the first resistance SR1, the second resistance SR2 and the 3rd resistance SR3;
Described first PNP transistor SQ1, it (is a switch in figure that its base stage passes through a switching-on/switching-off device PBTN on the one hand, corresponding to opening computer power knob) be connected with systematically signal, be connected with described supply unit 10 by described first resistance SR1 on the other hand, its collector is connected with described supply unit 10 by described second resistance SR2, and its emitter is connected with systematically signal by described 3rd resistance SR3;
Described second nmos pass transistor SQ2, its grid is connected with the emitter of described first PNP transistor SQ1, and its source electrode is connected with systematically signal, and its drain electrode is connected with the drain electrode of described 3rd nmos pass transistor SQ3, as the output terminal on described steering logic electricity 21 tunnels;
Described 3rd nmos pass transistor SQ3, its source electrode is connected with systematically signal, and its grid provides system control signal by described circuit system 30.
Its principle of work is: when described system control signal is high level signal, then the grid of described 3rd nmos pass transistor SQ3 is provided with high level signal, so, described 3rd nmos pass transistor SQ3 opens (conducting), makes the output terminal of control logic circuit 21 be low level signal;
When described system control signal is low level signal, then the grid of described 3rd nmos pass transistor SQ3 is provided with low level signal, so described 3rd nmos pass transistor SQ3 closes, makes the output terminal of control logic circuit 21 be high level signal.
Wherein, in described circuit system, 30 include system control signal providing unit (not shown), for the grid providing system control signal to arrive described 3rd nmos pass transistor SQ3, when described system control signal providing unit monitors starting-up signal, export the grid of high level signal to described 3rd nmos pass transistor SQ3, when described system control signal providing unit monitors off signal, output low level signal is to the grid of described 3rd nmos pass transistor SQ3.
Preferably, described system control signal providing unit is embedded controller (EmbeddedController, EC).Embedded controller in computing machine inherently has the function monitored system switching machine, in the embodiment of the present invention, when this embedded controller monitors starting-up signal, also export the grid of high level signal to described 3rd nmos pass transistor SQ3, when monitoring off signal, also output low level signal is to the grid of described 3rd nmos pass transistor SQ3.
In addition, the PS5V_ALWAYS in Fig. 3 refers to the 5Vstandby voltage that supply unit provides.
Referring to Fig. 3, the switching on and shutting down flow process after adopting the power control of the embodiment of the present invention is described in detail:
-adopt above-mentioned power control after, circuit system is directly connected with supply unit by original, changes into and is connected with the drain electrode of the first PMOS transistor PQ1 by D point, utilize described first PMOS transistor PQ1 to carry out the standby power supply of isolated power supply.
During-start, user presses start power knob PBTN, and continues for some time, such as 0.8s, by the low level causing B point generation one of short duration.
-when B point is low level, due to PS5V_ALWAY continued power, the first PNP transistor SQ1 will be caused to open, and make C point produce high level.
-when C point is high level, the second nmos pass transistor SQ2 will be caused to open, make A point produce low level.
-when A point is low level, the first PMOS transistor PQ1 will be caused to open, and the PS5V_ALWAY of D point and supply unit is connected, and circuit system part starts there is power supply supply.
-circuit system part is started working after having power supply supply, and the duration that user presses PBTN is enough to make the EC in circuit system complete initialization, and starting-up signal detected.
After-EC detects starting-up signal, send high level signal EC-Keep-Power to E point immediately.
-when E point is high level, the 3rd nmos pass transistor SQ3 opens, and makes A point be maintained low level, and then maintenance the first PMOS transistor PQ1 continues to open, thus supply unit can continue to power to circuit system.
-user is by operation system interface (such as Windows interface) shutdown, and EC detects off signal, and the EC-Keep-power signal of E point is moved to low level.
-when E point is low level, the 3rd nmos pass transistor SQ3 closes, and makes A point produce high level.
-when A point is high level, the first PMOS transistor PQ1 closes, and supply unit disconnects the power supply supply of circuit system, and circuit system quits work.
When specific implementation, optional parameter a: Power-down-No-power-mode can be increased in the Basic Input or Output System (BIOS) (BasicInputOutputSystem, BIOS) of mainboard, maintain data with CMOS battery.After user selects Power-down-No-power-mode=Yes, after user normally closes computer by Windows interface, EC can continue to have checked whether that wake events or powerbutton key-press event occur in a period of time, if not there is (such as 30s) in official hour, EC will move low level to EC-Keep-power signal, and then close the first PMOS transistor PQ1, the power supply supply causing circuit system on mainboard all is cut off.
When the circuit shown in Fig. 3 does not work, because this circuit itself does not become electric power loop, remove almost negligible transistor leakage loss, the electrical source consumption of this cover circuit itself is also almost nil.Due to mainboard to electrical source consumption 0A electric current, power supply body will be caused to enter no-powermode, also produce energy consumption hardly.
After user selects power-down-No-power-mode=No, maintenance EC-Keep-power signal is high level by EC, maintains the first PMOS transistor PQ1 and opens, and the power supply supply that on mainboard, circuit system is all will be the same with existing system.
The technical scheme of the embodiment of the present invention can use general ATX power supply, only need the 5Vstandby of PS5V_ALWAY and the ATX power supply in Fig. 3 to connect, by the drain electrode circuit system of script mainboard needing the place connecting PS5V_ALWAY receive the first PMOS transistor PQ1.
The technical scheme of the embodiment of the present invention is also applicable to use the electric power system of outside adaptor or the AIO system of built-in power device.Only need the PS5V_ALWAY in Fig. 3 to be connected with the input end of outside adaptor power supply, by the drain electrode circuit system of script mainboard needing the place connecting PS5V_ALWAY receive the first PMOS transistor PQ1.
In sum, embodiments of the invention are by arranging power control in a computer, described power control switches on power when starting-up signal produces the power supply supply of device to circuit system, to cut off the electricity supply when off signal produces the power supply supply of device to circuit system, make computing machine after shutdown, zero electric energy loss can be reached or close to zero electric energy loss.And the technical scheme of the embodiment of the present invention does not need the operating habit changing user, also without the need to changing existing power supply architecture, only need to increase a set of motherboard circuit at computing machine, there is the advantage that cost is low, be easy to realization.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a computing machine, the supply unit comprising circuit system He provide power supply to supply, is characterized in that, also comprises:
Connect the power control of described supply unit and described circuit system, described power control is used for connecting the power supply supply of described supply unit to described circuit system when starting-up signal produces, and cuts off the power supply supply of described supply unit to described circuit system when off signal produces;
Transistor switching circuit, when described transistor switching circuit is opened, connects the power supply supply of described supply unit to described circuit system, when described transistor switching circuit is closed, cuts off the power supply supply of described supply unit to described circuit system;
Control logic circuit, for when starting-up signal produces, controls described transistor switching circuit and opens, and when off signal produces, controls described transistor switching circuit and closes;
First PNP transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the first resistance, the second resistance and the 3rd resistance;
Described first PNP transistor, its base stage is connected with systematically signal by a switching-on/switching-off device on the one hand, be connected with described supply unit by described first resistance on the other hand, its collector is connected with described supply unit by described second resistance, and its emitter passes through described 3rd resistance and is connected with systematically signal;
Described second nmos pass transistor, its grid is connected with the emitter of described first PNP transistor, and its source electrode is connected with systematically signal, and its drain electrode is connected, as the output terminal of described control logic circuit with the drain electrode of described 3rd nmos pass transistor;
Described 3rd nmos pass transistor, its source electrode is connected with systematically signal, its grid provides system control signal by described circuit system, when described system control signal is high level signal, described 3rd nmos pass transistor is opened, when described system control signal is low level signal, described 3rd nmos pass transistor is closed.
2. computing machine according to claim 1, is characterized in that, described transistor switching circuit comprises:
4th resistance;
First PMOS transistor, its grid connects the output terminal of described control logic circuit on the one hand, and be connected to described supply unit by described 4th resistance on the other hand, its source electrode connects described supply unit, and its drain electrode connects described circuit system.
3. computing machine according to claim 2, is characterized in that, described circuit system comprises:
System control signal providing unit, for the grid providing system control signal to arrive described 3rd nmos pass transistor, when starting-up signal produces, described system control signal is high level signal, when off signal produces, described system control signal is low level signal.
4. computing machine according to claim 3, is characterized in that:
Described system control signal providing unit is embedded controller EC.
5. a power control for computing machine, the supply unit that described computing machine comprises circuit system and provides power supply to supply, it is characterized in that, described power control comprises:
Transistor switching circuit, when described transistor switching circuit is opened, connects the power supply supply of described supply unit to described circuit system, when described transistor switching circuit is closed, cuts off the power supply supply of described supply unit to described circuit system;
Control logic circuit, for when starting-up signal produces, controls described transistor switching circuit and opens, and when off signal produces, controls described transistor switching circuit and closes;
Described control logic circuit comprises:
First PNP transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the first resistance, the second resistance and the 3rd resistance;
Described first PNP transistor, its base stage is connected with systematically signal by a switching-on/switching-off device on the one hand, be connected with described supply unit by described first resistance on the other hand, its collector is connected with described supply unit by described second resistance, and its emitter passes through described 3rd resistance and is connected with systematically signal;
Described second nmos pass transistor, its grid is connected with the emitter of described first PNP transistor, and its source electrode is connected with systematically signal, and its drain electrode is connected, as the output terminal of described control logic circuit with the drain electrode of described 3rd nmos pass transistor;
Described 3rd nmos pass transistor, its source electrode is connected with systematically signal, its grid provides system control signal by described circuit system, when described system control signal is high level signal, described 3rd nmos pass transistor is opened, when described system control signal is low level signal, described 3rd nmos pass transistor is closed.
6. power control according to claim 5, is characterized in that, described transistor switching circuit comprises:
4th resistance;
First PMOS transistor, its grid connects the output terminal of described control logic circuit on the one hand, and be connected to described supply unit by described 4th resistance on the other hand, its source electrode connects described supply unit, and its drain electrode connects described circuit system.
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| CN105589343A (en) * | 2014-11-14 | 2016-05-18 | 西安电子科技大学 | Single-power accurately controllable time switch based on programmable device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1963707A (en) * | 2006-11-24 | 2007-05-16 | 北京中星微电子有限公司 | Apparatus for controlling power supply, method and electron system |
| CN201000602Y (en) * | 2007-01-05 | 2008-01-02 | 鸿富锦精密工业（深圳）有限公司 | Computer shut-down energy-saving circuit |
| CN101593016A (en) * | 2008-05-30 | 2009-12-02 | 鸿富锦精密工业（深圳）有限公司 | Power control circuit |
| CN101626201A (en) * | 2008-07-08 | 2010-01-13 | 鸿富锦精密工业（深圳）有限公司 | Switch power supply circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN201259988Y (en) * | 2008-09-19 | 2009-06-17 | 贾强贵 | Electricity-saving type computer power socket |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1963707A (en) * | 2006-11-24 | 2007-05-16 | 北京中星微电子有限公司 | Apparatus for controlling power supply, method and electron system |
| CN201000602Y (en) * | 2007-01-05 | 2008-01-02 | 鸿富锦精密工业（深圳）有限公司 | Computer shut-down energy-saving circuit |
| CN101593016A (en) * | 2008-05-30 | 2009-12-02 | 鸿富锦精密工业（深圳）有限公司 | Power control circuit |
| CN101626201A (en) * | 2008-07-08 | 2010-01-13 | 鸿富锦精密工业（深圳）有限公司 | Switch power supply circuit |
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