CN102738327A - Semiconductor epitaxial structure and manufacturing method thereof - Google Patents
Semiconductor epitaxial structure and manufacturing method thereof Download PDFInfo
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- CN102738327A CN102738327A CN2011100915030A CN201110091503A CN102738327A CN 102738327 A CN102738327 A CN 102738327A CN 2011100915030 A CN2011100915030 A CN 2011100915030A CN 201110091503 A CN201110091503 A CN 201110091503A CN 102738327 A CN102738327 A CN 102738327A
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Abstract
The present invention relates to a semiconductor epitaxial structure which includes a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially formed on a substrate. The first type semiconductor layer has an upper surface in contact with the active layer, and a surface roughness of the upper surface is less than or equal to 0.005 micron. The invention also relates to a manufacturing method of the semiconductor epitaxial structure.
Description
Technical field
The present invention relates to a kind of semiconductor, relate in particular to a kind of semiconductor epitaxial structure and manufacturing approach.
Background technology
General semiconductor epitaxial structure like the light-emitting diode epitaxial structure, comprises first type semiconductor layer of growing up successively on substrate, the active layer and second type semiconductor layer.Because the influence of crystals growth environment of heap of stone; Influence like temperature, air-flow and pressure; The in uneven thickness and rough surface of first type semiconductor layer at substrate easily causes growing up; Make active layer and the quality of second type semiconductor layer of follow-up growth on this first type semiconductor layer continue the of heap of stone crystalline condition of this first type semiconductor layer, and then influence the quality of last semiconductor epitaxial structure.
Summary of the invention
In view of this, be necessary to provide a kind of improve the quality of epitaxial structure and everywhere wavelength than homogeneous semiconductor epitaxial structure and manufacturing approach.
A kind of semiconductor epitaxial structure comprises first type semiconductor layer, active layer and second type semiconductor layer that are formed on successively on the substrate.This first type semiconductor layer has a upper surface that contacts with active layer, and the surface roughness of this upper surface is less than or equal to 0.005 micron.
A kind of manufacturing approach of semiconductor epitaxial structure, it comprises: a substrate is provided; One first type semiconductor layer of growth on substrate, this first type semiconductor layer has a upper surface away from this substrate, and this upper surface of planarization is so that the surface roughness of this upper surface is less than or equal to 0.005 micron; Active layer of growth on the upper surface of this first type semiconductor layer; This active layer away from the surface of this first type semiconductor layer on the growth one second type semiconductor layer.
Because the upper surface of this first type semiconductor layer is a planarized surface; When the growth active layer; The temperature that this upper surface bore equates that with pressure therefore, the thickness of the active layer of growing up is identical above that; Thereby promoted the quality of this semiconductor epitaxial structure, and the wavelength ratio of final this semiconductor epitaxial structure that forms is more even.And the upper surface of this first type semiconductor layer is a planarized surface, can reduce the defect concentration of this semiconductor epitaxial structure.
Description of drawings
Fig. 1 is the generalized section of the semiconductor epitaxial structure that provides of the embodiment of the invention.
Fig. 2 is the flow chart of the manufacturing approach of the semiconductor epitaxial structure that provides of the embodiment of the invention.
The main element symbol description
| The semiconductor |
100 |
| |
10 |
| |
20 |
| First |
30 |
| |
31 |
| |
40 |
| Second |
50 |
Following embodiment will combine above-mentioned accompanying drawing to further specify the present invention.
Embodiment
The semiconductor epitaxial structure 100 that provides for the embodiment of the invention shown in Figure 1.This semiconductor epitaxial structure 100 comprises the resilient coating that is formed on successively on the substrate 10 20, first type semiconductor layer 30, active layer 40 and second type semiconductor layer 50.
The sapphire substrate 10 is typically (
), silicon carbide (
), silicon (
), gallium arsenide (
), lithium aluminate (
), MgO (
), zinc oxide (
), gallium nitride (
), aluminum nitride (
), or indium nitride (
) and other single-crystal substrates.In the present embodiment, this substrate 10 is a sapphire substrate, and the upper surface of this substrate 10 is a tabular surface.
This resilient coating 20 is formed on the substrate 10.In the present embodiment, this resilient coating 20 is a n type nitride semiconductor layer, and it is used to reduce substrate 10 and follow-up lattice degree of not matching between the epitaxial structure of growing up on the resilient coating 20, and improves follow-up lattice quality.
This first type semiconductor layer 30 is formed on the surface away from this substrate 10 of this resilient coating 20.This first type semiconductor layer 30 has a upper surface 31 away from this substrate 10.In the present embodiment, this upper surface 31 is through planarization, and its surface roughness is less than or equal to 0.005 micron.This substrate 10, this resilient coating 20 and this first type semiconductor layer 30 threes' thickness calibration poor (standard deviation) is all less than one of percentage.Particularly, (Chemical Mechanical Polishing, CMP) upper surface 31 to this first type semiconductor layer 30 carries out planarization, to improve the surface roughness of this first type semiconductor layer 30 through chemical mechanical milling method.This first type semiconductor layer 30 is a n type semiconductor layer; It selects the III hi-nitride semiconductor material for use, like
; 1 ≦ x ≦ 1,1 ≦ y ≦ 1 and N type alloy are like the Si atom.
The active layer (
) 40 formed on the first-type semiconductor layer 30 on the upper surface 31.In the present embodiment; This active layer 40 can be single quantum well or multiple quantum trap, and its material can be
; 0 ≦ x ≦ 1,0 ≦ y ≦ 1.
This second type semiconductor layer 40 is formed on the side away from this substrate 10 of this active layer 30.This second type semiconductor layer 40 is a p type semiconductor layer, like
; 0 ≦ x ≦ 1,0 ≦ y ≦ 1 and P type alloy are like the Mg atom.
Because the upper surface 31 of this first type semiconductor layer 30 is a planarized surface; When growth active layer 40; The temperature that this upper surface 31 is born equates that with pressure therefore, the thickness of the active layer 40 of growing up is identical above that; Thereby promoted the quality of this semiconductor epitaxial structure 100, and the wavelength ratio of final this semiconductor epitaxial structure 100 that forms is more even.And the upper surface 31 of this first type semiconductor layer 30 is a planarized surface, can reduce the defect concentration of this semiconductor epitaxial structure 100.
The manufacturing approach of a kind of semiconductor epitaxial structure that provides for the embodiment of the invention shown in Figure 2.The manufacturing approach of this semiconductor epitaxial structure comprises the steps:
Step 1 a: substrate is provided.Please in the lump referring to shown in Figure 1, this substrate 10 can be sapphire (
), carborundum (
), silicon (
), GaAs (
), lithium metaaluminate (
), magnesia (
), zinc oxide (
), gallium nitride (
), aluminium nitride (
) or indium nitride single crystal substrates such as (
).In the present embodiment, this substrate 10 is for being sapphire substrate.
Step 2: resilient coating of growth on substrate.In the present embodiment, this resilient coating 20 is a n type nitride semiconductor layer, and it is used to reduce substrate 10 and follow-up lattice degree of not matching between the epitaxial structure of growing up on the resilient coating 20.
Step 3: resilient coating away from the surface of this substrate on the growth one first type semiconductor layer, this first type semiconductor layer has a upper surface away from this substrate, this upper surface of planarization.In the present embodiment, the surface roughness of this upper surface 31 is less than or equal to 0.005 micron, and this substrate 10, this resilient coating 20 and this first type semiconductor layer 30 threes' thickness calibration poor (standard deviation) is all less than one of percentage.Usually, (Chemical Mechanical Polishing, CMP) grinding forms the upper surface 31 of this first type semiconductor layer 30 through chemical mechanical milling method.In the present embodiment; This first type semiconductor layer 30 is a n type semiconductor layer; It selects the III hi-nitride semiconductor material for use, like
; 0 ≦ x ≦ 1,0 ≦ y ≦ 1 and N type alloy are like the Si atom.
Step 4: active layer of growth on the upper surface of this first type semiconductor layer.In the present embodiment; This active layer 40 can be single quantum well or multiple quantum trap, and its material can be
; 0 ≦ x ≦ 1,0 ≦ y ≦ 1.
Step 5: this active layer away from the surface of this first type semiconductor layer on the growth one second type semiconductor layer.In the present embodiment; This second type semiconductor layer 40 is a p type semiconductor layer, like
; 0 ≦ x ≦ 1,0 ≦ y ≦ 1 and P type alloy are like the Mg atom.
Because the upper surface 31 of this first type semiconductor layer 30 is a planarized surface; When growth active layer 40; The temperature that this upper surface 31 is born equates that with pressure therefore, the thickness of the active layer 40 of growing up is identical above that; Thereby promoted the quality of this semiconductor epitaxial structure 100, and the wavelength ratio of final this semiconductor epitaxial structure 100 that forms is more even.And the upper surface 31 of this first type semiconductor layer 30 is a planarized surface, can reduce the defect concentration of this semiconductor epitaxial structure 100.
It is understandable that those skilled in the art also can do other variation in spirit of the present invention, as long as it does not depart from technique effect of the present invention and all can.These all should be included within the present invention's scope required for protection according to the variation that the present invention's spirit is done.
Claims (9)
1. semiconductor epitaxial structure; Comprise first type semiconductor layer, active layer and second type semiconductor layer that are formed on successively on the substrate; It is characterized in that this first type semiconductor layer has the upper surface that contacts with active layer, the surface roughness of this upper surface is less than or equal to 0.005 micron.
2. semiconductor epitaxial structure as claimed in claim 1 is characterized in that, the thickness calibration difference of this substrate and this first type semiconductor layer is all less than one of percentage.
3. semiconductor epitaxial structure as claimed in claim 1 is characterized in that, further comprises a resilient coating between this substrate and this first type semiconductor layer.
4. semiconductor epitaxial structure as claimed in claim 1 is characterized in that, the upper surface of this first type semiconductor layer grinds to form surface roughness through chemical mechanical milling method and is less than or equal to 0.005 micron.
5. semiconductor epitaxial structure as claimed in claim 1 is characterized in that, this first type semiconductor layer is a n type semiconductor layer, and this second type semiconductor layer is a p type semiconductor layer.
6. the manufacturing approach of a semiconductor epitaxial structure, it comprises:
A substrate is provided;
One first type semiconductor layer of growth on substrate, this first type semiconductor layer has a upper surface away from this substrate, and this upper surface of planarization is so that the surface roughness of this upper surface is less than or equal to 0.005 micron;
Active layer of growth on the upper surface of this first type semiconductor layer;
This active layer away from the surface of this first type semiconductor layer on the growth one second type semiconductor layer.
7. the manufacturing approach of semiconductor epitaxial structure as claimed in claim 6 is characterized in that, the thickness calibration difference of this substrate and this first type semiconductor layer is all less than one of percentage.
8. the manufacturing approach of semiconductor epitaxial structure as claimed in claim 6 is characterized in that, the upper surface of this first type semiconductor layer grinds to form surface roughness through chemical mechanical milling method and is less than or equal to 0.005 micron.
9. the manufacturing approach of semiconductor epitaxial structure as claimed in claim 6 is characterized in that, this first type semiconductor layer is a n type semiconductor layer, and this second type semiconductor layer is a p type semiconductor layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100915030A CN102738327A (en) | 2011-04-13 | 2011-04-13 | Semiconductor epitaxial structure and manufacturing method thereof |
| TW100113071A TWI463539B (en) | 2011-04-13 | 2011-04-15 | Semiconductor epitaxial structure and making method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100915030A CN102738327A (en) | 2011-04-13 | 2011-04-13 | Semiconductor epitaxial structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102738327A true CN102738327A (en) | 2012-10-17 |
Family
ID=46993467
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100915030A Pending CN102738327A (en) | 2011-04-13 | 2011-04-13 | Semiconductor epitaxial structure and manufacturing method thereof |
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|---|---|
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| TW (1) | TWI463539B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905149A (en) * | 2005-06-13 | 2007-01-31 | 住友电气工业株式会社 | Damage evaluation method of compound semiconductor member |
| CN101140864A (en) * | 2005-09-07 | 2008-03-12 | 硅绝缘体技术有限公司 | Semiconductor heterostructure and method for forming a semiconductor heterostructure |
| CN101241957A (en) * | 2007-02-08 | 2008-08-13 | 大连路美芯片科技有限公司 | Making method for four-element LED |
| WO2010090262A1 (en) * | 2009-02-09 | 2010-08-12 | 住友電気工業株式会社 | Epitaxial wafer, method for manufacturing gallium nitride semiconductor device, gallium nitride semiconductor device and gallium oxide wafer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200840087A (en) * | 2007-03-30 | 2008-10-01 | Dauan Lumei Optoelectronics Corp | Making method for AlGaInP LED |
-
2011
- 2011-04-13 CN CN2011100915030A patent/CN102738327A/en active Pending
- 2011-04-15 TW TW100113071A patent/TWI463539B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905149A (en) * | 2005-06-13 | 2007-01-31 | 住友电气工业株式会社 | Damage evaluation method of compound semiconductor member |
| CN101140864A (en) * | 2005-09-07 | 2008-03-12 | 硅绝缘体技术有限公司 | Semiconductor heterostructure and method for forming a semiconductor heterostructure |
| CN101241957A (en) * | 2007-02-08 | 2008-08-13 | 大连路美芯片科技有限公司 | Making method for four-element LED |
| WO2010090262A1 (en) * | 2009-02-09 | 2010-08-12 | 住友電気工業株式会社 | Epitaxial wafer, method for manufacturing gallium nitride semiconductor device, gallium nitride semiconductor device and gallium oxide wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201241878A (en) | 2012-10-16 |
| TWI463539B (en) | 2014-12-01 |
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Application publication date: 20121017 |