CN102683338B - A kind of low temperature polycrystalline silicon tft array substrate and manufacture method thereof - Google Patents

A kind of low temperature polycrystalline silicon tft array substrate and manufacture method thereof Download PDF

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Publication number
CN102683338B
CN102683338B CN201110270029.8A CN201110270029A CN102683338B CN 102683338 B CN102683338 B CN 102683338B CN 201110270029 A CN201110270029 A CN 201110270029A CN 102683338 B CN102683338 B CN 102683338B
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described
layer
formed
region
photoresist
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CN201110270029.8A
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CN102683338A (en
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马占洁
龙春平
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京东方科技集团股份有限公司
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Abstract

The embodiment of the present invention provides a kind of low temperature polycrystalline silicon tft array substrate and manufacture method thereof, relates to liquid crystal display and displayer manufactures field, decrease patterning processes number of processes, thus simplify manufacturing process, reduce manufacturing cost.Its method is: form cushion on substrate;Described cushion is formed polysilicon layer;Described polysilicon layer is formed the first metal layer, utilize gray tone mask plate or half-penetration type mask plate that described the first metal layer, polysilicon layer are patterned PROCESS FOR TREATMENT, obtain data wire, source electrode, drain electrode and the pattern of polysilicon semiconductor part by a patterning processes.The embodiment of the present invention manufactures for low temperature polycrystalline silicon tft array substrate.

Description

A kind of low temperature polycrystalline silicon tft array substrate and manufacture method thereof

Technical field

The present invention relates to liquid crystal display and displayer manufactures field, particularly relate to A kind of low temperature polycrystalline silicon TFT (Thin Film Transistor, TFT) battle array Row substrate and manufacture method thereof.

Background technology

Due to the defect problem that non-crystalline silicon itself is own, the ON state current caused too much such as defect Low, mobility is low, poor stability, makes it have received restriction in a lot of fields, in order to make up The defect of non-crystalline silicon own, expands the application in association area, LTPS (Low Temperature Poly-Silicon, low temperature polycrystalline silicon) technology arises at the historic moment.

As shown in Figure 1 and Figure 2, low temperature polycrystalline silicon tft array substrate of the prior art manufactures Method includes:

S101, on the substrate 11 formation cushion 12.

S102, processed by for the first time patterning processes, form polysilicon active layer on the buffer layer Figure.

S103, by deposit inorganic materials on the whole surface of polycrystalline silicon active layer pattern, form the One insulating barrier 14.

S104, by second time patterning processes process, form grid line, grid on the insulating layer 15, afterwards polysilicon is doped, the process such as activation forms polysilicon semiconductor active layer 13。

S105, on grid line, grid 15, form the second insulating barrier 16.

S106, processed by third time patterning processes, in the first insulating barrier 14 and the second insulation Form source electrode via 17a, drain via 17b on layer 16, expose active layer 13.

S107, processed by the 4th patterning processes, form data wire, source electrode 18a and drain electrode 18b, wherein, source electrode 18a is connected with active layer 13 by source electrode via 17a, and drain 18b It is connected 13 with active layer by drain via 17b.

S108, on data wire, source electrode 18a and drain electrode 18b, form protective layer 19, and lead to Cross the 5th patterning processes and process formation via above drain electrode 18b, expose drain electrode 18b.

S109, by the 6th patterning processes process formed ITO pixel electrode 20, this ITO Pixel electrode 20 is connected with drain electrode 18b by via.

S110, processed by the 7th patterning processes, substrate is formed planarization layer 21.

As seen from the above, in the manufacture of low temperature polycrystalline silicon tft array substrate in prior art During, the patterning processes amounting at least 7 times need to be utilized to process, manufacturing process is complicated, manufactures Flow process is various, high material consumption, adds process time and processing cost.

Summary of the invention

Embodiments of the invention provide a kind of low temperature polycrystalline silicon tft array substrate and manufacturer thereof Method, decreases patterning processes number of processes, thus simplifies manufacturing process, reduce and be manufactured into This.

For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that

On the one hand, it is provided that a kind of low temperature polycrystalline silicon tft array substrate, including:

Substrate;

It is formed with polysilicon semiconductor active layer on the buffer layer;

It is formed with source electrode, drain electrode on described polysilicon semiconductor active layer;Described source electrode, drain electrode TFT zone is constituted with described polysilicon semiconductor active layer;

It is formed with gate insulation layer in described source electrode, drain electrode;

Grid, grid line it is formed with on described gate insulation layer;

It is formed with protective layer on described grid, grid line;

Being formed with pixel electrode layer on described protective layer, described pixel electrode layer is described by being positioned at Via on protective layer, gate insulation layer is connected with described drain electrode.

Also include:

Before being formed with polysilicon semiconductor active layer, it is formed with buffering on the substrate Layer.

On the other hand, it is provided that the manufacture method of a kind of low temperature polycrystalline silicon tft array substrate, bag Include:

Substrate is formed polysilicon layer;

Described polysilicon layer is formed the first metal layer, utilizes gray tone mask plate or half-penetration type Mask plate is patterned PROCESS FOR TREATMENT to described the first metal layer, polysilicon layer, by for the first time Patterning processes obtains data wire, source electrode, drain electrode and the pattern of polysilicon semiconductor part;

On described gate insulation layer, grid line, grid is formed by second time patterning processes;

The pattern of described source electrode, drain electrode and polysilicon semiconductor part is formed gate insulation layer;

Part between the source of described polysilicon layer, drain electrode is doped process, in order to institute State source, drain electrode forms channel region;

Described grid line, grid form protective layer, by third time patterning processes in described leakage Form via at pole, expose described drain electrode;

Forming pixel electrode layer on described protective layer, described pixel electrode layer passes through described via It is connected with described drain electrode;

Pixel electrode figure is formed by the 4th patterning processes;

Planarization layer figure is formed on the pixel electrode by the 5th patterning processes.

The low temperature polycrystalline silicon tft array substrate of embodiment of the present invention offer and manufacture method thereof, After substrate is formed cushion, coating polysilicon layer and metal level, by HTM or GTM is patterned PROCESS FOR TREATMENT to metal level, polysilicon layer, is obtained by a patterning processes To including data wire, source electrode, drain electrode, the pattern of polysilicon semiconductor part.Relatively prior art Middle first carry out patterning processes and process and obtain polycrystalline silicon active layer pattern, then carry out a structure Figure PROCESS FOR TREATMENT obtains the coupling part of source-drain electrode and active layer, then carries out at a patterning processes For reason obtains source, drain electrode, decrease the PROCESS FOR TREATMENT of exposure, thus reduce complex procedures Degree, decreases layer protective layer, thus reduces complex procedures degree, save material, is shortening Processing cost is reduced while process time.

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below by right In embodiment or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, Accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art From the point of view of, on the premise of not paying creative work, it is also possible to obtain the attached of other according to these accompanying drawings Figure.

Fig. 1 is the flow process signal of the manufacture method of existing low temperature polycrystalline silicon tft array substrate Figure;

Fig. 2 is the structural representation of existing low temperature polycrystalline silicon tft array substrate;

Fig. 3 a is the schematic diagram utilizing gray mask plate to carry out photoresist exposure;

Fig. 3 b is the schematic diagram utilizing half-penetration type mask plate to carry out photoresist exposure;

The manufacture method of the multi-crystal TFT array substrate that Fig. 4 provides for the embodiment of the present invention one Schematic flow sheet;

The first of the multi-crystal TFT array substrate that makes that Fig. 5 A provides for the embodiment of the present invention shows It is intended to;

The second of the multi-crystal TFT array substrate that makes that Fig. 5 B provides for the embodiment of the present invention shows It is intended to;

The 3rd of the multi-crystal TFT array substrate that makes that Fig. 5 C provides for the embodiment of the present invention shows It is intended to;

The 4th of the multi-crystal TFT array substrate that makes that Fig. 5 D provides for the embodiment of the present invention shows It is intended to;

The 5th of the multi-crystal TFT array substrate that makes that Fig. 5 E provides for the embodiment of the present invention shows It is intended to;

The 6th of the multi-crystal TFT array substrate that makes that Fig. 5 F provides for the embodiment of the present invention shows It is intended to;

The 7th of the multi-crystal TFT array substrate that makes that Fig. 5 G provides for the embodiment of the present invention shows It is intended to;

The 8th of the multi-crystal TFT array substrate that makes that Fig. 5 H provides for the embodiment of the present invention shows It is intended to;

The 9th of the multi-crystal TFT array substrate that makes that Fig. 5 I provides for the embodiment of the present invention shows It is intended to;

The tenth of the multi-crystal TFT array substrate that makes that Fig. 5 J provides for the embodiment of the present invention shows It is intended to;

Fig. 5 K makes the 11st of multi-crystal TFT array substrate for what the embodiment of the present invention provided Schematic diagram;

Fig. 5 L makes the 12nd of multi-crystal TFT array substrate for what the embodiment of the present invention provided Schematic diagram;

Fig. 5 M makes the tenth of multi-crystal TFT array substrate for what the embodiment of the present invention provided Three schematic diagrams;

Fig. 5 N makes the 14th of multi-crystal TFT array substrate for what the embodiment of the present invention provided Schematic diagram;

Fig. 5 O makes the 15th of multi-crystal TFT array substrate for what the embodiment of the present invention provided Schematic diagram;

Fig. 5 P makes the 16th of multi-crystal TFT array substrate for what the embodiment of the present invention provided Schematic diagram;

Fig. 5 Q makes the 17th of multi-crystal TFT array substrate for what the embodiment of the present invention provided Schematic diagram;

The manufacture method of the multi-crystal TFT array substrate that Fig. 6 provides for the embodiment of the present invention two Schematic flow sheet;

The manufacture method of the multi-crystal TFT array substrate that Fig. 7 provides for the embodiment of the present invention four Schematic flow sheet.

Detailed description of the invention

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is entered Row clearly and completely describes, it is clear that described embodiment is only a part of embodiment of the present invention, Rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not having Have and make the every other embodiment obtained under creative work premise, broadly fall into present invention protection Scope.

Embodiment one

The manufacture method of the low temperature polycrystalline silicon tft array substrate that the embodiment of the present invention one provides, in order to Illustrate as a example by manufacturing low temperature polycrystalline silicon tft array substrate with gray mask plate (GTM).

First, with reference to Fig. 3 a, the cardinal principle of GTM technique is illustrated.GTM mask plate is By grating effect, make to be exposed on zones of different different through the intensity of light, and make photoresist select The exposure of selecting property, development.Fig. 3 a represent utilize GTM mask plate 21 photoresist is exposed process Process.In GTM mask plate 21, including transparent region 211, zone of opacity 212 and half Transparent region 213.Photoresist 22 is the state after exposure, and wherein, the corresponding GTM in region 221 covers The transparent region 211 of lamina membranacea 21, the zone of opacity 212 of the corresponding GTM mask plate 21 in region 222, The translucent area 213 of the corresponding GTM mask plate 21 in region 223.After photoresist 23 is for development State, wherein, the transparent region 211 of the corresponding GTM mask plate 21 in region 231, region 232 is right Answer the zone of opacity 212 of GTM mask plate 21, the half of the corresponding GTM mask plate 21 in region 233 Transparent region 213.

Referring to Fig. 4, Fig. 5 A~5Q, the embodiment of the present invention one offer is utilized the low temperature of GTM The manufacture method of multi-crystal TFT array substrate illustrates.

S401, on substrate formed cushion.

In order to prevent harmful substance in glass substrate, such as the alkali metal ion shadow to polysilicon layer performance Ring, prerinse to be carried out (Pre-clean) before buffer layer.Concrete, first pass through initial Cleaning (Initial clean) technique realizes the cleaning to glass substrate, cleannes particle≤300ea to be met (particle diameter >=1um).Then, as shown in Figure 5A, use PECVD on glass substrate 51 Formation of deposits cushion 52.

S402, form polysilicon layer on the buffer layer.

As shown in Figure 5 B, use PECVD to deposit one layer of amorphous silicon layer on cushion 52, adopt With high temperature roaster, amorphous silicon layer is carried out dehydrogenating technology process, to prevent from occurring that in crystallization process hydrogen is quick-fried Phenomenon and reduction defect state density effect within crystallization rear film.After dehydrogenating technology completes, carry out LTPS technical process, use laser annealing technique (ELA), crystallization inducing metal technique (MIC), The crystallization means such as solid-phase crystallization technique (SPC) carry out crystallization process to amorphous silicon layer, in buffering Polysilicon layer 53 is formed on layer 52.

S403, form the first metal layer used by data wire, source electrode, drain electrode on the polysilicon layer.

As shown in Figure 5 C, sputtering technology is utilized to deposit the first metal layer 54 on the polysilicon layer.

S404, utilize gray tone mask plate, the first metal layer, polysilicon layer are patterned at technique Reason, obtains data wire, source electrode, drain electrode and polysilicon semiconductor partial pattern by a patterning processes.

As shown in Figure 5 D, the substrate of said structure coats a layer photoetching glue 55, uses GTM afterwards Photoresist 55 is exposed processing by technique.For TFT zone on this GTM mask plate 70, right Answering data wire (not shown), source electrode, the part of drain region is zone of opacity 702, right Region part between Ying Yuan, drain region is translucent area 703.

It is the view of photoresist 55 after above-mentioned exposure, wherein, photoresist as illustrated in figure 5f The zone of opacity 702 of the corresponding GTM mask plate 70 in the region 551 of 55, the region of photoresist 55 The translucent area 703 of 552 corresponding GTM mask plates 70.

For the view of the photoresist 55 after development, wherein, photoresist 55 as described in Fig. 5 G Region 551 region is fully retained for photoresist, the region 552 of photoresist 55 is that photoresist half is protected Staying region, other regions are that region removed completely by photoresist.

Then, as illustrated in fig. 5h, use wet etching (Wet Etch) technique complete to photoresist The first metal layer 54 removing region performs etching, and then uses dry etching (Dry Etch) technique Polysilicon layer 53 is performed etching.

Then, as shown in fig. 5i, process through plasma ashing, by the photoresist of photoresist 55 half The photoresist retaining region 552 etches away, and remaining photoresist is fully retained the photoresist in region 551, This photoresist is fully retained region 551 corresponding source electrode, drain region.

Then, as indicated at figure 5j, then through wet-etching technology photoresist half is retained region 552 The first metal layer 54 carry out secondarily etched.

Then, as it can be seen from figure 5k, after peeling off the photoresist that photoresist is fully retained region 551, Obtain source electrode 542, drain electrode 541.

So far, in the present embodiment, processed by a GTM patterning processes, obtained including data Line, source electrode, drain electrode, the pattern of polysilicon active layer.In relatively prior art, employing first carry out one Secondary patterning processes processes and obtains polycrystalline silicon active layer pattern, then carries out a patterning processes process and obtains Source, drain electrode and the layering of the connecting portion of active layer, then carry out a patterning processes and process and obtain source, drain electrode For, decrease the PROCESS FOR TREATMENT of exposure, thus reduce complex procedures degree, add man-hour shortening Processing cost is reduced while between.

S405, on the pattern of source electrode, drain electrode and polysilicon semiconductor part formed gate insulation layer, it After carry out channel region doping treatment, in order to source, drain electrode formed channel region.

As shown in fig. 5l, on source electrode 541 and drain electrode layer 542, use PECVD deposition grid Insulating barrier 56, then by self-registered technology (Self Align) method, use ion bath or from The mode that son injects, carries out the doping treatment of channel region 531, in order to make channel region 531 and source electrode, Drain region forms P-N junction, makes TFT constitute MOS switch structure.

S406, on gate insulation layer formed grid line, grid.

As shown in figure 5m, on gate insulation layer 56, sputtering technology is used to form the second of grid Metal level, is then processed by second time patterning processes, forms grid line (not shown), grid 57。

S407, formation protective layer (PVX) on grid line, grid.

As shown in Fig. 5 N, on grid 57, use PECVD deposition layer protective layer 58, Protect grid.

S408, on gate insulation layer and protective layer formed connect via.

As shown in Fig. 5 O, processed by third time patterning processes, at gate insulation layer 56 and protective layer Form a connection via 59 ' running through gate insulation layer 56 and protective layer 58 on 58, expose drain electrode 542, For making drain electrode be connected with pixel electrode.

S409, forming pixel electrode layer on the protection layer, pixel electrode layer passes through via and drain electrode Connect.

As shown in Fig. 5 P, PECVD is used to deposit one layer of ITO (Indium Tin on protective layer 58 Oxide, indium tin oxide quasiconductor), then use the 4th patterning processes to process, obtain pixel Electrode 59, pixel electrode 59 is connected with drain electrode 542 by connecting via 59 '.

S410, form planarization layer on the pixel electrode.

As shown in Fig. 5 Q, pixel electrode 59 deposits one layer and plays planarization and protection ITO picture The protective layer 90 of element electrode edge, can use the materials such as synthetic resin (Resin) or insulating barrier, Then the 5th patterning processes is used to form respective graphical.

The manufacture method of the low temperature polycrystalline silicon tft array substrate that the embodiment of the present invention provides, at substrate After upper formation cushion, coating polysilicon layer and metal level, by GTM to metal level, polycrystalline Silicon layer is patterned PROCESS FOR TREATMENT, by patterning processes obtain including data wire, source electrode, drain electrode, The pattern of polysilicon semiconductor part.Relatively prior art first carries out a patterning processes process and obtains many Crystal silicon active layer pattern, then carries out a patterning processes and processes the connection obtaining source-drain electrode with active layer Part, then carry out for patterning processes processes and obtain source, drain electrode, decreasing at the technique of exposure Reason, decreases layer protective layer, thus reduces complex procedures degree, save material, shortening Processing cost is reduced while process time.

Embodiment two

The manufacture method of the low temperature polycrystalline silicon tft array substrate that the embodiment of the present invention two provides, in order to Illustrate as a example by manufacturing low temperature polycrystalline silicon tft array substrate with half-penetration type mask plate (HTM).

First, with reference to Fig. 3 b, the cardinal principle of HTM technique is illustrated.HTM mask plate is By different through the intensity of light in zones of different, and photoresist is made to carry out selectivity exposure, development. Fig. 3 b represents the process utilizing HTM mask plate 31 that photoresist is exposed process.At HTM In mask plate 31, including transparent region 311, zone of opacity 312 and translucent area 313.Light Photoresist 32 is the state after exposure, wherein, and the bright zone of the corresponding HTM mask plate 31 in region 321 Territory 311, the zone of opacity 312 of the corresponding HTM mask plate 31 in region 322, region 323 is corresponding The translucent area 313 of HTM mask plate 31.Photoresist 33 is the state after development, wherein, district The transparent region 311 of the corresponding HTM mask plate 31 in territory 331, the corresponding HTM mask plate in region 332 The zone of opacity 312 of 31, the translucent area 313 of the corresponding HTM mask plate 31 in region 333.

As shown in Figure 6, the present embodiment two, compared with embodiment one, is patterned work except using HTM The step (S 604) that step (S604) and the embodiment one of skill uses GTM to be patterned technique has Outside institute's difference, remaining step is identical with embodiment one.

Including:

S601, on substrate formed cushion.

S602, form polysilicon layer on the buffer layer.

S603, in polysilicon active layer formed source, drain electrode used by the first metal layer.

S604, utilize half-penetration type mask plate, the first metal layer, polysilicon layer are patterned at technique Reason, obtains data wire, source electrode, drain electrode and polysilicon semiconductor partial pattern by a patterning processes.

As shown in fig. 5e (owing to Fig. 5 E with embodiment one is identical, with reference to the phase Radix Aconiti Coreani of embodiment one Scheme), the substrate of said structure coats a layer photoetching glue 55, afterwards by HTM technique pair Photoresist 55 is exposed processing.For TFT zone on this HTM mask plate 80, corresponding source electrode, The part of drain region is zone of opacity 802, and the part of corresponding area of grid is translucent area 803。

(owing to Fig. 5 F with embodiment one is identical, see the phase Radix Aconiti Coreani of embodiment one as illustrated in figure 5f Scheme), for the view of the photoresist 55 after above-mentioned exposure, wherein, photoresist 55 The zone of opacity 802 of the corresponding HTM mask plate 80 in region 551, the region 552 of photoresist 55 The translucent area 803 of corresponding HTM mask plate 80.

As depicted in fig. 5g (owing to Fig. 5 G with embodiment one is identical, being correlated with reference to embodiment one Accompanying drawing), for the view of the photoresist 55 after development, wherein, the district of photoresist 55 Territory 551 is fully retained region for photoresist, and the region 552 of photoresist 55 is photoresist half reserved area Territory, other regions are that region removed completely by photoresist.

Then, as illustrated in fig. 5h (owing to Fig. 5 H with embodiment one is identical, with reference to embodiment one Relevant drawings), use wet etching (Wet Etch) technique photoresist is removed completely district The source-drain electrode metal level in territory performs etching, and then uses dry etching (Dry Etch) technique to polycrystalline Silicon layer performs etching, and obtains polysilicon active layer 53.

Then, as shown in fig. 5i (owing to Fig. 5 I with embodiment one is identical, with reference to embodiment one Relevant drawings), process through plasma ashing, by photoresist half reserved area of photoresist 55 The photoresist in territory 552 etches away, and remaining photoresist is fully retained the photoresist in region 551, this photoetching Glue is fully retained region 551 corresponding source electrode, drain region.

Then, as indicated at figure 5j (owing to Fig. 5 J with embodiment one is identical, with reference to embodiment one Relevant drawings), then through wet-etching technology, photoresist half is retained the source-drain electrode in region 552 Metal level carries out secondarily etched.

Finally, as it can be seen from figure 5k (owing to Fig. 5 K with embodiment one is identical, with reference to embodiment one Relevant drawings), after peeling off the photoresist that photoresist is fully retained region 551, obtain Source electrode, drain electrode 54.

So far, in the present embodiment, processed by a HTM patterning processes, obtained including data Line, source electrode, drain electrode, the pattern of polysilicon active layer.In relatively prior art, employing first carry out one Secondary patterning processes processes and obtains polycrystalline silicon active layer pattern, then carries out a patterning processes process and obtains Source, drain electrode and the layering of the connecting portion of active layer, then carry out a patterning processes and process and obtain source, drain electrode For, decrease the PROCESS FOR TREATMENT of exposure, thus reduce complex procedures degree, add man-hour shortening Processing cost is reduced while between.

S605, on the pattern of source electrode, drain electrode and polysilicon semiconductor part formed gate insulation layer, it After carry out channel region doping treatment, in order to source, drain electrode formed channel region.

S606, on gate insulation layer formed grid line, grid.

S607, formation protective layer (PVX) on grid.

S608, on gate insulation layer and protective layer formed connect via.

S609, form ITO pixel electrode on via connecting.

S610, form planarization layer on the pixel electrode.

The manufacture method of the low temperature polycrystalline silicon tft array substrate that the embodiment of the present invention provides, at substrate After upper formation cushion, coating polysilicon layer and metal level, by HTM to metal level, polycrystalline Silicon layer is patterned PROCESS FOR TREATMENT, by patterning processes obtain including data wire, source electrode, drain electrode, The pattern of polysilicon semiconductor part.Relatively prior art first carries out a patterning processes process and obtains many Crystal silicon active layer pattern, then carries out a patterning processes and processes the connection obtaining source-drain electrode with active layer Part, then carry out for patterning processes processes and obtain source, drain electrode, decreasing at the technique of exposure Reason, decreases layer protective layer, thus reduces complex procedures degree, save material, shortening Processing cost is reduced while process time.

Embodiment three

The low temperature polycrystalline silicon tft array substrate that the embodiment of the present invention provides, as shown in Fig. 5 Q, including:

Substrate 51;

Cushion 52 it is formed with on substrate 51;

Polysilicon semiconductor active layer 53 it is formed with on cushion 52;

Source electrode 541, drain electrode 542 it is formed with on polysilicon semiconductor active layer 53;Source electrode 541, leakage Pole 542 and polysilicon semiconductor active layer 53 constitute TFT zone;

It is formed with gate insulation layer 56 in source electrode 541, drain electrode 542;

Grid 57, grid line (not shown) it is formed with on gate insulation layer 56;

Protective layer 58 it is formed with on grid 57, grid line;

Being formed with pixel electrode layer 59 on protective layer 58, pixel electrode layer 59 is by being positioned at protective layer 58, the via 59 ' on gate insulation layer 56 is connected with drain electrode 542.

The low temperature polycrystalline silicon tft array substrate that the embodiment of the present invention provides, forms buffering on substrate After layer, coating polysilicon layer and metal level, by HTM or GTM to metal level, polysilicon Layer is patterned PROCESS FOR TREATMENT, by patterning processes obtain including data wire, source electrode, drain electrode, The pattern of polysilicon semiconductor part.Relatively prior art first carries out a patterning processes process and obtains many Crystal silicon active layer pattern, then carries out a patterning processes and processes the connection obtaining source-drain electrode with active layer Part, then carry out for patterning processes processes and obtain source, drain electrode, decreasing at the technique of exposure Reason, decreases layer protective layer, thus reduces complex procedures degree, save material, shortening Processing cost is reduced while process time.

Embodiment four

The manufacture method of the low temperature polycrystalline silicon tft array substrate that the embodiment of the present invention provides, such as Fig. 7 Shown in, including:

S701, on substrate formed cushion.

S702, form polysilicon layer on the buffer layer.

S703, carry out low concentration doping at polysilicon layer.

After polysilicon layer is formed, polysilicon layer is carried out low concentration doping, doping type with will carry out Channel region doping type contrary, in order to channel doping process after between source, drain electrode and raceway groove formed Reversely PN junction, so can reduce the contact electricity of polysilicon layer and source and drain interpolar at source-drain electrode Resistance.

S704, in polysilicon active layer formed source, drain electrode used by the first metal layer.

S705, utilize Lycoperdon polymorphum Vitt mask plate or half-penetration type mask plate, the first metal layer, polysilicon layer are entered Row patterning processes processes, and obtains data wire, source electrode, drain electrode and polysilicon half by a patterning processes Conductor part pattern.

In addition to the above steps, remaining step is just the same with embodiment one or embodiment two for the present embodiment, Specifically refer to embodiment one or embodiment two.

The low temperature polycrystalline silicon tft array substrate that the embodiment of the present invention provides, forms buffering on substrate After layer, coating polysilicon layer and metal level, by HTM or GTM to metal level, polysilicon Layer is patterned PROCESS FOR TREATMENT, by patterning processes obtain including data wire, source electrode, drain electrode, The pattern of polysilicon semiconductor part.Relatively prior art first carries out a patterning processes process and obtains many Crystal silicon active layer pattern, then carries out a patterning processes and processes the connection obtaining source-drain electrode with active layer Part, then carry out for patterning processes processes and obtain source, drain electrode, decreasing at the technique of exposure Reason, decreases layer protective layer, thus reduces complex procedures degree, save material, shortening Processing cost is reduced while process time.

The above, the only detailed description of the invention of the present invention, but protection scope of the present invention not office Being limited to this, any those familiar with the art, can in the technical scope that the invention discloses The change readily occurred in or replacement, all should contain within protection scope of the present invention.Therefore, this Bright protection domain should be as the criterion with described scope of the claims.

Claims (5)

1. a low temperature polycrystalline silicon tft array substrate, it is characterised in that including:
Substrate;
It is formed with polysilicon layer;
It is formed with source electrode, drain electrode and polysilicon semiconductor active layer by a patterning processes;It After, the part between the source of described polysilicon semiconductor active layer, drain electrode is doped process, Described source electrode, drain electrode is made to constitute TFT zone with described polysilicon semiconductor active layer;
It is formed with gate insulation layer in described source electrode, drain electrode;
Grid, grid line it is formed with on described gate insulation layer;
It is formed with protective layer on described grid, grid line;
Being formed with pixel electrode layer on described protective layer, described pixel electrode layer is described by being positioned at Via on protective layer, gate insulation layer is connected with described drain electrode.
Low temperature polycrystalline silicon tft array substrate the most according to claim 1, it is characterised in that Also include:
Before being formed with polysilicon semiconductor active layer, it is formed with cushion on the substrate.
3. the manufacture method of a low temperature polycrystalline silicon tft array substrate, it is characterised in that including:
Substrate is formed polysilicon layer;
Described polysilicon layer is formed the first metal layer, utilizes gray tone mask plate or half-penetration type Mask plate is patterned PROCESS FOR TREATMENT to described the first metal layer, polysilicon layer, by for the first time Patterning processes obtains data wire, source electrode, drain electrode and the pattern of polysilicon semiconductor part;
On gate insulation layer, grid line, grid is formed by second time patterning processes;
The pattern of described source electrode, drain electrode and polysilicon semiconductor part is formed gate insulation layer;
Part between the source of described polysilicon layer, drain electrode is doped process, in order to institute State source, drain electrode forms channel region;
Described grid line, grid form protective layer, by third time patterning processes in described leakage Form via at pole, expose described drain electrode;
Forming pixel electrode layer on described protective layer, described pixel electrode layer passes through described via It is connected with described drain electrode;
Pixel electrode figure is formed by the 4th patterning processes;
Planarization layer figure is formed on the pixel electrode by the 5th patterning processes.
The manufacture method of low temperature polycrystalline silicon tft array substrate the most according to claim 3, It is characterized in that, described utilize gray tone mask plate or half-penetration type mask plate to described first metal Layer is patterned PROCESS FOR TREATMENT, by patterning processes obtain data wire, source electrode, drain electrode and The pattern of polysilicon semiconductor part, including:
Coating photoresist on described the first metal layer;
Utilize gray tone mask plate or half-penetration type mask plate that described photoresist is exposed, development Rear formation photoresist is fully retained region, photoresist half retains region and region removed completely by photoresist; Wherein, described photoresist is fully retained respective data lines region, region, source region, drain region Territory, described photoresist half retains the region between correspondence source, region, drain region;
Utilize etching technics to get rid of described photoresist and remove the first metal layer in region, polycrystalline completely Silicon layer;
Utilize plasma ash process to get rid of described photoresist half and retain the photoresist in region;
Utilize etching technics to get rid of described photoresist half and retain the first metal layer in region;
Peel off described photoresist and the photoresist in region is fully retained.
The manufacture method of low temperature polycrystalline silicon tft array substrate the most according to claim 3, It is characterized in that, the described polysilicon layer that formed on substrate includes: form cushion on substrate, Described cushion is formed polysilicon layer.
CN201110270029.8A 2011-09-13 2011-09-13 A kind of low temperature polycrystalline silicon tft array substrate and manufacture method thereof CN102683338B (en)

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CN103022145B (en) 2012-10-31 2016-11-16 京东方科技集团股份有限公司 Array base palte, display device and preparation method
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CN104022077B (en) * 2014-05-27 2017-01-25 京东方科技集团股份有限公司 Array substrate, preparing method thereof and display device
CN103985638A (en) * 2014-05-27 2014-08-13 京东方科技集团股份有限公司 Low temperature polycrystalline silicon thin film transistor, preparation method thereof, and display device
CN104078424B (en) 2014-06-30 2017-02-15 京东方科技集团股份有限公司 Low-temperature poly-silicon TFT array substrate, manufacturing method thereof and display device
CN104253246B (en) * 2014-09-23 2016-08-17 京东方科技集团股份有限公司 The manufacture method of low-temperature polysilicon film, low-temperature polysilicon film and related device
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