CN102682839B - Flash memory device and programming method thereof - Google Patents
Flash memory device and programming method thereof Download PDFInfo
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- CN102682839B CN102682839B CN201110065726.XA CN201110065726A CN102682839B CN 102682839 B CN102682839 B CN 102682839B CN 201110065726 A CN201110065726 A CN 201110065726A CN 102682839 B CN102682839 B CN 102682839B
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Abstract
The invention relates to a flash memory device and a programming method thereof. The flash memory device comprises a memory array, a column decoder and M page buffers, wherein M is a positive integer, the memory array comprises a plurality of memory cells and is electrically connected with a plurality of character lines and a plurality of bit lines, the column decoder drives a specific character line in the character lines in an enabling period, the enabling period is divided into N sub-periods by the M page buffers, and N is an integer greater than 2. In addition, the M page buffers drive the ith, (i+N)th, (i+2N)th,..., [i+(M-1)*N]th bit lines in the ith sub-period so as to realize programming of the memory cells electrically connected to the specific character line, and i is an integer which is greater than or equal to 1 and less than or equal to N. The invention also provides a programming method of the flash memory device. Through the invention, the program disturbance of the memory cells can be reduced under the condition of giving consideration to transmission disturbance.
Description
Technical field
The present invention relates to a kind of flash memory device and its method for programming, particularly relate to a kind of NAND formula flash memory device and its method for programming.
Background technology
Fig. 1 is the block scheme of typical NAND formula flash memory device.Refer to shown in Fig. 1, NAND formula flash memory device 100 comprises memory cell 110, column decoder (row decoder) 120 and page buffer (page buffer) 131 ~ 133.Wherein, memory cell 110 comprises multiple memory cell tandem, and each memory cell tandem comprises the selection transistor of series connection mutually, multiple memory cell and grounding transistor.Such as, memory cell tandem 140 comprises the selection transistor SW11, multiple memory cell 151,161 ~ 163 and the grounding transistor SW12 that mutually connect.
In addition, column decoder 120 selects line SSL1, character line WL11 ~ WL14 and ground connection to select line GSL1 to be electrically connected to memory cell 110 by string, and page buffer 131 ~ 133 is then be electrically connected to memory cell 110 by bit line BL11 ~ BL16.In the operation of sequencing, column decoder 120 can select a character line according to address data.In addition, every page buffer is electrically connected two bit lines, and alternately provides ground voltage Vs1 and supply voltage Vc1 to be connected two bit lines.Moreover when character line WL12 is selected, column decoder 120 will provide programm voltage Vp1 to selected character line WL12, and provides transfer overvoltage Vt1 to character line WL11, WL13 of not choosing ~ WL14.
Thus, as shown in Figure 1, before sequencing in the semiperiod, page buffer 131 ~ 133 will provide ground voltage Vs1 to odd number bar bit line BL11, BL13, BL15, and provide supply voltage Vc1 to even number bar bit line BL12, BL14, BL16.By this, the odd number memory cell 151,153,155 be connected in character line WL12 will carry out sequencing.Memory cell 152,154,156 in order to avoid position on same character line WL12 is affected, the variation of the critical voltage of memory cell 152,154,156 can be avoided, namely so-called program disturbance (program disturbance) by the channel voltage improving each memory cell tandem.
In general, the method for operating of existing memory cell is all the transfer overvoltage Vt1 provided by raising column decoder 120, improves the channel voltage of each memory cell tandem, and then reduces program disturbance.But, if the words that the transfer overvoltage Vt1 that column decoder 120 provides is too high, the critical voltage of the memory cell 161 ~ 163,171 ~ 173,181 ~ 183 be positioned on same bit line with memory cell 151,153,155 respectively will be affected, namely so-called transmission disturbance (pass disturbance).In other words, although the method for operating of existing memory cell utilizes the lifting of transfer overvoltage to solve program disturbance, transmission disturbance is too increased.Therefore, how to reduce program disturbance when taking into account and transmitting disturbance, be the large problem that memory cell is operationally faced.
As can be seen here, above-mentioned existing flash memory device and its method for programming, in product structure, method and use, obviously still have inconvenience and defect, and are urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development always, and common product and method do not have appropriate structure and method to solve the problem, this is obviously the anxious problem for solving of relevant dealer.Therefore how to found a kind of new flash memory device and its method for programming, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
The object of the invention is to, overcome the defect that existing flash memory device exists, and a kind of new flash memory device is provided, technical matters to be solved be make its by page buffer by be divided into more than 3 during activation son during, and during different sons in drive different bit line, by this, when not improving transfer overvoltage, reduce the program disturbance of memory cell, be very suitable for practicality.
Another object of the present invention is to, the defect that the method for programming overcoming existing flash memory device exists, and a kind of method for programming of new flash memory device is provided, technical matters to be solved makes it pass through during being divided into N number of son during activation, and during different sons in drive different bit line, by this, by the reduction of the equivalent total capacitance of memory cell, improve channel voltage, thus be more suitable for practicality.
Another object of the present invention is, overcome the defect that existing flash memory device exists, and a kind of new flash memory device is provided, technical matters to be solved makes its bit line passing through every page buffer to be electrically connected respectively more than 3, and every page buffer drives respective connected bit line one by one, by this, when not improving transfer overvoltage during activation, reduce the program disturbance of memory cell, thus be more suitable for practicality.
An also object of the present invention is, the defect that the method for programming overcoming existing flash memory device exists, and a kind of method for programming of new flash memory device is provided, technical matters to be solved makes its bit line passing through every page buffer to be electrically connected respectively more than 3, and utilize page buffer to drive the bit line connected separately one by one, by this, by the reduction of the equivalent total capacitance of memory cell, improve channel voltage, thus be more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of flash memory device that the present invention proposes, comprise memory array, a column decoder and M page buffer, M is positive integer.Wherein, memory array comprises multiple memory cell, and is electrically connected many character lines and many bit lines.Column decoder drives in these character lines one specific character line during an activation.A described M page buffer by during being divided into N number of son during activation, N be greater than 2 integer.In addition, a described M page buffer during i-th son, drive i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line, to carry out sequencing to the memory cell being electrically connected to specific character line, i is integer and 1≤i≤N.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid flash memory device, wherein said memory array is more electrically connected string and selects line and ground connection to select line, and above-mentioned column decoder provides a supply voltage and a ground voltage to select line and ground connection to select line to going here and there respectively during activation, and provide a programm voltage to specific character line, and provide a transfer overvoltage to remaining character line.
Aforesaid flash memory device, M wherein said page buffer provides a ground voltage to the i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line respectively during i-th son, and provides a supply voltage to remaining bit line respectively.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The method for programming of a kind of flash memory device proposed according to the present invention, wherein said flash memory device comprises the memory array being electrically connected bar character line and many bit lines at the most, and memory array comprises multiple memory cell, the method for programming of described flash memory device comprises the following steps: during an activation, drive in these character lines one specific character line; By M page buffer by during being divided into N number of son during activation, wherein M is positive integer, N be greater than 2 integer; And driving i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line during i-th son, to carry out sequencing to the memory cell being connected to specific character line, wherein i is integer and 1≤i≤N.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method for programming of aforesaid flash memory device, wherein said memory array is more electrically connected a string selection line and a ground connection selects line, and during this activation, drive the step of this specific character line in those character lines to comprise: provide a supply voltage to select line to this string; A ground voltage is provided to select line to this ground connection; There is provided a programm voltage to this specific character line; And provide a transfer overvoltage to remaining those character line.
The method for programming of aforesaid flash memory device, wherein during i-th son, the step of driving i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line comprises: during i-th son, provide a ground voltage to the i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line respectively; And during i-th son, provide a supply voltage to remaining those bit line respectively.
The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.According to a kind of flash memory device that the present invention proposes, comprise memory array, a column decoder and M page buffer, M is positive integer.Wherein, memory array comprises multiple memory cell, and is electrically connected many character lines and many bit lines.Column decoder drives in these character lines one specific character line during an activation.Every page buffer is electrically connected the N bar bit line in these bit lines respectively, N be greater than 2 integer.Wherein, a jth page buffer drives N* (j-1)+1 article of bit line to N*j article of bit line during activation, and be electrically connected to those memory cells of specific character line with sequencing one by one, j is integer and 1≤j≤M.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid flash memory device, wherein said memory array is more electrically connected a string selection line and a ground connection selects line, and this column decoder provides a supply voltage and a ground voltage to this string to select line and this ground connection to select line respectively during this activation, and provide a programm voltage to this specific character line, and provide a transfer overvoltage to remaining those character line.
Aforesaid flash memory device, a wherein said jth page buffer sequentially provides a ground voltage to N* (j-1)+1 article of bit line to N*j article of bit line during this activation, and under the bit line not receiving this ground voltage in N* (j-1)+1 article of bit line to N*j article of bit line is biased in a supply voltage.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.The method for programming of a kind of flash memory device proposed according to the present invention, wherein said flash memory device comprises the memory array being electrically connected bar character line and many bit lines at the most, and memory array comprises multiple memory cell.The method for programming of shown flash memory device comprises the following steps: during an activation, drive in these character lines one specific character line; Be electrically connected M page buffer by these bit lines, and often page buffer is electrically connected the N bar bit line in these bit lines respectively, wherein M is positive integer, N be greater than 2 integer; And during activation, a jth page buffer drives N* (j-1)+1 article of bit line to N*j article of bit line, be electrically connected to the memory cell of specific character line with sequencing one by one, j is integer and 1≤j≤M.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method for programming of aforesaid flash memory device, wherein said memory array is more electrically connected a string selection line and a ground connection selects line, and during this activation, drive the step of this specific character line in those character lines to comprise: provide a supply voltage to select line to this string; A ground voltage is provided to select line to this ground connection; There is provided a programm voltage to this specific character line; And provide a transfer overvoltage to remaining those character line.
The method for programming of aforesaid flash memory device, wherein during this activation, a jth page buffer drives N* (j-1)+1 article of bit line to comprise to the step of N*j article of bit line: during this activation, and a jth page buffer sequentially provides a ground voltage to N* (j-1)+1 article of bit line to N*j article of bit line; And during this activation, under the bit line not receiving this ground voltage in N* (j-1)+1 article of bit line to N*j article of bit line is biased in a supply voltage.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, flash memory device of the present invention and its method for programming at least have following advantages and beneficial effect: every page buffer is electrically connected the bit line of more than 3 by the present invention separately, and every page buffer can during activation in drive respective be electrically connected bit line one by one.In addition, from another viewpoint, the present invention is by during being divided into N number of son during activation, and during different sons in drive different bit lines.Thus, the equivalent total capacitance of memory cell tandem will be lowered, and then improve the channel voltage of each memory cell tandem.In addition, the present invention is in the process promoting channel voltage, and the position of not improving transfer overvoltage is accurate, therefore can not cause the increase of transmitting disturbance.In other words, the present invention, when taking into account transmission disturbance, reduces the program disturbance of memory cell.
In sum, the invention relates to a kind of flash memory device and its method for programming.This flash memory device, comprises memory array, a column decoder and M page buffer, and M is positive integer.Wherein, memory array comprises multiple memory cell, and is electrically connected many character lines and many bit lines.Column decoder drives in these character lines one specific character line during an activation.A described M page buffer by during being divided into N number of son during activation, N be greater than 2 integer.In addition, a described M page buffer during i-th son, drive i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line, to carry out sequencing to the memory cell being electrically connected to specific character line, i is integer and 1≤i≤N.Present invention also offers a kind of method for programming of flash memory device.The present invention when taking into account transmission disturbance, can reduce the program disturbance of memory cell by this.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of instructions, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is the block scheme of typical NAND formula flash memory device.
Fig. 2 is the schematic diagram of the flash memory device according to one embodiment of the invention.
Fig. 3 is the schematic diagram of the method for programming of the flash memory device of foundation one embodiment of the invention.
Fig. 4 is the layout sectional view of the memory cell according to one embodiment of the invention.
Fig. 5 is another layout sectional view of the memory cell according to one embodiment of the invention.
Fig. 6 A and Fig. 6 B is the diffusion bit line of foundation one embodiment of the invention and the schematic layout pattern of diffusion character line respectively.
Fig. 7 is the schematic diagram of the method for programming of the flash memory device of foundation another embodiment of the present invention.
100,200: flash memory device
110,210: memory cell
120,220: column decoder
131 ~ 133,231 ~ 233: page buffer
140,240: memory cell tandem
SW11, SW41: select transistor
SW12, SW42: grounding transistor
151 ~ 156,161 ~ 163,171 ~ 173,181 ~ 183,251 ~ 253,261 ~ 263,271 ~ 273,281 ~ 283: memory cell
SSL1, SSL4: string selects line
WL11 ~ WL14, WL41 ~ WL44: character line
GSL1, GSL4: ground connection selects line
BL11 ~ BL16, BL1 ~ BL9: bit line
Vc1, Vc4: supply voltage
Vs1, Vs4: ground voltage
Vp1, Vp4: programm voltage
Vt1, Vt4: transfer overvoltage
S310 ~ S330, S311 ~ S314, S331, S332: in order to each steps flow chart of the method for programming of key diagram 3
410: substrate
420: source/drain mixes layer
430,520: floating gate layer
440,510: control gate layer
450: inversion layer
Cono, Ctun, Cdep: stray capacitance
Cj: junction capacitance
530: insulation course
540,550: diffusion bit line
Cdef: diffusion capacitance
610 ~ 630: diffusion character line
S710 ~ S730, S731, S732: in order to each steps flow chart of the method for programming of key diagram 7
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the flash memory device proposed according to the present invention and its embodiment of its method for programming, structure, method, step, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, when can to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, however institute's accompanying drawings be only to provide with reference to and the use of explanation, be not used for being limited the present invention.
Fig. 2 is the schematic diagram of the flash memory device according to one embodiment of the invention.Refer to shown in Fig. 2, flash memory device 200 comprises memory cell 210, column decoder 220 and multiple page buffer.Wherein, Fig. 2 embodiment is described for 3 page buffers 231 ~ 233 (M=3), but it is not intended to limiting the invention.
In the present embodiment, memory cell 210 is a NAND formula memory cell, and therefore memory cell 210 comprises multiple memory cell tandem, and each memory cell tandem comprises the selection transistor of series connection mutually, multiple memory cell and grounding transistor.For example, memory cell tandem 240 comprises the selection transistor SW41, multiple memory cell 251,281 ~ 283 and the grounding transistor SW42 that mutually connect.In addition, memory cell 210 is electrically connected string and selects line SSL4, character line WL41 ~ WL44, ground connection selection line GSL4 and bit line BL1 ~ BL9.
Column decoder 220 selects each being electrically connected in memory cell 210 of line SSL4 to select transistor by string, such as: select transistor SW41.In addition, column decoder 220 is electrically connected to each grounding transistor in memory cell 210 by ground connection selection line GSL4, such as: grounding transistor SW42.Moreover column decoder 220 is electrically connected to the memory cell in memory cell 210 by character line WL41 ~ WL44, such as: memory cell 251,281 ~ 283.In the operation of sequencing, column decoder 220 can select a character line according to address data, and during an activation in character line selected by driving.
Page buffer 231 ~ 233 is electrically connected to N bar bit line separately, wherein N be greater than 2 integer.For example, if the words that N equals 3,1st page buffer 231 is electrically connected the 1st article to the 3rd article bit line BL1 ~ BL3, and the 2nd page buffer 232 is electrically connected the 4th article to the 6th article bit line BL4 ~ BL6, and the 3rd page buffer 233 is electrically connected the 7th article to the 9th article bit line.That is, a jth page buffer is electrically connected (j-1) * N+1 article to jth * N article bit line, and j is integer and 1≤j≤M.During an activation, every page buffer 231 ~ 233 can drive respective connected N bar bit line one by one, to carry out sequencing to the memory cell be electrically connected on a certain character line.
In order to the technician causing this area to have usual knowledge more can understand the present embodiment, Fig. 3 is the schematic diagram of the method for programming of the flash memory device of foundation one embodiment of the invention, below please refer to the thin portion operation of Fig. 2 and Fig. 3 flash memory device 200.
In the process of programmable memory cell array 210, as shown in step S310, column decoder 220 understands in during an activation the specific character line driven in character line.For example, if column decoder 220 is that character line WL42 is considered as specific character line, then drive the detailed step of specific character line WL42 as follows.At this, as shown in step S311, column decoder 220 can provide a supply voltage Vc4 to select line SSL4 to string, selects transistor with each in conducting (turn on) memory cell 210.In addition, as shown in step S312, column decoder 220 can provide a ground voltage Vs4 to select line GSL4, to disconnect each grounding transistor in (turn off) memory cell 210 to ground connection.Thus, one end of each memory cell tandem will be electrically connected to corresponding page buffer, and the other end of each memory cell tandem is by suspension joint (floating).
In addition, as shown in step S313 and step S314, column decoder 220 can provide a programm voltage Vp4 to specific character line WL42, and provides a transfer overvoltage Vt4 to remaining character line WL41, WL43 ~ WL44.By this, the signal that the memory cell 251 ~ 253,261 ~ 263,271 ~ 273 being electrically connected to specific character line WL42 can transmit with reference to page buffer 231 ~ 233 carries out sequencing.On the other hand, as shown in step S320, page buffer 231 ~ 233 can by during being divided into N number of son during activation.For example, if page buffer 231 ~ 233 separately connects 3 bit lines (N=3), then page buffer 231 ~ 233 can by during being divided into 3 sons during activation.
In addition, as shown in step S330, during i-th son, page buffer 231 ~ 233 can drive i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line, to carry out sequencing to the memory cell being electrically connected specific character line WL42, wherein i is integer and 1≤i≤N.For example, if 3 page buffers 231 ~ 233 are by during being divided into 3 sons during activation, also with regard to M=3 and N=3 when, the thin portion flow process of step S330 is as follows.
As shown in Figure 2, in during the 1st son, page buffer 231 ~ 233 will provide a ground voltage Vs4 to the 1st, 4,7 article of bit line BL1, BL4, BL7 respectively, and provides a supply voltage Vc4 to remaining bit line BL2 ~ BL3, BL5 ~ BL6, BL8 ~ BL9 respectively.By this, memory cell 251 ~ 253 can carry out sequencing.Then, in during the 2nd son, page buffer 231 ~ 233 will provide a ground voltage Vs4 to the 2nd, 5,8 article of bit line BL2, BL5, BL8 respectively, and provides a supply voltage Vc4 to remaining bit line BL1, BL3 ~ BL4, BL6 ~ BL7, BL9 respectively.By this, memory cell 261 ~ 263 can carry out sequencing.
Finally, in during the 3rd son, page buffer 231 ~ 233 will provide a ground voltage Vs4 to the 3rd, 6,9 article of bit line BL3, BL6, BL9 respectively, and provides a supply voltage Vc4 to remaining bit line BL1 ~ BL2, BL4 ~ BL5, BL7 ~ BL8 respectively.By this, memory cell 271 ~ 273 can carry out sequencing.In other words, as shown in step S331 and step S332, in during i-th son, page buffer 231 ~ 233 can provide a ground voltage Vs4 to the i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line respectively, and provides a supply voltage Vc4 to remaining bit line respectively.
Thus, in the process of programmable memory cell, with regard to a certain bit line being biased in supply voltage Vc4, under only having at most a bit line to be biased in ground voltage Vs4 in two bit lines adjacent with its left and right.Such as, in during the 1st son, for the bit line BL5 being biased in supply voltage Vc4, under the bit line BL4 only on the left of it is biased in ground voltage Vs4.In addition, in during the 1st son, for the bit line BL6 being biased in supply voltage Vc4, under the bit line BL7 only on the right side of it is biased in ground voltage Vs4.By this, the channel voltage of each memory cell tandem can promote, and then reduce the transmission disturbance of memory cell.
Chief reason is, as Fig. 4 shown in the layout sectional view of memory cell that illustrates, wherein Fig. 4 shows the layout sectional view of memory cell 281,251,282, and Fig. 4 indicates substrate 410 respectively, source/drain mixes layer 420, floating gate layer 430 and control gate layer 440.As shown in Figure 4, under the control gate of memory cell 281,251,282 is biased in transfer overvoltage Vt4, programm voltage Vp4 and transfer overvoltage Vt4 respectively, and each self-forming one inversion layer 450 of memory cell 281,251,282.In addition, the stray capacitance caused because of layout structure comprises: the stray capacitance Cono between control gate and floating grid, the stray capacitance Ctun between floating grid and inversion layer, stray capacitance Cdep between inversion layer and substrate and junction capacitance Cj.Accordingly, the channel voltage Vch of memory cell tandem 240 will such as formula shown in (1):
Cch＝Cj+Cdep，Ctotal＝Cs+Cch
Wherein, the number of the memory cell that n is connected in series for memory cell tandem 240, Vchi is that the initial bit of memory cell tandem 240 channel voltage Vch when switching to floating is accurate, and Vth is the critical voltage of memory cell.Shown in (1), channel voltage Vch is inversely proportional to equivalent total capacitance Ctotal.In other words, by the equivalent total capacitance Ctotal of reduction, channel voltage Vch can be promoted.
In addition, Fig. 5 is another layout sectional view of the memory cell according to one embodiment of the invention, wherein Fig. 5 shows the layout sectional view of memory cell 251 and 261, and Fig. 5 indicates control gate layer 510, floating gate layer 520, insulation course 530 and diffusion bit line 540 and 550 respectively.As shown in Figure 5, the diffusion capacitance Cdef of a parasitism can be formed between two diffusion bit lines 540 and 550, and diffusion capacitance Cdef is a part of equivalent total capacitance Ctotal.In addition, in the layout of integrated circuit, two diffusion bit lines 540 and 550 are electrically connected to bit line BL1 and BL2 respectively.In other words, whether the voltage level of bit line BL1 and BL2 can determine the formation of diffusion capacitance Cdef, and then affect the size of equivalent total capacitance Ctotal.
For example, Fig. 6 A and Fig. 6 B is the diffusion bit line of foundation one embodiment of the invention and the schematic layout pattern of diffusion character line respectively, and wherein Fig. 6 A and Fig. 6 B shows respectively and spreads bit line 540 and 550 and spread character line 610 ~ 630.Wherein, as shown in Figure 6A, when pressure drop is at ground voltage Vs4 and supply voltage Vc4 respectively for bit line BL1 and BL2, two diffusion bit lines 540 and 550 also will distinguish pressure drop at supply voltage Vc4 and ground voltage Vs4.Now, the voltage difference between bit line BL1 and BL2 will cause forming diffusion capacitance between two diffusion bit lines 540 and 550, and then improve equivalent total capacitance Ctotal.Relatively, as shown in Figure 6B, when all pressure drop is at supply voltage Vc4 for bit line BL1 and BL2, under two diffusion bit lines 540 and 550 are also all biased in supply voltage Vc4.Now, because the voltage difference between bit line BL1 and BL2 is zero, therefore cannot form diffusion capacitance between two diffusion bit lines 540 and 550, and then reduce equivalent total capacitance Ctotal.
In other words, in the process of programmable memory cell, with regard to a certain bit line being biased in supply voltage Vc4, if under adjacent two bit lines in its left and right are all biased in ground voltage Vs4, two bit lines that then this bit line is adjacent with its left and right all can each self-forming one voltage difference, and then causes the lifting of equivalent total capacitance Ctotal.But, in the present embodiment, for a certain bit line being biased in supply voltage Vc4, under only having at most a bit line can be biased in ground voltage Vs4 in two bit lines that its left and right is adjacent, therefore can reduce equivalent total capacitance Ctotal, and then promote channel voltage Vch.And known, the present embodiment is in the process promoting channel voltage Vch, and the position of not improving transfer overvoltage Vt4 is accurate, therefore can not cause the increase of transmitting disturbance.In other words, the present embodiment when taking into account transmission disturbance, can reduce the program disturbance of memory cell.
It is worth mentioning that, in the above-described embodiments, every page buffer 231 ~ 233 be all during activation in drive one by one separately be electrically connected N bar bit line.Thus, if by during being divided into N number of son during activation, in during i-th son, i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line can drive by page buffer 231 ~ 233.In other words, from another viewpoint, Fig. 7 is the schematic diagram of the method for programming of the flash memory device of foundation another embodiment of the present invention.
Please refer to Fig. 2 and Fig. 7, in the process of programmable memory cell array 210, as shown in step S710, column decoder 220 understands in during an activation the specific character line driven in character line.Wherein, the detailed step of step S710 is identical or similar with the step S310 described in Fig. 3 embodiment, therefore does not repeat them here.In addition, as shown in step S720, by bit line BL1 ~ BL9 be electrically connected M page buffer 231 ~ 233, wherein page buffer 231 ~ 233 is electrically connected to N bar bit line separately, and M is integer, N be greater than 2 integer.In other words, a jth page buffer is electrically connected (j-1) * N+1 article to jth * N article bit line, and j is integer and 1≤j≤M.
In addition, as shown in step S730, during activation, a jth page buffer can sequentially drive N* (j-1)+1 article of bit line to N*j article of bit line, and be electrically connected the memory cell of specific character line with sequencing one by one, j is integer and 1≤j≤M.For example, if M=3 and N=3, then, in during activation, page buffer 231 can provide ground voltage Vs4 to bit line BL1 ~ BL3 one by one.In addition, when page buffer 231 provides ground voltage Vs4 to bit line BL1, under bit line BL2 and BL3 can be biased in supply voltage Vc4 by page buffer 231.Similarly, when page buffer 231 provides ground voltage Vs4 to bit line BL2, under bit line BL1 and BL3 can be biased in supply voltage Vc4 by page buffer 231.
On the other hand, for page buffer 232, in during activation, it also can provide ground voltage Vs4 to bit line BL4 ~ BL6 one by one.In addition, when page buffer 232 provides ground voltage Vs4 to bit line BL4, under bit line BL5 and BL6 can be biased in supply voltage Vc4 by page buffer 232.By that analogy, the operation of page buffer 233.In other words, as shown in step S731 and step S732, during activation, a jth page buffer sequentially can provide a ground voltage Vs4 to N* (j-1)+1 article of bit line to N*j article of bit line, and under the bit line not receiving ground voltage Vs4 in N* (j-1)+1 article of bit line to N*j article of bit line will be biased in supply voltage Vc4.Thin portion flow process as the present embodiment is included in the various embodiments described above, therefore does not repeat them here.
In sum, every page buffer is electrically connected the bit line of more than 3 by the present invention separately, and every page buffer can during activation in drive respective be electrically connected bit line one by one.By this, the equivalent total capacitance of memory cell tandem can be lowered, and then promote the channel voltage of each memory cell tandem.In addition, the present invention is in the process promoting channel voltage, and the position of not improving transfer overvoltage is accurate, therefore can not cause the increase of transmitting disturbance.In other words, the present invention when taking into account transmission disturbance, can reduce the program disturbance of memory cell.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the method and technology contents that can utilize above-mentioned announcement are made a little change or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (8)
1. a flash memory device, is characterized in that it comprises:
One memory array, comprises multiple memory cell, and is electrically connected many character lines and many bit lines;
One column decoder, drives in those character lines one specific character line during an activation; And
M page buffer, wherein those page buffers are by during being divided into N number of son during this activation, and those page buffers drive i-th during i-th son, i+N, i+2N ..., i+ (M-1) * N bar bit line, to carry out sequencing to those memory cells being electrically connected this specific character line, M is positive integer, N be greater than 2 integer, i is integer and 1≤i≤N; Wherein during i-th son, those page buffers provide a ground voltage to the i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line respectively, and provide a supply voltage to remaining those bit line respectively; Wherein during this activation for a certain bit line being biased in supply voltage, under only having at most a bit line to be biased in ground voltage in two bit lines that its left and right is adjacent, when taking into account transmission disturbance, the program disturbance of memory cell can be reduced by this.
2. flash memory device according to claim 1, it is characterized in that wherein said memory array is more electrically connected a string selection line and a ground connection selects line, and this column decoder provides a supply voltage and a ground voltage to this string to select line and this ground connection to select line respectively during this activation, and provide a programm voltage to this specific character line, and provide a transfer overvoltage to remaining those character line.
3. the method for programming of a flash memory device, it is characterized in that wherein this flash memory device comprises the memory array being electrically connected bar character line and many bit lines at the most, and this memory array comprises multiple memory cell, the method for programming of this flash memory device comprises the following steps:
In those character lines one specific character line is driven during an activation;
By M page buffer by during being divided into N number of son during this activation, wherein M is positive integer, N be greater than 2 integer; And
Driving i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line during i-th son, to carry out sequencing to those memory cells connecting this specific character line, wherein i is integer and 1≤i≤N;
Wherein during i-th son, the step of driving i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line comprises:
During i-th son, provide a ground voltage to the i-th, i+N, i+2N ..., i+ (M-1) * N bar bit line respectively; And
During i-th son, provide a supply voltage to remaining those bit line respectively;
Wherein during this activation for a certain bit line being biased in supply voltage, under only having at most a bit line to be biased in ground voltage in two bit lines that its left and right is adjacent, when taking into account transmission disturbance, the program disturbance of memory cell can be reduced by this.
4. the method for programming of flash memory device according to claim 3, it is characterized in that wherein said memory array is more electrically connected a string selection line and a ground connection selects line, and during this activation, drive the step of this specific character line in those character lines to comprise:
A supply voltage is provided to select line to this string;
A ground voltage is provided to select line to this ground connection;
There is provided a programm voltage to this specific character line; And
There is provided a transfer overvoltage to remaining those character line.
5. a flash memory device, is characterized in that it comprises:
One memory array, comprises multiple memory cell, and is electrically connected many character lines and many bit lines;
One column decoder, drives in those character lines one specific character line during an activation; And
M page buffer, each those page buffer is electrically connected the N bar bit line in those bit lines respectively, wherein, a jth page buffer drives N* (j-1)+1 article of bit line to N*j article of bit line during this activation, those memory cells of this specific character line are electrically connected with sequencing one by one, M is positive integer, N be greater than 2 integer, j is integer and 1≤j≤M; A wherein said jth page buffer sequentially provides a ground voltage to N* (j-1)+1 article of bit line to N*j article of bit line during this activation, and under the bit line not receiving this ground voltage in N* (j-1)+1 article of bit line to N*j article of bit line is biased in a supply voltage; Wherein during this activation for a certain bit line being biased in supply voltage, under only having at most a bit line to be biased in ground voltage in two bit lines that its left and right is adjacent, when taking into account transmission disturbance, the program disturbance of memory cell can be reduced by this.
6. flash memory device according to claim 5, it is characterized in that wherein said memory array is more electrically connected a string selection line and a ground connection selects line, and this column decoder provides a supply voltage and a ground voltage to this string to select line and this ground connection to select line respectively during this activation, and provide a programm voltage to this specific character line, and provide a transfer overvoltage to remaining those character line.
7. the method for programming of a flash memory device, it is characterized in that wherein this flash memory device comprises the memory array being electrically connected bar character line and many bit lines at the most, and this memory array comprises multiple memory cell, the method for programming of this flash memory device comprises the following steps:
In those character lines one specific character line is driven during an activation;
Be electrically connected M page buffer by those bit lines, and each those page buffer is electrically connected the N bar bit line in those bit lines respectively, and wherein M is positive integer, N be greater than 2 integer; And
During this activation, a jth page buffer drives N* (j-1)+1 article of bit line to N*j article of bit line, and be electrically connected those memory cells of this specific character line with sequencing one by one, j is integer and 1≤j≤M;
Wherein during this activation, a jth page buffer drives N* (j-1)+1 article of bit line to comprise to the step of N*j article of bit line:
During this activation, a jth page buffer sequentially provides a ground voltage to N* (j-1)+1 article of bit line to N*j article of bit line; And
During this activation, under the bit line not receiving this ground voltage in N* (j-1)+1 article of bit line to N*j article of bit line is biased in a supply voltage;
Wherein during this activation for a certain bit line being biased in supply voltage, under only having at most a bit line to be biased in ground voltage in two bit lines that its left and right is adjacent, when taking into account transmission disturbance, the program disturbance of memory cell can be reduced by this.
8. the method for programming of flash memory device according to claim 7, it is characterized in that wherein said memory array is more electrically connected a string selection line and a ground connection selects line, and during this activation, drive the step of this specific character line in those character lines to comprise:
A supply voltage is provided to select line to this string;
A ground voltage is provided to select line to this ground connection;
There is provided a programm voltage to this specific character line; And
There is provided a transfer overvoltage to remaining those character line.
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| CN1971762A (en) * | 2005-11-23 | 2007-05-30 | 三星电子株式会社 | Nonvolatile semiconductor memory and method of programming the same |
| CN101354921A (en) * | 2007-07-23 | 2009-01-28 | 三星电子株式会社 | Non-volatile memory device programming selection transistor and method of programming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1971762A (en) * | 2005-11-23 | 2007-05-30 | 三星电子株式会社 | Nonvolatile semiconductor memory and method of programming the same |
| CN101354921A (en) * | 2007-07-23 | 2009-01-28 | 三星电子株式会社 | Non-volatile memory device programming selection transistor and method of programming the same |
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