CN102651206B - Display floater and there is the display device of this display floater - Google Patents

Abstract

This application provides a kind of display floater and there is the display device of this display floater.Described display floater includes: viewing area, include the first outer peripheral areas and the outer peripheral areas of second outer peripheral areas relative with described first outer peripheral areas, the multiple pixels being positioned in described viewing area, a plurality of data lines, first grid polar curve, second gate line, first grid drive circuit and second grid drive circuit.Every data line is corresponding to two pixel columns.First grid polar curve is positioned on the first side of pixel column.Second gate line is positioned at the second side of pixel column.First grid drive circuit is positioned in the first outer peripheral areas, and includes the first order providing signal to first grid polar curve.Second grid drive circuit is positioned in the second outer peripheral areas, and includes the second level providing signal to second gate line.

Description

Display floater and there is the display device of this display floater

Technical field

The illustrative embodiments of the present invention relates to a kind of display floater and has this display floater Display device.More specifically, the illustrative embodiments of the present invention relates to a kind of presentation quality of improving Display floater and there is the display device of this display floater.

Background technology

Generally, liquid crystal display (" LCD ") equipment includes LCD and drives this LCD Driving means.LCD includes a plurality of data lines and a plurality of gate line intersected with data wire. Therefore, multiple pixels of LCD can be limited by data wire and gate line.Driving means include by Signal output is to the gate driver circuit of gate line with by the number of data signal output to data wire According to drive circuit.

In order to reduce overall size and the manufacturing cost of LCD device, it is used for reducing number According to the quantity of line and the dot structure of the quantity of data drive circuit.Two pixels adjacent one another are are shared A data line in dot structure.Therefore, the multiple pixels being included in two pixel columns share one Data line so that the quantity of data wire reduces.But, it is included in the multiple pictures in a pixel column Element is electrically connected to each other adjacent two gate line, and two signals different from each other put on Article two, gate line.

For driving this pixel column, two gate lines are necessary so that produce two signals Two circuit-level be formed at the LCD corresponding with this pixel column in the viewing area of LCD In the outer peripheral areas of panel.Therefore, the width of outer peripheral areas increases so that frame (bezel) width Increase.

It addition, in High Resolution LCD panel, signal occurs due to the resistance of gate line Delay poor (delay difference) so that be positioned at the left side of LCD and the pixel on right side by In delay difference, there is charge difference (charge difference).As a result, lacking of such as vertical line, occurs Fall into.

Summary of the invention

The illustrative embodiments of the present invention provides a kind of border width that can reduce display device Display floater.

The illustrative embodiments of the present invention also provides for a kind of display device with display floater.

According to an illustrative embodiment of the invention, display floater includes: viewing area；Outer peripheral areas, Around viewing area, and include the first outer peripheral areas and the relative with this first outer peripheral areas second periphery Region；Multiple pixels；A plurality of data lines；First grid polar curve；Second gate line；First grid drives Circuit and second grid drive circuit.Pixel is positioned in viewing area, and include multiple pixel column and Multiple pixel columns.Data wire extends along column direction and every data line is corresponding to two pixel columns.The One gate line extends in the row direction and is positioned at the first side of each pixel column.Second gate line is along row Direction extends and is positioned at the second side of each pixel column.First grid drive circuit is positioned at outside first Enclose in region and include providing to the first grid polar curve first order of signal.Second grid drives electricity Road is positioned in the second outer peripheral areas and includes providing to second gate line the second level of signal.

In the exemplary embodiment, display floater can also include: the first clock line, and it is by first Clock signal is sent to first grid drive circuit；3rd clock line, it is by the 3rd clock signal transmission To second grid drive circuit, the 3rd clock signal has the first delay relative to the first clock signal Difference；Second clock line, second clock signal is sent to first grid drive circuit, second clock by it It is poor that signal has the second delay relative to the first clock signal, and the second delay difference is poor more than the first delay； And the 4th clock line, it sends the 4th clock signal to second grid drive circuit, the 4th clock It is poor that signal has the 3rd delay relative to the first clock signal, and the 3rd delay difference is poor more than the second delay.

In the exemplary embodiment, during the first order may be located at the first outer peripheral areas and its width is little In or equal to the pixel column width that limited by the distance between first grid polar curve and second gate line, and The second level may be located in the second outer peripheral areas and has the width less than or equal to pixel column width.

In the exemplary embodiment, display floater can also include: the first discharge circuit, is adjacent to The second level, and this first discharge circuit includes the high-voltage discharge putting on first grid polar curve is become low First discharge transistor of voltage；And second discharge circuit, be adjacent to the first order, and this second Discharge circuit includes the second electric discharge crystalline substance that the high-voltage discharge putting on second gate line becomes low-voltage Body pipe.

In the exemplary embodiment, pixel can include multiple red pixel, multiple green pixel and Multiple blue pixel, one in first grid polar curve and second gate line can be electrically connected to red pixel In each and another can be electrically connected to each in green pixel, and first grid polar curve Blue pixel is can be electrically connected to each in second gate line.

Another exemplary embodiment according to the present invention, display device includes display floater and printing electricity Road plate (" PCB ").Display floater includes: viewing area；Outer peripheral areas, around viewing area, and And include the first outer peripheral areas and second outer peripheral areas relative with the first outer peripheral areas；Multiple pixels, It is positioned in viewing area and includes multiple pixel column and multiple pixel column；A plurality of data lines, along row side Two pixel columns are corresponded to extension and every data line；First grid polar curve, extends also in the row direction And be positioned at the first side of each pixel column；Second gate line, extends in the row direction and is positioned at each At second side of pixel column；First grid drive circuit, is positioned in the first outer peripheral areas, including to One gate line provides the first order of signal；And second grid drive circuit, it is positioned at second peripheral In region, and include the second level that signal is provided to second gate line.PCB is electrically connected to show Show panel and there is the main drive circuit being positioned on PCB.Main drive circuit produces and is provided to the One and the first clock signal of second grid drive circuit, second clock signal, the 3rd clock signal and 4th clock signal.

In the exemplary embodiment, printed circuit board (PCB) can include passing the first and second clock signals Give a plurality of first holding wire of first grid drive circuit, the third and fourth clock signal is sent to The a plurality of secondary signal line of second grid drive circuit and when controlling the RC of the first and second holding wires Between resistance-capacitance (" RC ", resistor-capacitor circuit) the control portion of constant.

According to the present invention, signal is supplied to position by one in the first and second gate driver circuits Gate line at the first side of pixel column, and signal is supplied to be positioned at pixel column by another The second side at gate line so that can reduce in high-resolution display device border width and Power consumption can be reduced.It addition, by the dot structure of the present invention, be possible to prevent owing to grid is believed Number postpone difference produce significant difference.

Accompanying drawing explanation

Above and other feature of the present invention is by real to the Detailed example of the present invention by referring to accompanying drawing Execute the description of mode and become more fully apparent, wherein:

Fig. 1 shows the plane graph of the illustrative embodiments of the display device according to the present invention；

Fig. 2 A shows the block diagram of the illustrative embodiments of the first grid drive circuit of Fig. 1；

Fig. 2 B shows the block diagram of the illustrative embodiments of the second grid drive circuit of Fig. 1；

Fig. 3 shows input and the output of first and second gate driver circuits of Fig. 2 A and 2B The oscillogram of the illustrative embodiments of signal；

Fig. 4 shows input and the output of the first and second gate driver circuits according to the present invention The oscillogram of the another exemplary embodiment of signal；

Fig. 5 shows the schematic diagram of the illustrative embodiments of the display floater of Fig. 1；

Fig. 6 A to 6C shows according to each color images included in the display floater of Fig. 1 Driving that element is carried out and the schematic diagram of the illustrative embodiments of picture quality that obtains；

Fig. 7 A to 7B shows the exemplary of the presentation quality improvement of the display device according to Fig. 1 The schematic diagram of embodiment；

Fig. 8 shows showing of the another exemplary embodiment of the display floater always according to the present invention It is intended to；

Fig. 9 shows the signal of the another exemplary embodiment of the display floater according to the present invention Figure；

Figure 10 A to 10C shows according to each colour included in the display floater of Fig. 9 Driving that pixel is carried out and the schematic diagram of the illustrative embodiments of picture quality that obtains；And

Figure 11 shows the signal of the another exemplary embodiment of the display floater according to the present invention Figure.

Detailed description of the invention

Hereinafter with reference to the accompanying drawing showing exemplary embodiment of the invention, the present invention is carried out more complete Ground, face describes.But, the present invention can implement in many different forms, and should not be construed as limit In illustrative embodiments set forth herein.Certainly, it is provided that these embodiments are to make the disclosure Content fully and completely, and will fully convey the scope of the invention to those skilled in the art.Attached In figure, for the sake of clarity, layer and the size in region and relative size may be exaggerated.

Be appreciated that when an element or layer be referred to as another element or layer " on " or " even It is connected to " another element or during layer, this element or layer can directly on another element or layer or directly It is connected to another element or layer, or there may be intermediary element or layer.On the contrary, when an element Or layer is referred to as " directly " on another element or layer or " being connected directly to " another element Or during layer, the most there is not intermediary element or layer.Identical label represents similar elements all the time.As herein Being used, term "and/or" includes any and all group in one or more relevant Listed Items Close.

Although being appreciated that can use term first, second, third, etc. to describe various unit herein Part, parts, region, layer and/or part, but these elements, parts, region, layer and/or portion Divide and should not necessarily be limited to these terms.These terms are only used for element, parts, region, a layer Or part makes a distinction with another element, parts, region, layer or part.Therefore, without departing substantially from In the case of present invention teach that, the first element, parts, region, layer or part discussed below can With the referred to as second element, parts, region, layer or part.

For the ease of describing, can use herein such as D score, " on " etc. space relative terms, with An element or feature and another element or the relation of feature as illustrated in the drawing are described.It is appreciated that In addition to the orientation shown in figure, the difference of device when space relative terms is intended to include using or operating Orientation.Such as, if the device in flipchart, then it is D score relative to other element or feature description Element will be positioned as relative to other element or feature " on ".Therefore, exemplary term D score Two orientation above and below can be included.Device can otherwise position (90-degree rotation or It is positioned at other orientation), and space used herein relative descriptors can correspondingly explain.

Terms used herein is only used for describing the purpose of particular implementation rather than being intended to limit this Invention.As used in this article, unless literary composition otherwise clearly indicates, otherwise when not limiting When determining the particular number listd, it is intended to include one or more being listd.It is further appreciated that and works as When using in this specification, term " includes (comprises) " and/or " comprising (comprising) " Show to there are described feature, entirety, step, operation, element and/or parts, but be not precluded from Exist or be attached with one or more other feature, entirety, step, operation, element, parts, And/or its group.

Unless otherwise defined, all terms the most used herein (include technical term and Scientific terminology) have and be generally understood identical with general technical staff of the technical field of the invention Implication.Be further appreciated that such as those terms defined in common dictionary should be construed to have with The implication that they implications in the context of association area are consistent, and unless limit the most especially Fixed, otherwise should not be construed as Utopian or the most formal implication.

Next, with reference to the accompanying drawing present invention explained in detail.

Fig. 1 shows the plane graph of the illustrative embodiments of the display device according to the present invention.

With reference to Fig. 1, display device includes display floater 100, data driver 300 and printed circuit Plate (" PCB ") 400.

Display floater 100 can include viewing area DA and the outer peripheral areas around viewing area DA PA.A plurality of data lines DLm-1, DLm and DLm+1, a plurality of grid is had in the DA of viewing area (wherein, m, i and j are natures for line GLi-1, GLj-1, GLi and GLj and multiple pixel P Number).

Data wire DLm-1, DLm and DLm+1 are longitudinally extended along column direction and in the row direction Arrange, and every data line DLm-1, DLm and DLm+1 are corresponding to two pixel columns.

Gate lines G Li-1, GLj-1, GLi and GLj are longitudinally extended and in the row direction along row side To arranging (wherein, i and j is natural number).In an illustrative embodiments, such as, grid Line GLi-1 or GLi is positioned at the first side of each pixel column, and gate lines G Lj-1 or GLj It is positioned at second side relative with the first side of each pixel column.

Each pixel P all includes pixel switch element and is electrically connected to the pixel electricity of pixel switch element Pole.Pixel can be arranged to include multiple pixel column and the matrix-type of multiple pixel column.Two pixels Row can be arranged between data wire DLm-1 and DLm adjacent one another are.One pixel column can set Put between two gate lines adjacent one another are.The pixel of pixel column can be electrically connected to two grids Line.

Outer peripheral areas PA can include first grid drive circuit 210, second grid drive circuit 230 With data driver 300.

First grid drive circuit 210 is positioned in the first outer peripheral areas PA1 and includes cascading with one another Connect multiple levels (stage) SCi-1 and SCi of (cascade-connected).First grid drives Circuit 210 is physically connected to and/or is electrically connected to the first clock line in the first outer peripheral areas PA1 CKL1 and second clock line CKL2.First grid drive circuit 210 includes multiple contactor unit Part, and can be by processing substantially the same process shape with for form pixel switch element Become.What first grid drive circuit 210 was electrically connected in two gate lines is positioned at picture along scanning direction The first grid polar curve of first side (upside) of element row, these two gate lines are electrically connected to this pixel column Pixel, and first grid drive circuit 210 produce with put on the first of the first clock line CKL1 Clock signal CK1 or put on second clock line CKL2 second clock signal CK2 synchronize grid Pole signal.

In an illustrative embodiments, such as, (i-1) level SCi-1 is connected to be positioned at first (i-1) article gate lines G Li-1 at first side of pixel column PL1, and (i-1) level SCi-1 Width W1 can be less than or equal to the width W2 of the first pixel column PL1.I-stage SCi connects To i-th gate lines G Li being positioned at first side of the second pixel column PL2, and i-stage SCi Width W1 can be less than or equal to the width W2 of the second pixel column PL2.

Second grid drive circuit 230 is positioned in the second outer peripheral areas PA2, and includes level each other Multiple grades of SCj-1 and SCj that connection connects.Second grid drive circuit 230 is connected to be positioned at outside second Enclose the 3rd clock line CKL3 in the PA2 of region and the 4th clock line CKL4.Second grid drives electricity Road 230 includes multiple circuit switch element, and can by with for forming pixel switch element Process substantially the same process to be formed.Second grid drive circuit 230 is electrically connected to two gate lines In the second gate line at the second side (downside) place being positioned at pixel column along scanning direction, these two Gate line is electrically connected to the pixel of this pixel column, and second grid drive circuit 230 produces and applies In the 3rd clock signal CK3 of the 3rd clock line CKL3 or put on the 4th clock line CKL4's The signal that 4th clock signal CK4 synchronizes.

In an illustrative embodiments, such as, (j-1) level SCj-1 is connected to be positioned at first (j-1) article gate lines G Lj-1 at second side of pixel column PL1, and (j-1) level SCj-1 Width W1 can be less than or equal to the width W2 of the first pixel column PL1.J-th stage SCj connects To j-th strip gate lines G Lj being positioned at second side of the second pixel column PL2, and j-th stage SCj Width W1 can be less than or equal to the width W2 of the second pixel column PL2.Width W2 can be by Define along (i-1) article gate lines G Li-1 and (j-1) article grid that identical (arranging) direction obtains Distance between polar curve GLj-1 or i-th gate lines G Li and j-th strip gate lines G Lj.

Data driver 300 is positioned in the 3rd outer peripheral areas PA3.Data driver 300 includes many Individual data drive circuit 310,320 and 330, and each data drive circuit 310,320 and 330 Flexible PCB can be included, this flexible PCB is provided with data driving chip.

PCB 400 can be electrically connected to display floater 100 by data driver 300.PCB 400 Including main drive circuit 410 and multiple holding wire 421,422,423 and 424.Main drive circuit 410 Produce first, second, third and fourth clock signal CK1, CK2, CK3 and CK4, and It is positioned on PCB 400.

Holding wire 421,422,423 and 424 is by first, second, third and fourth clock signal CK1, CK2, CK3 and CK4 are respectively sent to the first and second gate driver circuits 210 and 230. In an illustrative embodiments, such as, the first holding wire 421 and 422 is driven by the first data Galvanic electricity road 310 and be electrically connected to the first and second clock lines being positioned in the first outer peripheral areas PA1 CKL1 and CKL2.Secondary signal line 423 and 424 is by last data drive circuit 330 And be electrically connected to the third and fourth clock line CKL3 of being positioned in the second outer peripheral areas PA2 and CKL4。

PCB 400 may further include the first resistance-capacitance (" RC ") control portion 431 and second RC control portion 432.

First and second RC control portions 431 and 432 control the first and second holding wires 421,422, The RC time constant value of 423 and 424.When first holding wire 421 and 422 transmits first and second Clock signal CK1 and CK2, and secondary signal line 423 and 424 transmission the third and fourth clock letter Number CK3 and CK4.In an illustrative embodiments, such as, when the first holding wire 421 He When the RC time constant value of 422 is different from the RC time constant value of secondary signal line 423 and 424, Oneth RC control portion 431 controls the RC time constant of the first holding wire 421 and 422, and Two RC control portions 432 control the RC time constant of secondary signal line 423 and 424 so that first The RC time constant value of holding wire 421 and 422 and the RC time of secondary signal line 423 and 424 Constant value is substantially the same.Therefore, it can reduce or effectively prevent from first grid drive circuit 210 The signal produced and the delay between the signal that second grid drive circuit 230 produces Difference.

Display floater 100 includes the opposing substrate 130 that display base plate 110 is relative with display base plate 110 And the liquid crystal layer (not shown) between display base plate 110 and opposing substrate 130.

Display base plate 110 includes first basal substrate with viewing area DA and outer peripheral areas PA, And data wire DLm-1, DLm and DLm+1, gate lines G Li-1, GLj-1, GLi and GLj And pixel electrode is positioned in the viewing area DA of the first basal substrate.First and second raster data model Circuit 210 and 230 is positioned in the first and second outer peripheral areas PA1 and the PA2 of the first basal substrate.

Opposing substrate 130 includes second basal substrate relative with the first basal substrate, and the second base Substrate has viewing area DA and outer peripheral areas PA1, PA2 and PA3.

Multiple color filter (not shown) are positioned in the viewing area DA of the second basal substrate.Color filter Redness, green and blue color filter can be included.Public electrode (not shown) is positioned at and includes color filter The second basal substrate on, and public electrode relative with pixel electrode (faced by such as).Can In the embodiment replaced, color filter can be included in display base plate 110.It addition, common electrical Extremely can be included in display base plate 110.

Fig. 2 A shows the frame of the illustrative embodiments of the first grid drive circuit 210 of Fig. 1 Figure.Fig. 2 B shows the block diagram of the second grid drive circuit 230 of Fig. 1.Fig. 3 shows The first grid drive circuit 210 of Fig. 2 A and 2B and the input of second grid drive circuit 230 and The oscillogram of the illustrative embodiments of output signal.

With reference to Fig. 2 A and Fig. 3, first grid drive circuit 210 include multiple grades of SC1, SC2 ..., SCi-1, SCi ..., SCk-1, dSC, and receive vertical initial signal STV, low-voltage VOFF, First clock signal CK1 and second clock signal CK2.Second clock signal CK2 is relative to first Clock signal CK1 can have the second delay difference t2.

Each grade of SC1, SC2 ..., SCi-1, SCi ..., SCk-1, dSC can include first Input terminal IN1, the second input terminal IN2, the 3rd input terminal IN3, voltage terminal VSS, Lead-out terminal OT and carry terminal (carry terminal) CR.The sub-IN1 of first input end receives and hangs down Straight initial signal STV or prime in the carry signal of at least one (carry signal).Second Input terminal IN2 receives the first clock signal CK1 or second clock signal CK2.3rd input The signal of at least one in the rear class of sub-IN3 reception.Voltage terminal VSS receives low-voltage VOFF, this low-voltage VOFF is the low level of signal.Lead-out terminal OT output is with first Or the signal that second clock signal CK1 or CK2 synchronizes.Carry terminal CR output and grid The carry signal that signal synchronizes.

In an illustrative embodiments, such as, (i-1) level SCi-1 is in response to from previous stage The high voltage VON of carry signal Cri-2 that (it is (i-2) level) exports and driven, with Produce (i-1) individual signal Gi-1 Tong Bu with the first clock signal CK1.(i-1) is individual Signal Gi-1 applies to (i-1) article grid being positioned at first side of the first pixel column PL1 Line GLi-1.I-stage SCi is in response to the carry letter exported from previous stage (it is (i-1) level) The high voltage VON of number Cri-1 and driven, to produce Tong Bu with second clock signal CK2 the I signal Gi.I-th signal Gi applies to the first side being positioned at the second pixel column PL2 I-th gate lines G Li at place.

Therefore, first grid drive circuit 210 is believed based on the first clock signal CK1 or second clock Number CK2 and sequentially export signal G1, G3 ..., Gi-1, Gi ..., Gk-1 (wherein, K is natural number).

With reference to Fig. 2 B and Fig. 3, second grid drive circuit 230 include multiple grades of SC1, SC2 ..., SCj-1, SCj ..., SCk, dSC, and receive vertical initial signal STV, low-voltage VOFF, 3rd clock signal CK3 and the 4th clock signal CK4.3rd clock signal CK3 is relative to first Clock signal CK1 can have the first delay difference t1.First postpones difference t1 less than the second delay difference t2. 4th clock signal CK4 can have the 3rd delay difference t3 relative to the first clock signal CK1.The Three postpone difference t3 more than the second delay difference t2.Can repeat first, second by a cycle T, Third and fourth clock signal CK1, CK2, CK3 and CK4, and first, second, third Or each of which in the 4th clock signal CK1, CK2, CK3 or CK4 has corresponding to 1/4T The high level period (high period).

Each of which in level SC1, SC2 ..., SCj-1, SCj ..., SCk, dSC can be wrapped Include the sub-IN1 of first input end, the second input terminal IN2, the 3rd input terminal IN3, voltage terminal VSS, lead-out terminal OT and carry terminal CR.The sub-IN1 of first input end receives vertical initial letter Number STV or prime in the carry signal of at least one.Second input terminal IN2 receives the 3rd Clock signal CK3 or the 4th clock signal CK4.In the rear class of the 3rd input terminal IN3 reception The signal of at least one.Voltage terminal VSS receives low-voltage VOFF, this low-voltage VOFF Low level for signal.Lead-out terminal OT output with the 3rd or the 4th clock signal CK3 or The signal that CK4 synchronizes.The carry signal that carry terminal CR output is Tong Bu with signal.

In an illustrative embodiments, such as, (j-1) level SCj-1 is in response to from previous stage The high voltage VON of carry signal Crj-2 that (it is (j-2) level) exports and driven, with Produce (j-1) individual signal Gj-1 Tong Bu with the 3rd clock signal CK3.(j-1) is individual Signal Gj-1 applies to (j-1) article grid being positioned at second side of the first pixel column PL1 Line GLj-1.J-th stage SCj is in response to the carry letter exported from previous stage (it is (j-1) level) The high voltage VON of number Crj-1 and driven, to produce Tong Bu with the 4th clock signal CK4 the J signal Gj.Jth signal Gj applies to the second side being positioned at the second pixel column PL2 J-th strip gate lines G Lj at place.

Therefore, second grid drive circuit 230 is in response to the 3rd clock signal CK3 or the 4th clock Signal CK4 and sequentially export signal G2, G4 ..., Gj-1, Gj ..., Gk.

First and second gate driver circuits 210 and 230 can sequentially by signal G1, G2 ..., Gi-1, Gj-1, Gi, Gj ..., the gate line of Gk output to display floater 100.

Fig. 4 shows input and the output of the first and second gate driver circuits according to the present invention The oscillogram of the another exemplary embodiment of signal.

With reference to Fig. 1 and Fig. 4, the first clock signal CK1 and second clock signal CK2 put on the One gate driver circuit 210.3rd clock signal CK3 and the 4th clock signal CK4 put on Two gate driver circuits 230.

3rd clock signal CK3 has the first poor t1 of delay relative to the first clock signal CK1, the Two clock signals CK2 have second more than the first delay difference t1 relative to the first clock signal CK1 Postpone difference t2, and the 4th clock signal CK4 has more than the relative to the first clock signal CK1 Two the 3rd delay difference t3 postponing difference t2.

Can by a cycle T repeat first, second, third and fourth clock signal CK1, CK2, CK3 and CK4, and first, second, third or the 4th clock signal CK1, CK2, Each of which in CK3 or CK4 has the high level period corresponding to 1/2T.

When in first, second, third or the 4th clock signal CK1, CK2, CK3 or CK4 When the high level period of each is substantially the same with 1/2T, the high level of the 3rd clock signal CK3 The half crossover of the high level period of period and the first clock signal CK1, second clock signal CK2 The half crossover of high level period of high level period and the 3rd clock signal CK3, and the 4th The half of the high level period of the high level period of clock signal CK4 and second clock signal CK2 is handed over Repeatedly.First clock CK1 can have the phase place of the opposite in phase with second clock CK2.When the 3rd Clock CK3 can have the phase place of the opposite in phase with the 4th clock CK4.

When the high level period of each clock signal is 1/2T, crossover section (overlapping Period) it is 1/2T.But, when the high level period of each clock signal is less than 1/2T, crossover Section can be less than 1/2T.

With reference to Fig. 2 A, Fig. 2 B and Fig. 4, drive the first and second gate driver circuits 210 and 230 Method substantially the same, therefore by letter with those methods described in foregoing exemplary embodiment Change the detailed description of any repeatability.(i-1) level SCi-1 of first grid drive circuit 210 is defeated Go out high level period synchronization with the first clock signal CK1 (i-1) individual carry signal Cri-1 and (i-1) individual signal Gi-1.I-stage SCi is in response to (i-1) individual carry signal Cri-1 And be actuated to export the i-th Tong Bu with the high level period 1/2T of second clock signal CK2 and enter Position signal Cri and i-th signal Gi.

The output of (j-1) level SCj-1 and the 3rd clock signal CK3 of second grid drive circuit 230 (j-1) individual carry signal Crj-1 of high level period synchronization and (j-1) individual signal Gj-1.J-th stage SCj is actuated to output and the in response to (j-1) individual carry signal Crj-1 Jth carry signal Crj of the high level period 1/2T synchronization of four clock signals CK4 and jth grid Pole signal Gj.

Fig. 5 shows the schematic diagram of the illustrative embodiments of the display floater of Fig. 1.

With reference to Fig. 1, Fig. 2 A, Fig. 2 B and Fig. 5, multiple pixels P1, P2 ..., P12 are positioned at aobvious Show in the viewing area DA of panel 100, and pixel P1, P2 ..., P12 are electrically connected to a plurality of Data wire DLm-1, DLm, DLm+1 and DLm+2 and a plurality of gate lines G Li-1, GLj-1, GLi and GLj.First grid drive circuit 210 is positioned at the first outer peripheral areas PA1 of display floater 100 In, and provide signal to gate lines G Li-1 and GLi.Second grid drive circuit 230 In the second outer peripheral areas PA2 of display floater 100, and provide to gate lines G Lj-1 and GLj Signal.

In an illustrative embodiments, such as, first pixel P1 of the first pixel column PL1 and Second pixel P2 and the 7th pixel P7 of the second pixel column PL2 and the 8th pixel P8 are positioned at (m-1) between data line DLm-1 and m data line DLm.First pixel column PL1's 3rd pixel P3 and the 4th pixel P4 and the 9th pixel P9 of the second pixel column PL2 and the tenth picture Element P10 is positioned between m data line DLm and (m+1) data line DLm+1.The 5th pixel P5 of one pixel column PL1 and the 6th pixel P6 and the tenth of the second pixel column PL2 the One pixel P11 and the 12nd pixel P12 are positioned at (m+1) data line DLm+1 and (m+2) Between data line DLm+2.First to the 6th pixel P1, P2 ..., P6 are sequentially disposed at In first pixel column PL1, and the 7th to the 12nd pixel P7, P8 ..., P12 sequentially arrange In the second pixel column PL2.

Each in 7th to the 12nd pixel P7, P8 ..., P12 is respectively relative to along column direction Each in first to the 6th pixel P1, P2 ..., P6 is arranged.As it is shown in figure 5, pixel column Pixel be electrically connected to the upper gate line that is positioned at the first side of pixel column or be positioned at same pixel column Lower gate line at second side.In an illustrative embodiments, such as, the first pixel column PC1 The first and the 7th each in pixel P1 and P7 be electrically connected to gate line, and the second pixel The second of row PC2 and the 8th each in pixel P2 and P8 is electrically connected to lower gate line.

(i-1) article gate lines G Li-1 is positioned at the first side (upside) place of the first pixel column PL1, And (j-1) article gate lines G Lj-1 is positioned at the second side (downside) place of the first pixel column PL1. (i-1) article and (j-1) article gate lines G Li-1 and GLj-1 are electrically connected to the first pixel column PL1 The first to the 6th pixel P1, P2 ..., P6.Article i-th, gate lines G Li is positioned at the second pixel column First side (upside) place of PL2, and j-th strip gate lines G Lj is positioned at the second pixel column PL2's Second side (downside) place.Article i-th, it is electrically connected to the second pixel with j-th strip gate lines G Li and GLj 7th to the 12nd pixel P7 of row PL2, P8 ..., P12.

For pixel P1 of the first pixel column PL1, P2 ..., P6, the first and second pixels P1 and P2 be all connected in adjacent (m-1) article and m data line DLm-1 and DLm M data line DLm, the third and fourth pixel P3 and P4 be all connected to adjacent the m article and (m+1) data line DLm+1 in (m+1) data line DLm and DLm+1, And the 5th and the 6th pixel P5 and P6 are all connected to adjacent (m+1) article and (m+2) (m+2) data line DLm+2 in data line DLm+1 and DLm+2.

The first, the the 3rd and the 6th pixel P1, P3 and P6 are connected to be positioned at (i-1) at upside Bar gate lines G Li-1, and under the second, the 4th and the 5th pixel P2, P4 and P5 are connected to be positioned at (j-1) article gate lines G Lj-1 at side.Therefore, pixel P1 of the first pixel column PL1, P2 ..., P6 can be by (i-1) level SCi-1 of first grid drive circuit 210 and second grid drive circuit (j-1) level SCj-1 of 230 drives.

For pixel P7 of the second pixel column PL2, P8 ..., P12, the 7th and the 8th pixel P7 It is all connected in adjacent (m-1) article and m data line DLm-1 and DLm with P8 (m-1) data line DLm-1, the 9th and the tenth pixel P9 and P10 are all connected to phase The adjacent m data line DLm in the m article and (m+1) data line DLm and DLm+1, And the 11st and the 12nd pixel P11 and P12 are all connected to adjacent (m+1) article and (m+2) (m+1) data line DLm+1 in data line DLm+1 and DLm+2.

Seven, the 9th and the 12nd pixel P7, P9 and P12 be connected to be positioned at i-th article at upside Gate lines G Li, and the eight, the tenth and under the 11st pixel P8, P10 and P11 be connected to be positioned at J-th strip gate lines G Lj at side.Therefore, pixel P7 of the second pixel column PL2, P8 ..., P12 Can be by i-stage SCi of first grid drive circuit 210 and the of second grid drive circuit 230 J level SCj drives.

In an illustrative embodiments, such as, when display floater 100 include redness, green and During blue pixel, in the first pixel column PL1, first and the 4th pixel P1 and P4 can be blue Pixel, second and the 5th pixel P2 and P5 can be red pixel, and the 3rd and the 6th pixel P3 and P6 can be green pixel.It addition, in the second pixel column PL2, the 7th and the tenth pixel P7 and P10 is blue pixel, the 8th and the 11st pixel P8 and P11 be red pixel, and Nine and the 12nd pixel P9 and P12 be green pixel.

The second, the five, the 8th and the 11st pixel P2, P5, P8 accordingly, as red pixel It is electrically connected to (j-1) article and j-th strip gate lines G Lj-1 and GLj, in order to by second gate with P11 Pole drive circuit 230 drives.The three, the six, the 9th and the 12nd pixel as green pixel P3, P6, P9 and P12 are electrically connected to (i-1) article and i-th article of gate lines G Li-1 and GLi, with Just driven by first grid drive circuit 210.As blue pixel the first, the 4th, the 7th and Ten pixels P1, P4, P7 and P10 be electrically connected to (i-1) article, (j-1) article, i-th article and J-th strip gate lines G Li-1, GLj-1, GLi and GLj, in order to by the first and second raster data model electricity Road 210 and 230 drives.

Fig. 6 A to 6C shows according to each color images included in the display floater of Fig. 1 Driving that element is carried out and the schematic diagram of the illustrative embodiments of picture quality that obtains.

With reference to Fig. 5 and Fig. 6 A, it is multiple red that the display floater 100 shown in Fig. 6 A illustrates driving Color pixel R.The red pixel R of the first pixel column PL1 is connected to be positioned at the first pixel column PL1's Gate line at Xia Ce, and the red pixel R of the second pixel column PL2 is connected to be positioned at the second picture Gate line at the downside of element row PL2.Therefore, red pixel R is connected to relative to pixel line position Gate line at downside.The red pixel R of display floater 100 is by the gate line being positioned at downside The second grid drive circuit 230 providing signal drives.

Therefore, the signal produced from second grid drive circuit 230 drives towards with second grid The first grid drive circuit 210 that circuit 230 is relative transmits.Due to the resistance of gate line, applying To be adjacent to second grid drive circuit 230 red pixel R signal with apply to being adjacent to It is likely to occur delay between the signal of the red pixel R of first grid drive circuit 210 poor, makes Obtain red pixel R and be likely to be of the charge difference gradually changed owing to postponing difference.But, at all pictures Element row PL1, PL2, PL3 ... in charge difference occurs equably so that will not due to charge difference Display floater 100 occurs red significant difference.

With reference to Fig. 5 and Fig. 6 B, it is multiple green that the display floater 100 shown in Fig. 6 B illustrates driving Color pixel G.The green pixel G of the first pixel column PL1 is connected to be positioned at the first pixel column PL1's Gate line at Shang Ce, and the green pixel G of the second pixel column PL2 is connected to be positioned at the second picture Gate line at the upside of element row PL2.Therefore, green pixel G is connected to relative to pixel line position Gate line at upside.The green pixel G of display floater 100 is by the gate line being positioned at upside The first grid drive circuit 210 providing signal drives.

Therefore, the signal produced from first grid drive circuit 210 drives towards with first grid The second grid drive circuit 230 that circuit 210 is relative transmits.Due to the resistance of gate line, applying To being adjacent to the green pixel G of first grid drive circuit 210 and applying to being adjacent to second grid to drive Delay it is likely to occur poor so that green pixel between the signal of the green pixel G on galvanic electricity road 230 G is likely to be of the charge difference gradually changed owing to postponing difference.But, all pixel column PL1, PL2, PL3 ... occur charge difference equably so that will not be due to charge difference at display floater Green significant difference occurs in 100.

With reference to Fig. 5 and Fig. 6 C, the display floater 100 shown in Fig. 6 C illustrates the multiple indigo plants of driving Color pixel B.Blue pixel B of the first pixel column PL1 is connected to be positioned at the first pixel column PL1's Gate line at the upper side and lower side, and blue pixel B of the second pixel column PL2 is connected to be positioned at Gate line at the upper side and lower side of second pixel column PL2.Therefore, blue pixel B all connects To laying respectively at all gate lines at the upper side and lower side relative to pixel column.The indigo plant of display floater 100 Color pixel B is provided the first of signal respectively by all gate lines being positioned at the upper side and lower side Drive with second grid drive circuit 210 and 230.

Accordingly, because the resistance of gate line, it is being adjacent to the blueness picture of first grid drive circuit 210 It is likely to occur charge difference between element B and blue pixel B being adjacent to second grid drive circuit 230, Allow to the defect that such as vertical line occurs due to charge difference.But, compared with redness or green, Blueness is difficult to be identified, thus without reducing display quality.

According to the dot structure of shown illustrative embodiments, the first and second gate driver circuits In 210 and 230 one provides signal to the upper gate line of pixel column, and another is to this The lower gate line of pixel column provides signal.Therefore, do not have owing to the delay of signal is poor The significant difference of the display quality caused.

Fig. 7 A to 7B shows the exemplary of the presentation quality improvement of the display device according to Fig. 1 The schematic diagram of embodiment.

With reference to Fig. 1 and Fig. 7 A, two circuit-level are positioned at the first outer peripheral areas PA1 of display floater 500 In, and two signals are respectively supplied to be positioned at the upside of pixel column PLc by these two circuit-level With two gate lines at downside.

In this case, these two circuit-level be positioned at the first outer peripheral areas PA1 with pixel column PLc Region corresponding for width W in.That is, these two circuit-level the overall width occupied is not more than picture The width W of element row PLc so that these two circuit-level are fully located in the width W of pixel column PLc. Therefore, these two circuit-level are positioned in the region with width W so that can increase and display floater The width BW1 of the frame that the outer peripheral areas of 500 is corresponding.

With reference to Fig. 1 and Fig. 7 B, according to shown illustrative embodiments, two circuit-level positions respectively In first and second outer peripheral areas PA1 and PA2 of display floater 600, and by two grids Signal is respectively supplied to two gate lines being positioned at the upper side and lower side of pixel column Ple.Such as Fig. 6 A Described in Fig. 6 C, do not have the display matter caused due to the delay difference of two signals The significant difference of amount.The first circuit-level in these two circuit-level may be located at the first outer peripheral areas PA1 In, and the second circuit level in these two circuit-level may be located in the second outer peripheral areas PA2.

In this case, the first circuit-level may be located at the first outer peripheral areas PA1 and pixel column In the region corresponding for width W of PLe, and second circuit level may be located at the second outer peripheral areas In the region corresponding with the width W of pixel column PLe of PA2.Periphery with display floater 600 The width BW2 of the frame that region is corresponding can be less at least about than the width BW1 described in Fig. 7 A 50%.

Therefore, in there is the display floater 600 of dot structure of shown illustrative embodiments, Border width can be reduced so that the presentation quality of display device can be improved.

Hereinafter, use same reference numerals is represented retouched in illustrative embodiments before The same or analogous parts of parts stated, and the detailed description of any repeatability will be omitted.

Fig. 8 shows the signal of the another exemplary embodiment of the display floater according to the present invention Figure.

With reference to Fig. 1, Fig. 3 and Fig. 8, display floater 600 include first grid drive circuit 210, First discharge circuit 241, second grid drive circuit 230 and the second discharge circuit 242.

First grid drive circuit 210 include level SCi-1 that is positioned in the first outer peripheral areas PA1 and Each in SCi, and level SCi-1 and SCi is to the grid being positioned at the first side of each pixel column Polar curve GLi-1 and GLi provides signal.First grid drive circuit 210 is electrically connected to gate line First end of GLi-1 and GLi.

First discharge circuit 241 is positioned in the second outer peripheral areas PA2.First discharge circuit 241 electricity It is connected to second end relative with the first end of gate lines G Li-1 and GLi, and will apply to every The high voltage VON of the signal of gate lines G Li-1 or GLi is discharged into low-voltage VOFF.The One discharge circuit 241 includes the first discharge transistor TR1 and transmits the pressure-wire of low-voltage VOFF VL.As shown in Figure 8, the first discharge transistor TR1 between level SCj-1 and SCj-2 second In outer peripheral areas PA2, and be positioned at by (i-1) article and (j-1) article gate lines G Li-1 And the width corresponding (such as less than this width) of the pixel column of the distance restriction between GLj-1 In second outer peripheral areas PA2.

First discharge transistor TR1 includes the first control electrode, the first input electrode and the first output Electrode.In an illustrative embodiments, such as, the first control electrode is connected to and i-stage SCi I-th gate lines G Li connected, the first input electrode is connected to (i-1) article gate lines G Li-1, And the first output electrode is connected to pressure-wire VL.When high voltage VON applies to i-th gate line During GLi, the first discharge transistor TR1 conducting.First discharge transistor TR1 will put on (i-1) The high voltage VON of bar gate lines G Li-1 is discharged into low-voltage VOFF.

Second grid drive circuit 230 include level SCj-1 that is positioned in the second outer peripheral areas PA2 and Each in SCj, and level SCj-1 and SCj is to the grid being positioned at the second side of each pixel column Polar curve GLj-1 and GLj provides signal.Second grid drive circuit 230 is electrically connected to gate line Second end of GLj-1 and GLj.

Second discharge circuit 242 is positioned in the first outer peripheral areas PA1.Second discharge circuit 242 electricity Be connected to first end of gate lines G Lj-1 and GLj, and will put on every gate lines G Lj-1 or The high voltage VON of the signal of GLj is discharged into low-voltage VOFF.Second discharge circuit 242 Including the second discharge transistor TR2 and the pressure-wire VL of transmission low-voltage VOFF.As shown in Figure 8, In the second discharge transistor TR2 the first outer peripheral areas PA1 between level SCi-1 and SCi, And it is positioned at and by (i-1) article and (j-1) distance article between gate lines G Li-1 and GLj-1 First outer peripheral areas PA1 of the width corresponding (such as less than this width) of the pixel column limited In.

Second discharge transistor TR2 includes the second control electrode, the second input electrode and the second output Electrode.In an illustrative embodiments, such as, the second control electrode is connected to and j-th stage SCj J-th strip gate lines G Lj connected, the second input electrode is connected to (j-1) article gate lines G Lj-1, And the second output electrode is connected to pressure-wire VL.When high voltage VON applies to j-th strip gate line During GLj, the second discharge transistor TR2 conducting.Second discharge transistor TR2 will put on (j-1) The high voltage VON of bar gate lines G Lj-1 is discharged into low-voltage VOFF.

Fig. 9 shows the signal of the another exemplary embodiment of the display floater according to the present invention Figure.

With reference to Fig. 1, Fig. 2 A, Fig. 2 B and Fig. 9, display floater 700 wraps in the DA of viewing area Include a plurality of data lines DLm-1, DLm and DLm+1, a plurality of gate lines G Li-1, GLj-1, GLi With GLj and be electrically connected to data wire DLm-1, DLm and DLm+1 and gate lines G Li-1, Multiple pixels P1 of GLj-1, GLi and GLj, P2 ..., P12.Display floater 700 includes being positioned at The first grid to gate lines G Li-1 and GLi offer signal in first outer peripheral areas PA1 drives Believing to gate lines G Lj-1 and GLj offer grid in galvanic electricity road 210 and the second outer peripheral areas PA2 Number second grid drive circuit 230.

In an illustrative embodiments, such as, (m-1) data line DLm-1 is positioned at Between first pixel P1 and second pixel P2 of the first pixel column PL1, and it is positioned at the second pixel column Between 7th pixel P7 and the 8th pixel P8 of PL2.M data line DLm is positioned at the first picture Between 3rd pixel P3 and the 4th pixel P4 of element row PL1, and it is positioned at the second pixel column PL2 The 9th pixel P9 and the tenth pixel P10 between.(m+1) data line DLm+1 is positioned at Between 5th pixel P5 and the 6th pixel P6 of one pixel column PL1, and it is positioned at the second pixel column Between 11st pixel P11 and the 12nd pixel P12 of PL2.As it is shown in figure 9, first to the 6th Pixel P1, P2 ..., P6 are sequentially disposed in the first pixel column PL1, and the 7th to the tenth Two pixels P7, P8 ..., P12 are sequentially disposed in the second pixel column PL2.

Each in 7th to the 12nd pixel P7, P8 ..., P12 along column direction relative to first Each to the 6th pixel P1, P2 ..., P6 is arranged.As it is shown in figure 9, the picture of pixel column Element is electrically connected to the upper gate line being positioned at the first side of pixel column or the second side being positioned at this pixel column The lower gate line at place.In an illustrative embodiments, such as, the first of the first pixel column PC1 It is electrically connected to upper gate line, and the second pixel column PC2 with each in the 7th pixel P1 and P7 The second and the 8th each in pixel P2 and P8 be electrically connected to lower gate line.

(i-1) article gate lines G Li-1 is positioned at the first side (upside) place of the first pixel column PL1, And (j-1) article gate lines G Lj-1 is positioned at the second side (downside) place of the first pixel column PL1. (i-1) article and (j-1) article gate lines G Li-1 and GLj-1 are electrically connected to the first pixel column PL1 The first to the 6th pixel P1, P2 ..., P6.Article i-th, gate lines G Li is positioned at the second pixel column First side (upside) place of PL2, and j-th strip gate lines G Lj is positioned at the second pixel column PL2's Second side (downside) place.Article i-th, it is electrically connected to the second pixel with j-th strip gate lines G Li and GLj 7th to the 12nd pixel P7 of row PL2, P8 ..., P12.

For pixel P1 of the first pixel column PL1, P2 ..., P6, the first and second pixels P1 and P2 is all connected to (m-1) data line DLm-1, and the third and fourth pixel P3 and P4 are whole It is connected to m data line DLm, and the 5th and the 6th pixel P5 and P6 are all connected to (m+1) data line DLm+1.

The first, the the 4th and the 6th pixel P1, P4 and P6 are connected to (i-1) article gate lines G Li-1, And second, third and the 5th pixel P2, P3 and P5 are connected to (j-1) article gate lines G Lj-1. Therefore, pixel P1 of the first pixel column PL1, P2 ..., P6 can be by first grid drive circuit (i-1) level SCi-1 of 210 and (j-1) level SCj-1 of second grid drive circuit 230 are driven Dynamic.

For pixel P7 of the second pixel column PL2, P8 ..., P12, the 7th and the 8th pixel P7 It is all connected to (m-1) data line DLm-1, the 9th and the tenth pixel P9 and P10 with P8 Be all connected to m data line DLm, and the 11st and the 12nd pixel P11 and P12 complete Portion is connected to (m+1) data line DLm+1.

Seven, the tenth and the 12nd pixel P7, P10 and P12 be connected to i-th article of gate lines G Li, And the eight, the 9th and the 11st pixel P8, P9 and P11 be connected to j-th strip gate lines G Lj.Cause This, pixel P7 of the second pixel column PL2, P8 ..., P12 can be by first grid drive circuit I-stage SCi of 210 and j-th stage SCj of second grid drive circuit 230 drive.

In an illustrative embodiments, such as, when display floater 700 include redness, green and During blue pixel, in the first pixel column PL1, first and the 4th pixel P1 and P4 can be red Pixel, second and the 5th pixel P2 and P5 can be green pixel, and the 3rd and the 6th pixel P3 and P6 can be blue pixel.It addition, in the second pixel column PL2, the 7th and the tenth pixel P7 and P10 is red pixel, the 8th and the 11st pixel P8 and P11 be green pixel, and Nine and the 12nd pixel P9 and P12 be blue pixel.

Accordingly, as the first, the four, the 7th and the tenth pixel P1 of red pixel, P4, P7 and P10 is electrically connected to (i-1) article and i-th article of gate lines G Li-1 and GLi, in order to by first grid Drive circuit 210 drives.As green pixel the second, the five, the 8th and the 11st pixel P2, P5, P8 and P11 are electrically connected to (j-1) article and j-th strip gate lines G Lj-1 and GLj, in order to by Second grid drive circuit 230 drives.As blue pixel the three, the six, the 9th and the 12nd Pixel P3, P6, P9 and P12 be electrically connected to (i-1) article, (j-1) article, i-th article and J bar gate lines G Li-1, GLj-1, GLi and GLj, in order to by the first and second gate driver circuits Drive both 210 and 230.

Figure 10 A to 10C shows according to each colour included in the display floater of Fig. 9 Driving that pixel is carried out and the schematic diagram of the illustrative embodiments of picture quality that obtains.

With reference to Fig. 9 and Figure 10 A, it is multiple that the display floater 700 shown in Figure 10 A illustrates driving Red pixel R.The red pixel R of the first pixel column PL1 is connected to be positioned at the first pixel column PL1 Upside at gate line, and the red pixel R of the second pixel column PL2 is connected to be positioned at second Gate line at the upside of pixel column PL2.Therefore, red pixel R is connected to relative to pixel column It is positioned at the gate line at upside.The red pixel R of display floater 700 is by the grid being positioned at upside Line provides the first grid drive circuit 210 of signal to drive.

Therefore, the signal produced from first grid drive circuit 210 drives towards with first grid The second grid drive circuit 230 that circuit 210 is relative transmits.Due to the resistance of gate line, applying To being adjacent to the red pixel R of first grid drive circuit 210 and applying to being adjacent to second grid to drive Delay it is likely to occur poor so that red pixel between the signal of the red pixel R on galvanic electricity road 230 R is likely to be of the charge difference gradually changed owing to postponing difference.But, all pixel column PL1, PL2, PL3 ... occur charge difference equably so that will not be due to electric charge in display floater 700 Differ from and red significant difference occurs.

With reference to Fig. 9 and Figure 10 B, it is multiple that the display floater 700 shown in Figure 10 B illustrates driving Green pixel G.The green pixel G of the first pixel column PL1 is connected to be positioned at the first pixel column PL1 Downside at gate line, and the green pixel G of the second pixel column PL2 is connected to be positioned at second Gate line at the downside of pixel column PL2.Therefore, green pixel G is connected to relative to pixel column The gate line at downside being positioned in the upper side and lower side.The green pixel G of display floater 700 is by position Gate line at downside provides the second grid drive circuit 230 of signal to drive.

Therefore, the signal produced from second grid drive circuit 230 drives towards with second grid The first grid drive circuit 210 that circuit 230 is relative transmits.Due to the resistance of gate line, applying To being adjacent to the green pixel G of second grid drive circuit 230 and being adjacent to first grid drive circuit Delay it is likely to occur poor so that green pixel G may between the signal of the green pixel G of 210 There is the charge difference gradually changed owing to postponing difference.But, all pixel column PL1, PL2, PL3 ... occur charge difference equably so that will not be due to charge difference in display floater 700 Green significant difference occurs.

With reference to Fig. 9 and Figure 10 C, it is multiple that the display floater 700 shown in Figure 10 C illustrates driving Blue pixel B.Blue pixel B of the first pixel column PL1 is connected to be positioned at the first pixel column PL1 The upper side and lower side at gate line, and blue pixel B of the second pixel column PL2 is connected to position Gate line at the upper side and lower side of the second pixel column PL2.Therefore, blue pixel B all connects It is connected to lay respectively at all gate lines at the upper side and lower side relative to pixel column.Display floater 100 Blue pixel B is by providing the of signal to all gate lines being positioned at the upper side and lower side respectively One and second grid drive circuit 210 and 230 drive.

Accordingly, because the resistance of gate line, it is being adjacent to the blueness picture of first grid drive circuit 210 It is likely to occur charge difference between element B and blue pixel B being adjacent to second grid drive circuit 230, Allow to the defect that such as vertical line occurs due to charge difference.But, compared with redness or green, Blueness is difficult to be identified, and therefore display quality will not reduce.

According to the dot structure of shown illustrative embodiments, the first and second gate driver circuits Signal is supplied to the upper gate line of pixel column by 210 and 230, and another will Signal is supplied to the lower gate line of pixel column.Therefore, the delay due to signal is not had The significant difference of the display quality that difference causes.

Figure 11 shows the signal of the another exemplary embodiment of the display floater according to the present invention Figure.Display floater 800 according to shown illustrative embodiments is at the display floater 700 shown in Fig. 9 In also include the first and second discharge circuits 241 and 242 shown in Fig. 8.Hereinafter, will use Same reference numerals represent with illustrative embodiments before described in parts same or similar Parts, and will simplify any repeatability detailed description.

With reference to Fig. 9 and Figure 11, display floater 800 includes first grid drive circuit 210, first puts Electricity circuit 241, second grid drive circuit 230 and the second discharge circuit 242.

First grid drive circuit 210 include level SCi-1 that is positioned in the first outer peripheral areas PA1 and Each in SCi, and level SCi-1 and SCi is to the grid being positioned at the first side of each pixel column Polar curve GLi-1 and GLi provides signal.

First discharge circuit 241 is positioned in the second outer peripheral areas PA2.First discharge circuit 241 wraps Include the first discharge transistor TR1 and transmit the pressure-wire VL of low-voltage VOFF.As shown in figure 11, In the first discharge transistor TR1 the second outer peripheral areas PA2 between level SCj-1 and SCj-2, And it is positioned at and by (i-1) article and (j-1) distance article between gate lines G Li-1 and GLj-1 In the second outer peripheral areas PA2 that the width of pixel column that limits is corresponding.

First discharge transistor TR1 includes the first control electrode, the first input electrode and the first output Electrode.In an illustrative embodiments, such as, the first control electrode is connected to and i-stage SCi I-th gate lines G Li being connected, the first input electrode is connected to (i-1) article gate lines G Li-1, And the first output electrode is connected to pressure-wire VL.

Second grid drive circuit 230 include level SCj-1 that is positioned in the second outer peripheral areas PA2 and Each in SCj, and level SCj-1 and SCj is to the grid being positioned at the second side of each pixel column Polar curve GLj-1 and GLj provides signal.

Second discharge circuit 242 is positioned in the first outer peripheral areas PA1.Second discharge circuit 242 wraps Include the second discharge transistor TR2 and transmit the pressure-wire VL of low-voltage VOFF.As shown in figure 11, In the second discharge transistor TR2 the first outer peripheral areas PA1 between level SCi-1 and SCi, And it is positioned at and by (i-1) article and (j-1) distance article between gate lines G Li-1 and GLj-1 In the first outer peripheral areas PA1 that the width of pixel column that limits is corresponding.

Second discharge transistor TR2 includes the second control electrode, the second input electrode and the second output Electrode.In an illustrative embodiments, such as, the second control electrode is connected to and j-th stage SCj J-th strip gate lines G Lj being connected, the second input electrode is connected to (j-1) article gate lines G Lj-1, And the second output electrode is connected to pressure-wire VL.

According to above-mentioned illustrative embodiments, in the first and second gate driver circuits 210 and 230 One provides signal to the gate line being positioned at the first side of pixel column, and another is to being positioned at Gate line at second side relative with the first side of pixel column provides signal so that at high-resolution In rate display device, border width can be reduced and power consumption can be lowered.It addition, by above-mentioned The dot structure of illustrative embodiments, it is possible to reduce or effectively prevent owing to the delay of signal is poor And the significant difference produced.

It is above the exemplary illustration to the present invention, and is not necessarily to be construed as limiting the present invention.Although Through describing the illustrative embodiments of the present invention, but those skilled in the art can be easily geographical Solve, substantially without departing from the novel teachings of the present invention and advantage in the case of, can be to exemplary Embodiment carries out multiple modification.Therefore, all these modification are intended to be included in as in claim Defined in the scope of the present invention in.In the claims, device adds function (means-plus-function) statement is intended to cover the knot of function listed by described herein as performing Structure, and not only structural equivalents, and cover equivalent structure.It is, therefore, to be understood that with On be the exemplary illustration to the present invention, and should not be construed as limited to disclosed particular exemplary Embodiment, and to the modification of disclosed illustrative embodiments and other exemplary enforcement Mode will be intended to be included in scope of the following claims.The present invention is limited by claims Fixed, wherein the equivalent of claim will be included.

Claims (11)

1. a display floater, including:

Viewing area；

Outer peripheral areas, described outer peripheral areas is around described viewing area, and includes outside first Enclose region and second outer peripheral areas relative with described first outer peripheral areas；

Multiple pixels, are positioned in described viewing area, and include multiple pixel column and multiple Pixel column；

A plurality of data lines, described a plurality of data lines extends along column direction, wherein, every data Line corresponds to two pixel columns；

First grid polar curve, described first grid polar curve extends in the row direction, and is positioned at each institute State at the first side of pixel column；

Second gate line, described second gate line extends along described line direction, and is positioned at every At second side relative with described first side of individual described pixel column；

First grid drive circuit, is positioned in described first outer peripheral areas, and includes to institute State first grid polar curve and the first order of signal is provided；And

Second grid drive circuit, is positioned in described second outer peripheral areas, and includes to institute State second gate line and the second level of described signal be provided,

Wherein, the plurality of pixel includes multiple red pixel, multiple green pixel and multiple Blue pixel,

In described first grid polar curve and described second gate line one is electrically connected to each institute State red pixel, and another electricity in described first grid polar curve and described second gate line It is connected to each described green pixel,

Each of which in described first grid polar curve and described second gate line is electrically connected to institute State blue pixel,

The described first order is positioned in described first outer peripheral areas, and have less than or equal to by The pixel column width that distance between described first grid polar curve and described second gate line limits Width, and

The described second level is positioned in described second outer peripheral areas, and has less than or equal to institute State the width of pixel column width, and described display floater farther include:

(m-1) data line of order layout, m data line, (m+1) Data line and (m+2) data line, wherein, m is natural number,

Wherein,

It is included in the first pixel column and is positioned at described (m-1) data line with described The first pixel and the second pixel between m data line are electrically connected to described m data Line,

It is included in described first pixel column and is positioned at described m data line with described The 3rd pixel and the 4th pixel between (m+1) data line are electrically connected to described (m+1) data line, and

Be included in described first pixel column and be positioned at described (m+1) data line with The 5th pixel and the 6th pixel between described (m+2) data line are electrically connected to described (m+2) data line, and wherein

Described first pixel of described first pixel column, the 3rd pixel and the electrical connection of the 6th pixel To the described first grid polar curve being positioned at described first side of described first pixel column, and

Described second pixel of described first pixel column, the 4th pixel and the electrical connection of the 5th pixel To the described second gate line being positioned at described second side of described first pixel column.

Display floater the most according to claim 1, farther includes:

First clock line, first grid drive circuit described in described first clock alignment transmits the One clock signal；

3rd clock line, second grid drive circuit described in described 3rd clock alignment transmits the Three clock signals, described 3rd clock signal has first relative to described first clock signal It is poor to postpone；

Second clock line, first grid drive circuit described in described second clock alignment transmits the Two clock signals, described second clock signal has second relative to described first clock signal It is poor to postpone, and it is poor that described second delay difference postpones more than described first；And

4th clock line, second grid drive circuit described in described 4th clock alignment transmits the Four clock signals, described 4th clock signal has the 3rd relative to described first clock signal It is poor to postpone, and it is poor that described 3rd delay difference postpones more than described second.

Display floater the most according to claim 1, farther includes:

First discharge circuit, is adjacent to the described second level, and includes the first discharge transistor, The high-voltage discharge applied to described first grid polar curve is become low electricity by described first discharge transistor Pressure；And

Second discharge circuit, is adjacent to the described first order, and includes the second discharge transistor, The high-voltage discharge applied to described second gate line is become low electricity by described second discharge transistor Pressure.

Display floater the most according to claim 3, wherein,

The described first order and described second discharge transistor are positioned in described first outer peripheral areas, And have less than or equal to by between described first grid polar curve and described second gate line away from From the width of the pixel column width limited, and

The described second level and described first discharge transistor are positioned in described second outer peripheral areas, And there is the width less than or equal to described pixel column width.

Display floater the most according to claim 1, wherein, each institute being included in pixel column State pixel and be electrically connected to same gate line.

Display floater the most according to claim 5, wherein,

In single pixel column and between two data line adjacent one another are the first pictures Element and the second pixel are electrically connected to the same data wire in described two adjacent data line, and And

In described first grid polar curve and described second gate line one is electrically connected to described Another electrical connection in one pixel, and described first grid polar curve and described second gate line To described second pixel.

Display floater the most according to claim 1, wherein,

It is included in the second pixel column and is positioned at described (m-1) data line with described The 7th pixel and the 8th pixel between m data line are electrically connected to described (m-1) Data line,

It is included in described second pixel column and is positioned at described m data line with described (m+1) the 9th pixel and the tenth pixel between data line are electrically connected to described the m article Data wire, and

Be included in described second pixel column and be positioned at described (m+1) data line with The 11st pixel and the 12nd pixel between described (m+2) data line are electrically connected to Described (m+1) data line.

Display floater the most according to claim 7, wherein,

Described 7th pixel, the 9th pixel and the 12nd pixel of described second pixel column are electrically connected It is connected to the described first grid polar curve being positioned at described first side of described second pixel column, and

Described 8th pixel, the tenth pixel and the 11st pixel of described second pixel column are electrically connected It is connected to be positioned at the described second gate line at described second side of described second pixel column.

Display floater the most according to claim 5, wherein,

Adjacent one another are that every described data wire is electrically connected in single first pixel column Each in one pixel and the second pixel, and it is positioned at described first pixel and described second Between pixel, and

In described first grid polar curve and described second gate line one is electrically connected to described Described first pixel of one pixel column, and described first grid polar curve and described second gate line In another be electrically connected to described second pixel of described first pixel column.

10. a display device, including:

Display floater, including:

Viewing area,

Outer peripheral areas, described outer peripheral areas is around described viewing area, and includes One outer peripheral areas and second outer peripheral areas relative with described first outer peripheral areas,

Multiple pixels, are positioned in described viewing area, and include multiple pixel column and Multiple pixel columns,

A plurality of data lines, described a plurality of data lines extends along column direction, wherein every number According to line corresponding to two pixel columns,

First grid polar curve, described first grid polar curve extends in the row direction, and is positioned at every At first side of individual described pixel column,

Second gate line, described second gate line extends along described line direction, and position At second side relative with described first side of each described pixel column,

First grid drive circuit, is positioned in described first outer peripheral areas, and includes The first order of signal is provided to described first grid polar curve, and

Second grid drive circuit, is positioned in described second outer peripheral areas, and includes The second level of described signal is provided to described second gate line；And

Printed circuit board (PCB), described printed circuit board (PCB) is electrically connected to described display floater, and has There are the main drive circuit installed on the printed circuit board, wherein, described main drive circuit Produce and be provided to the of described first grid drive circuit and described second grid drive circuit One clock signal, second clock signal, the 3rd clock signal and the 4th clock signal,

Wherein, the plurality of pixel includes multiple red pixel, multiple green pixel and multiple Blue pixel,

In described first grid polar curve and described second gate line one is electrically connected to each institute State red pixel, and another electricity in described first grid polar curve and described second gate line It is connected to each described green pixel,

Each of which in described first grid polar curve and described second gate line is electrically connected to institute State blue pixel,

The described first order is positioned in described first outer peripheral areas, and have less than or equal to by The pixel column width that distance between described first grid polar curve and described second gate line limits Width, and

The described second level is positioned in described second outer peripheral areas, and has less than or equal to institute State the width of pixel column width, and described display floater farther include:

(m-1) data line of order layout, m data line, (m+1) Data line and (m+2) data line, wherein, m is natural number,

Wherein,

It is included in the first pixel column and is positioned at described (m-1) data line with described The first pixel and the second pixel between m data line are electrically connected to described m data Line,

It is included in described first pixel column and is positioned at described m data line with described The 3rd pixel and the 4th pixel between (m+1) data line are electrically connected to described (m+1) data line, and

Be included in described first pixel column and be positioned at described (m+1) data line with The 5th pixel and the 6th pixel between described (m+2) data line are electrically connected to described (m+2) data line, and wherein

Described first pixel of described first pixel column, the 3rd pixel and the electrical connection of the 6th pixel To the described first grid polar curve being positioned at described first side of described first pixel column, and

Described second pixel of described first pixel column, the 4th pixel and the electrical connection of the 5th pixel To the described second gate line being positioned at described second side of described first pixel column.

11. display devices according to claim 10, wherein, described printed circuit board (PCB) includes:

Multiple first holding wires, transmit described first clock to described first grid drive circuit Signal and described second clock signal；

Multiple secondary signal lines, transmit described 3rd clock to described second grid drive circuit Signal and described 4th clock signal；And

Resistance-capacitance control portion, controls described first holding wire and the electricity of described secondary signal line Resistance-capacity time constant.