CN102610751A - Method for preparing small hole of nano-sized resistive random access memory - Google Patents
Method for preparing small hole of nano-sized resistive random access memory Download PDFInfo
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- CN102610751A CN102610751A CN2012100465705A CN201210046570A CN102610751A CN 102610751 A CN102610751 A CN 102610751A CN 2012100465705 A CN2012100465705 A CN 2012100465705A CN 201210046570 A CN201210046570 A CN 201210046570A CN 102610751 A CN102610751 A CN 102610751A
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Abstract
The invention discloses a method for preparing a small hole of a nano-sized resistive random access memory. The preparation method disclosed by the invention comprises the step of using a sacrifice layer corrosion method to prepare the small hole of the nano-sized resistive random access memory. The direction of the small hole can be vertical and horizontal, as well as at any in other directions. The preparation method disclosed by the invention can be used for preparing small holes of any shapes; and the minimal precision of the small hole can reach up to 20 nanometers. The preparation method is high in precision, simple in process and low in cost.
Description
Technical field
The present invention relates to microelectronic process engineering, relate in particular to a kind of sacrifice layer corrosion legal system of utilizing and be equipped with the method that the nano-scale resistance becomes the memristor aperture.
Background technology
Microelectronic industry is related to the every aspect of people's life, and from handheld devices such as mobile phone, notebook computers, to high tip device such as supercomputer, radar, satellites, microelectronic product has almost covered people's various fields in life.Memory then is a requisite device in the various device, and wherein resistance-variable storing device is simple in structure owing to having, area is little, be convenient to advantages such as extensive integrated, becomes the strong candidate of memory of future generation.Typical resistance-variable storing device has the metal-insulator-metal type mim structure, and insulator (resistance becomes material) between double layer of metal (electrode) determined its area by being clipped in.Be that usefulness is peeled off or all very difficult area with electrode of the way of wet etching reduces.The area that therefore how will be clipped in the resistance change material between double layer of metal reduces the size that affects its integrated level to a great extent.Adopt aperture to fill the area of the resistance change material that way that resistance becomes material can reduce contact with double layer of metal well, thus how effectively to prepare small size particularly the nano-scale aperture very big effect will be arranged the lifting of resistance-variable storing device integrated level.
Summary of the invention
Problem to above prior art need solve proposes the present invention.
The object of the present invention is to provide a kind of nano-scale resistance to become the preparation method of memristor aperture.
The preparation method that nano-scale resistance of the present invention becomes the memristor aperture may further comprise the steps:
1) prepares deposit sacrifice layer on the substrate of aperture at needs; The thickness of sacrifice layer is by the degree of depth decision of prepared aperture; Generally between 2nm and 500nm, also can in the scope that the microelectronic technique processing conditions is allowed, carry out freely selecting according to the degree of depth of prepared aperture;
2) resist coating;
3) carry out photoetching, define the figure of sacrifice layer;
4) dry etching sacrifice layer;
5) remove photoresist, with the figure transfer on the photoresist to sacrifice layer;
6) deposit need prepare the material layer of aperture, and thickness is identical with the thickness of sacrifice layer, also can be a bit larger tham the thickness of sacrifice layer;
7) chemico-mechanical polishing, the polish stop stop is as the criterion with the figure top of sacrifice layer;
8) wet etching sacrifice layer obtains the aperture of required preparation.
Substrate is generally the Si substrate, also can be glass substrate etc.; This substrate can be the substrate that has passed through the microelectronic technique processed and comprised microelectronic component, also can be the substrate that does not pass through the microelectronic technique processed.The material of sacrifice layer is a kind of in the materials such as silicon dioxide, silicon nitride and phosphorosilicate glass.Material layer adopts polysilicon or silica etc.
The preparation method that nano-scale resistance of the present invention becomes the memristor aperture can be used for preparing the aperture of Any shape, and the direction of aperture can be vertical, can be level, also can be any other direction.The concrete figure of preparing aperture is decided by the figure of sacrifice layer.The figure that lithographic definition goes out sacrifice layer can adopt optical lithography, also can adopt electron beam lithography, and minimum precision can reach 20nm.Aspect the corrosive liquid of selecting the wet etching sacrifice layer, corrosive liquid need be far longer than the corrosion rate to material layer for the corrosion rate of sacrifice layer.
Advantage of the present invention:
Method of the present invention utilizes the sacrifice layer corrosion method to prepare the aperture that the nano-scale resistance becomes memristor, and preparation method provided by the present invention can be used for preparing the aperture of Any shape, and minimum precision can reach 20nm.Preparation method's precision of the present invention is high, technology is simple, cost is low.
Description of drawings
Fig. 1 is the schematic flow sheet of embodiments of the invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further specified through instance.
It is following that preparation lines diameter is about the method step of aperture of 20nm:
1) chemical vapour deposition (CVD) is the sacrifice layer 2 of silicon nitride on silicon substrate 1, and thickness is 300nm, shown in Fig. 1 (a);
2) being coated with electron beam resist 3, shown in Fig. 1 (b) on the sacrifice layer 2 of silicon nitride;
3) lithographic definition goes out the figure of sacrifice layer, shown in Fig. 1 (c);
4) reactive ion etching RIE sacrifice layer 300nm, with the figure transfer on the photoresist to sacrifice layer, shown in Fig. 1 (d);
5) remove photoresist, shown in Fig. 1 (e);
6) chemical vapor deposition 400nm silica is as material layer 4, shown in Fig. 1 (f);
7) substrate is carried out chemico-mechanical polishing, the polish stop stop is as the criterion with the figure top of sacrifice layer, shown in Fig. 1 (g);
8) with 1: 10～1: 40 hydrofluoric acid HF and the mixed liquor of ammonium fluoride NH4F (BHF solution) or HF solution wet etching silicon nitride, obtain required aperture, shown in Fig. 1 (h).
It should be noted that at last; The purpose of publicizing and implementing mode is to help further to understand the present invention; But it will be appreciated by those skilled in the art that: in the spirit and scope that do not break away from the present invention and appended claim, various replacements and to revise all be possible.Therefore, the present invention should not be limited to the disclosed content of embodiment, and the scope that the present invention requires to protect is as the criterion with the scope that claims define.
Claims (9)
1. the preparation method of a nano-scale resistance change memristor aperture is characterized in that, may further comprise the steps:
1) prepares deposit sacrifice layer on the substrate of aperture at needs;
2) resist coating;
3) carry out photoetching, define the figure of sacrifice layer;
4) dry etching sacrifice layer;
5) remove photoresist, with the figure transfer on the photoresist to sacrifice layer;
6) deposit need prepare the material layer of aperture;
7) chemico-mechanical polishing, the polish stop stop is as the criterion with the figure top of sacrifice layer;
8) wet etching sacrifice layer obtains the aperture of required preparation.
2. preparation method as claimed in claim 1 is characterized in that, in step 1), said substrate is Si substrate or glass substrate etc.
3. preparation method as claimed in claim 1 is characterized in that, in step 1), the material of said sacrifice layer is a kind of in the materials such as silicon dioxide, silicon nitride and phosphorosilicate glass.
4. preparation method as claimed in claim 1 is characterized in that, in step 1), the thickness of said sacrifice layer is between 2nm and 500nm
5. preparation method as claimed in claim 1 is characterized in that, in step 3), optical lithography or electron beam lithography are adopted in photoetching.
6. preparation method as claimed in claim 1 is characterized in that, in step 6), said material layer adopts polysilicon or silica etc.
7. preparation method as claimed in claim 1 is characterized in that, in step 6), the thickness of said material layer is identical with the thickness of sacrifice layer, or is a bit larger tham the thickness of sacrifice layer.
8. preparation method as claimed in claim 1 is characterized in that, in step 8), the corrosive liquid that the wet etching sacrifice layer adopts is far longer than the corrosion rate to material layer for the corrosion rate of sacrifice layer.
9. preparation method as claimed in claim 8 is characterized in that, said corrosive liquid is 1: 10～1: 40 hydrofluoric acid HF and mixed liquor or the HF solution of ammonium fluoride NH4F.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100465705A CN102610751A (en) | 2012-02-27 | 2012-02-27 | Method for preparing small hole of nano-sized resistive random access memory |
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| CN2012100465705A CN102610751A (en) | 2012-02-27 | 2012-02-27 | Method for preparing small hole of nano-sized resistive random access memory |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080131994A1 (en) * | 2006-12-01 | 2008-06-05 | Heon Yong Chang | Method for manufacturing phase change memory device which can stably form an interface between a lower electrode and a phase change layer |
| CN101872838A (en) * | 2008-04-22 | 2010-10-27 | 旺宏电子股份有限公司 | Memory cell having a buried phase change region and method for fabricating the same |
| CN102347442A (en) * | 2010-07-29 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for making phase change memory structure |
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2012
- 2012-02-27 CN CN2012100465705A patent/CN102610751A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080131994A1 (en) * | 2006-12-01 | 2008-06-05 | Heon Yong Chang | Method for manufacturing phase change memory device which can stably form an interface between a lower electrode and a phase change layer |
| CN101872838A (en) * | 2008-04-22 | 2010-10-27 | 旺宏电子股份有限公司 | Memory cell having a buried phase change region and method for fabricating the same |
| CN102347442A (en) * | 2010-07-29 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for making phase change memory structure |
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Application publication date: 20120725 |