CN102609380A - SDRAM (synchronous dynamic random access memory) controller data writing quick response method based on AXI (advanced extensible interface) bus - Google Patents
SDRAM (synchronous dynamic random access memory) controller data writing quick response method based on AXI (advanced extensible interface) bus Download PDFInfo
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Abstract
The invention provides an SDRAM (synchronous dynamic random access memory) controller data writing quick response method based on an AXI (advanced extensible interface) bus. When an SDRAM controller receives data writing command requests transmitted from various AXI main devices, the data writing commands are placed in a reading and writing command queuing register by the SDRAM controller to wait for processing, simultaneously, to-be-written data of the AXI main devices are placed in a data cache area to wait for processing, and at the moment, the SDRAM controller does not need to wait for the to-be-written data to be written into peripheral equipment of the SDRAM controller but directly transmits data writing completion response to the AXI main devices; and when one of the AXI main devices simultaneously performs data reading operation for the SDRAM controller, the SDRAM controller needs to filter writing operation for the same address by the aid of an address filter module, so that consistency of data in the data cache area is prevented from being destroyed when the SDRAM controller performs data reading and writing operation. Accordingly, data writing efficiency of the SDRAM controller is improved.
Description
[technical field]
The present invention relates to the design field of SOC chip, particularly a kind of sdram controller write data fast response method based on the AXI bus.
[background technology]
The SDARM controller is the important module in the SOC chip, mainly is responsible for the storage of dynamic data in the SOC system.AMBA3 AXI bus is widely used in embedding in the SOC chip, supports the sdram controller of AMBA3 AXI bus to be widely used in the SOC System on Chip/SoC at present.The data-handling capacity that improves the SDRAM bus is important indicator of design sdram controller.
The structure of present sdram controller; As shown in Figure 1; SDRAM comprises AXI EBI, data buffer area, read write command queuing register, moderator, command processing unit and SDRAM protocol controller; Wherein the AXI EBI mainly is used for the read write command on the AXI main equipment is converted to the sdram controller internal command and submits to the moderator arbitration, simultaneously data is write data buffer area, and it is medium pending that the order after the arbitration is put into the read write command queuing register.After write order after the command processing unit receives arbitration simultaneously and the data that will write, the data that will write are write the external unit of sdram controller; By the time after data processing was accomplished, the AXI EBI sent the response signal that transmission is accomplished to the AXI main equipment, if the read data order is returned read data simultaneously and given the AXI main equipment.In order to improve the execution efficient of SDRAM protocol controller, present sdram controller is generally supported the caching function of write data, and the order of write order and read data is arbitrated according to the characteristic of SDRAM.
But present sdram controller is in application; If have a plurality of AXI main equipments simultaneously frequent carry out reading and writing data to sdram controller; The write data of a main equipment in wherein a plurality of AXI main equipments possibly deposited in always and can not get timely processing in the data buffer area; Can let the SDRAM protocol controller become very long toward the time of the outer SDRAM peripheral hardware write data of sheet like this, this AXI main equipment just can be received response signal after data are sent a very long time like this, can be in waiting status so always; Do not do further processing, influenced the execution efficient of this AXI main equipment.For example: in Fig. 1, be example with AXI main equipment 0, sdram controller common treatment scheme when handling the write data requests of AXI main equipment 0 is: begin WR0 earlier, then WR1, WR2 at last.WR0:AXI main equipment 0 sends one and writes request, and sends to sdram controller to write data; The WR1:SDRAM controller sends to write data in the outer SDRAM peripheral hardware of sheet; WR2: when data are successfully write outside the sheet behind the SDRAM, AXI slave unit interface is replied OKAY (agreements) response to AXI main equipment 0, represent that current write data transmits completion.At this moment; If have a plurality of AXI main equipments simultaneously frequent carry out reading and writing data to sdram controller, the write data of AXI main equipment 0 possibly deposited in always and can not get timely processing in the buffer memory in certain time, can let the time of WR1 become very long like this; AXI main equipment 0 just can be received response signal after data are sent a very long time like this; Can be in waiting status so always, not do further processing, influence the execution efficient of this AXI main equipment.
A kind of " access control method of synchronous dynamic random access memory and synchronous dynamic storage controller " is provided in the prior art; See that publication number is: CN101021819 open day was: the Chinese patent of 2007.08.22, the wherein access control method of synchronous dynamic random access memory SDRAM; Its unique point is; Comprise: after sdram controller is received the visit order to SDRAM, judge in the visit order of self buffer memory whether have the operation of going together, if exist with the visit order of receiving; Then after the cache access order with the visit order insertion colleague who receives, preferentially carry out the visit order of going together; Otherwise, the visit order of receiving is inserted in the scheduling queue according to the normal consistency flow process.Synchronous dynamic random access memory sdram controller wherein; Its unique point is to comprise: bus on chip protocol interface, main control unit and distinguish control module one to one with each district of SDRAM, wherein; Main control unit; The visit order from the bus on chip protocol interface that is used for receiving is broadcast to each district's control module, and is used to receive the district's operation application from district's control module, preferentially authorizes existence with pairing district, the district of line operate control module with access rights; District's control module, be used for receive belong to local area visit order insert scheduling queue, and, behind gain access, corresponding district is conducted interviews to main control unit sending area operation application.This invention proposes a kind of arbitration and dispatching algorithm according to characteristics of SDRAM, in its dispatching algorithm is together to handle with multi-region processing with line command SDRAM etc.; This invention can not realize the quick response of sdram controller write data.
[summary of the invention]
The technical matters that the present invention will solve is to provide the sdram controller write data fast response method based on the AXI bus.
The present invention is achieved in that a kind of sdram controller write data fast response method based on the AXI bus, and said sdram controller comprises AXI slave unit interface, data buffer area, read write command queuing register, moderator, command processing unit and SDRAM protocol controller; Said sdram controller also comprises the address filtering module;
Said method is: sdram controller is when receiving the write data command request of each the AXI main equipment transmission that is connected with the AXI bus; Sdram controller changes into each write data order the sdram controller internal command and submits to said moderator arbitration through said address filtering module through said AXI slave unit interface; It is medium pending that each write data order after the arbitration is put into said read write command queuing register; It is medium pending that the data that simultaneously each AXI main equipment will be write are put into said data buffer area; This moment, sdram controller need not wait for that the data that will write write the external unit of sdram controller, but directly sent the response that write data is accomplished to each AXI main equipment correspondence; Carry out read data when operation to sdram controller simultaneously as a certain AXI main equipment; Then sdram controller needs to filter the write operation of identical address through described address filtering module, when avoiding sdram controller to read and write data in the said data buffer area consistance of data destroyed;
The write operation that said address filtering module is filtered identical address is specially: after said address filtering module receives the read data order of a certain AXI main equipment transmission; Order corresponding address whether consistently to compare with each write data in the said read-write queuing register address of this read data order earlier; Be then to operate by the normal consistency flow process; Not; Then with current read data order carrying out locking; After the data that all write datas orders of the address correlation of in said read-write queuing register, ordering with this read data all carry out writing are write the external unit of sdram controller; Again said moderator being delivered in this read data order arbitrates; The order of read data after the arbitration is put in the said read write command queuing register, during read data order after the command processing unit receives arbitration, reads desired data return to said transmission read data order through said SDRAM protocol controller AXI main equipment from the external unit of sdram controller.
Further; Said normal consistency flow process is operated and is the data that will write that said command processing unit receives each write data order and each write data order correspondence; The said data that respectively will write are write the external unit of sdram controller through said SDRAM protocol controller; Simultaneously said moderator being delivered in said read data order arbitrates; Read data order after the arbitration is put in the said read write command queuing register; During the order of read data after the command processing unit receives arbitration, read desired data return to said transmission read data order through said SDRAM protocol controller AXI main equipment from the external unit of sdram controller.
The invention has the advantages that: the present invention improves on existing sdram controller; Added the address filtering module; And wherein sdram controller is when receiving the write data command request of each AXI main equipment transmission; It is medium pending that sdram controller is put into the read write command queuing register with the order of each write data; It is medium pending that the data that simultaneously each AXI main equipment will be write are put into data buffer area, and this moment, sdram controller need not wait for that the data that will write write the external unit of sdram controller, but directly sent the response that write data is accomplished to each AXI main equipment correspondence; But processing can cause the ruined problem of data consistency in the sdram controller like this.In order to address this problem; On sdram controller, add the address filtering module; When a certain AXI main equipment carries out read data when operation to sdram controller simultaneously; Sdram controller needs to filter the write operation of identical address through the address filtering module, when avoiding sdram controller to read and write data in the data buffer area consistance of data destroyed; Thereby improved the efficient of sdram controller write data, shortened the response time of AXI bus write data, improved the bus operational efficiency.
[description of drawings]
Fig. 1 is the structural representation of sdram controller in the prior art.
Fig. 2 is the principle of work block diagram of sdram controller of the present invention.
Fig. 3 is the structural representation of the address filtering module of sdram controller of the present invention.
[embodiment]
See also shown in Figure 2; A kind of sdram controller write data fast response method of the present invention based on the AXI bus; Said sdram controller comprises AXI slave unit interface 1, data buffer area 2, read write command queuing register 3, moderator 4, command processing unit 5 and SDRAM protocol controller 6, also comprises address filtering mould 7;
Said method is: sdram controller is when receiving the write data command request of each the AXI main equipment transmission that is connected with the AXI bus; Sdram controller changes into each write data order the sdram controller internal command and submits to said moderator 4 arbitrations through said address filtering module 7 through said AXI slave unit interface 1; It is medium pending that each write data order after the arbitration is put into said read write command queuing register 3; It is medium pending that the data that simultaneously each AXI main equipment will be write are put into said data buffer area 2; This moment, sdram controller need not wait for that the data that will write write the external unit 8 of sdram controller, but directly sent the response that write data is accomplished to each AXI main equipment correspondence; Will reduce the stand-by period of each AXI main equipment write data like this; But processing can cause the ruined problem of data consistency in the sdram controller like this; Lift a simple example; Suppose to have two AXI main equipments; With AXI main equipment R0 among Fig. 2 and AXI main equipment R1 is example, when AXI main equipment R0 and AXI main equipment R1 have exchanges data promptly to carry out FM, can visit the address with a slice SDRAM simultaneously; Suppose that AXI main equipment R0 writes one group of data in the data buffer area 2 of sdram controller, AXI main equipment R0 notice AXI main equipment R1 goes reading of data in the identical address after accomplishing; After obtaining notifying, passes through AXI main equipment R1 read channel read data in sdram controller of AXI bus immediately; This time might AXI main equipment R0 write data also be kept in the data buffer area 2 of sdram controller and do not write in the external unit 8 of sdram controller; What so just cause that AXI main equipment R1 reads is legacy data (promptly not being from the external unit 8 of sdram controller, to obtain), is destroyed thereby shine into the consistance of data.For the execution efficient of the write data that improves the AXI bus and avoid the data consistency in the sdram controller to be destroyed; When the design sdram controller, adding an address filtering module 7 handles; Promptly carry out read data when operation (RD0 among Fig. 2) to sdram controller simultaneously as a certain AXI main equipment; Then sdram controller needs to filter the write operation of identical address through described address filtering module 7, when avoiding sdram controller to read and write data in the said data buffer area 2 consistance of data destroyed;
The write operation that said address filtering module 7 is filtered identical address is specially: after said address filtering module 7 receives the read data order of a certain AXI main equipment transmission; Order corresponding address whether consistently to compare with each write data in the said read-write queuing register 3 address of this read data order earlier; Be then to operate by the normal consistency flow process; Not; Then with current read data order carrying out locking; After the data that all write datas orders of the address correlation of in said read-write queuing register 3, ordering with this read data all carry out writing are write the external unit 8 of sdram controller; Again said moderator 4 being delivered in this read data order arbitrates; Read data order after the arbitration is put in the said read write command queuing register 3; During the order of read data after command processing unit 5 receives arbitration, read desired data (being the RD1 Fig. 2) from the external unit 8 of sdram controller and return to the AXI main equipment (being the RD2 among Fig. 2) of said transmission read data order through said SDRAM protocol controller 6.
Wherein said normal consistency flow process is operated and is the data that will write that said command processing unit 5 receives each write data order and each write data order correspondence; The said data that respectively will write are write the external unit 8 of sdram controller through said SDRAM protocol controller 6; Simultaneously said moderator 4 being delivered in said read data order arbitrates; Read data order after the arbitration is put in the said read write command queuing register 3; During the order of read data after command processing unit 5 receives arbitration, read desired data (being the RD1 Fig. 2) from the external unit 8 of sdram controller and return to the AXI main equipment (being the RD2 among Fig. 2) of said transmission read data order through said SDRAM protocol controller.
Here what deserves to be mentioned is: as shown in Figure 3, said address filtering module 7 comprises at least one address comparator 71 and at least one control module 72 of reading; Have N address comparator 71 to read control module 72 with N among Fig. 3, said N is the natural number more than or equal to 1, and an one of which address comparator 71 one of correspondence are read control module 72; Said read write command queuing register 3 is connected with said address comparator 71; Said address comparator 71 is accepted address and each write data order corresponding address in the said read write command queuing register 3 of the read data order of an AXI main equipment respectively, judges through comparer 71 whether the address of this read data order is consistent with each write data order corresponding address in the said read-write queuing register 3 like this; It reads control module 72 is that read data order the carrying out locking of AXI main equipment is operated or directly delivered to said moderator 4 and arbitrate.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (2)
1. sdram controller write data fast response method based on the AXI bus, said sdram controller comprises AXI slave unit interface, data buffer area, read write command queuing register, moderator, command processing unit and SDRAM protocol controller; It is characterized in that: said sdram controller also comprises the address filtering module;
Said method is: sdram controller is when receiving the write data command request of each the AXI main equipment transmission that is connected with the AXI bus; Sdram controller changes into each write data order the sdram controller internal command and submits to said moderator arbitration through said address filtering module through said AXI slave unit interface; It is medium pending that each write data order after the arbitration is put into said read write command queuing register; It is medium pending that the data that simultaneously each AXI main equipment will be write are put into said data buffer area; This moment, sdram controller need not wait for that the data that will write write the external unit of sdram controller, but directly sent the response that write data is accomplished to each AXI main equipment correspondence; Carry out read data when operation to sdram controller simultaneously as a certain AXI main equipment; Then sdram controller needs to filter the write operation of identical address through described address filtering module, when avoiding sdram controller to read and write data in the said data buffer area consistance of data destroyed;
The write operation that said address filtering module is filtered identical address is specially: after said address filtering module receives the read data order of a certain AXI main equipment transmission; Order corresponding address whether consistently to compare with each write data in the said read-write queuing register address of this read data order earlier; Be then to operate by the normal consistency flow process; Not; Then with current read data order carrying out locking; After the data that all write datas orders of the address correlation of in said read-write queuing register, ordering with this read data all carry out writing are write the external unit of sdram controller; Again said moderator being delivered in this read data order arbitrates; The order of read data after the arbitration is put in the said read write command queuing register, during read data order after the command processing unit receives arbitration, reads desired data return to said transmission read data order through said SDRAM protocol controller AXI main equipment from the external unit of sdram controller.
2. the sdram controller write data fast response method based on the AXI bus according to claim 1; It is characterized in that: said normal consistency flow process is operated and is the data that will write that said command processing unit receives each write data order and each write data order correspondence; The said data that respectively will write are write the external unit of sdram controller through said SDRAM protocol controller; Simultaneously said moderator being delivered in said read data order arbitrates; Read data order after the arbitration is put in the said read write command queuing register; During the order of read data after the command processing unit receives arbitration, read desired data return to said transmission read data order through said SDRAM protocol controller AXI main equipment from the external unit of sdram controller.
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| CN110674075A (en) * | 2019-09-27 | 2020-01-10 | 山东华芯半导体有限公司 | Method and system for realizing AXI bus broadcasting mechanism |
| CN113254384A (en) * | 2021-06-23 | 2021-08-13 | 中科院微电子研究所南京智能技术研究院 | Data transmission method and system for many-core system |
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| CN117312210A (en) * | 2023-11-29 | 2023-12-29 | 沐曦集成电路(南京)有限公司 | Method for expanding performance of RISC-V processor |
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