CN102594298A

CN102594298A - Mixed SETCMOS D trigger based on negative differential resistance characteristic

Info

Publication number: CN102594298A
Application number: CN2012100480264A
Authority: CN
Inventors: 魏榕山; 陈寿昌; 陈锦锋; 何明华
Original assignee: Fuzhou University
Current assignee: Fuzhou University
Priority date: 2012-02-29
Filing date: 2012-02-29
Publication date: 2012-07-18
Anticipated expiration: 2032-02-29
Also published as: CN102594298B

Abstract

The invention relates to the integrated circuit technology field, especially to a mixed single-electron transistor (SET) CMOS D trigger based on a negative differential resistance (NDR) characteristic. Key points of the D trigger structure are as follows: a mixed circuit formed by an SET and a CMOS is utilized to generate two kinds of NDR characteristics with opposite changing directions; and moreover, the NDR characteristics are utilized to form two stable state points used for storing voltage values so as to realize functions of latch registers; and the two latch registers are in cascade connection to realize the functions of the D trigger. Compared with a traditional D trigger, the NDR characteristic-based mixed SETCMOS D edge trigger employed in the invention enables circuit power consumption to be substantially reduced and the circuit integrated level to be improved.

Description

Mixing SETCMOS d type flip flop based on negative differential resistance characteristic

Technical field

The present invention relates to technical field of integrated circuits, particularly a kind of mixing SETCMOS d type flip flop based on negative differential resistance characteristic.

Background technology

After the development entering 100nm of characteristic size along with Moore's Law of metal-oxide-semiconductor, its reliability and electrology characteristic are faced with many challenges owing to receive the influence of quantum effect.Digital circuit is along with the metal-oxide-semiconductor characteristic size dwindles gradually, and its stability and integrated level also are faced with challenge.(single-electron transistor SET) as novel nano electron device, is expected to become the strong replacer after metal-oxide-semiconductor gets into the nanometer field to single-electronic transistor.SET is made up of Coulomb island, grid capacitance and two tunnel junctions, mainly forms electric current through grid voltage control electron tunneling, has extra small size and extremely low power consumption.In addition, single-electronic transistor also possesses unique coulomb oscillations characteristic and higher characteristics such as charge sensitivity, can reduce the complexity of circuit effectively.Therefore, adopting the SET design circuit is one of effective scheme that solves the difficulty that present digital circuit faces.But higher transmission postpones because SET has, the shortcoming of low output level, only can not obtain required performance by the traditional circuit that SET constitutes, and can't be compatible mutually with the large scale integrated circuit of present maturation.The form that the present invention adopts SET/CMOS to mix has made up a digital circuit-d type flip flop based on negative differential resistance characteristic.

Summary of the invention

The purpose of this invention is to provide a kind of mixing SETCMOS d type flip flop, greatly reduce the power consumption of circuit, and improved the integrated level of circuit based on negative differential resistance characteristic.

The present invention adopts following scheme to realize: a kind of mixing SETCMOS d type flip flop based on negative differential resistance characteristic; It is characterized in that; Comprise: one first latch; It comprises a NMOS transfer tube, have the mixing SET/CMOS circuit NDR1 of NDR characteristic and be the negative differential resistance circuit SET-MOS1 on basis with SET/CMOS, described NDR1 and SET-MOS1 series connection, and the drain electrode that said NMOS manages is connected between this NDR1 and the SET-MOS1; One second latch; It comprises a PMOS transfer tube, have the mixing SET/CMOS circuit NDR2 of NDR characteristic and be the negative differential resistance circuit SET-MOS2 on basis with SET/CMOS; Described NDR2 and SET-MOS2 series connection, the drain electrode of said PMOS pipe is connected between this NDR2 and the SET-MOS2; And a buffer, described first latch is connected with said second latch through this buffer.

In an embodiment of the present invention; Said SET-MOS1 and SET-MOS2 comprise a single-electronic transistor SET and NMOS pipe; The source electrode of described NMOS pipe is connected with the drain electrode of single-electronic transistor SET; The drain electrode of said NMOS pipe is connected the drain-source voltage of this single-electronic transistor SET with the grid of said single-electronic transistor SETVDsMust satisfy |VDs|<ECΣ, wherein,CΣBe total capacitance,CΣ=Cg+ CCtrl+ Cd+ CseBe elementary charge.

In an embodiment of the present invention; Said NDR1 and NDR2 comprise a single-electronic transistor SET and PMOS pipe; The source electrode of described PMOS pipe links to each other with the source electrode of single-electronic transistor SET; The grid of single-electronic transistor SET links to each other the drain-source voltage of this single-electronic transistor SET with the drain electrode of PMOS pipeVDsMust satisfy |VDs|<ECΣ, wherein,CΣBe total capacitance,eBe elementary charge.

In an embodiment of the present invention; Said single-electronic transistor SET is in series through Coulomb island by two tunnel junctions; The bias voltage that adds is coupled on the Coulomb island by grid capacitance, and with the tunnelling current of control device, the major parameter of this single-electronic transistor SET comprises: tunnel junctions electric capacity C _dWith C _s, tunnel junctions resistance R _dWith R _s, grid capacitance C _gWith C _CtrlWherein, the thermal fluctuation that the charging of tunnel junctions can cause greater than ambient temperature, promptly E _c =e ² / 2C _Σ >>k _B T, in the formula: E _cFor the charging of tunnel junctions can; C _Σ =C _g + C _Ctrl + C _d + C _sTotal capacitance for single-electronic transistor; eBe elementary charge; k _BBe Boltzmann constant; TBe ambient temperature; The resistance of tunnel junctions must be greater than quantum resistance, promptly R _d, R _s >>R _Q =h/e ² ≈25.8 K Ω, in the formula: R _QBe quantum resistance; hBe planck constant.

In an embodiment of the present invention, the parameter of said NMOS transfer tube satisfies: channel width W _nBe 65nm, channel length L _nBe 100 nm, threshold voltage V _ThBe 0.423 V; The parameter of said PMOS transfer tube satisfies: channel width W _nBe 65nm, channel length L _nBe 100 nm, threshold voltage V _ThFor-0.365V; The parameter of said PMOS pipe satisfies: channel width W _pBe 100 nm, channel length L _pBe 65 nm, grid voltage V _PgBe 0.3 V, threshold voltage V _ThBe-0.365 V; The parameter of said NMOS pipe satisfies: channel width W _nBe 100nm, channel length L _nBe 65nm, threshold voltage V _ThBe 0.423 V, grid voltage V _nBe 0.26V; The parameter of said single-electronic transistor SET satisfies: tunnel junctions electric capacity C _s, C _dBe 0.15aF, tunnel junctions resistance R _s, R _dBe 1 M Ω, back gate voltage V _Ctrl1For-0.1V, back gate voltage V _Ctrl2Be 0.7V, back of the body gate capacitance C _CtrlBe 0.1aF, grid capacitance C _gBe 0.2aF.

Compare with traditional d type flip flop, the operating current based on the mixing SET/CMOSD trigger of negative differential resistance characteristic that the present invention adopts only has only 20 ~ 40nA, greatly reduces the power consumption of circuit; If adopt pure CMOS to realize buffer; The D edge triggered flip flop that the present invention proposes need 14 transistors; And if employing SET/CMOS mixed structure is realized buffer, then need 16 transistors, in addition because SET has minimum area; Compare with the D edge triggered flip flop that pure CMOS constitutes, circuit structure of the present invention has littler area.In the design of low-power consumption, high integration, can well be used.And compare with the trigger that SET constitutes, the present invention has bigger output voltage swing.

Description of drawings

Fig. 1 is a single-electronic transistor SET structural representation.

Fig. 2 is to be the negative differential resistance circuit SET-MOS electrical block diagram on basis with SET/CMOS.

Fig. 3 is to be the simulated properties curve chart of the negative differential resistance circuit SET-MOS circuit on basis with SET/CMOS.

Fig. 4 is the mixing SET/CMOS circuit NDR electrical block diagram with NDR characteristic.

Fig. 5 is the simulated properties curve chart with mixing SET/CMOS circuit NDR circuit of NDR characteristic.

Fig. 6 is the structural representation of latch.

Fig. 7 is the simulated properties curve chart of latch.

Fig. 8 is the transient state simulation result sketch map of latch.

Fig. 9 is the structural representation that the present invention is based on the mixing SETCMOS d type flip flop of negative differential resistance characteristic.

Figure 10 is the emulation sketch map of this d type flip flop.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is further specified.

Present embodiment provides a kind of mixing SETCMOS d type flip flop based on negative differential resistance characteristic; It is characterized in that; Comprise: one first latch; It comprises a NMOS transfer tube, have the mixing SET/CMOS circuit NDR1 of NDR characteristic and be the negative differential resistance circuit SET-MOS1 on basis with SET/CMOS, described NDR1 and SET-MOS1 series connection, and the drain electrode that said NMOS manages is connected between this NDR1 and the SET-MOS1; One second latch; It comprises a PMOS transfer tube, have the mixing SET/CMOS circuit NDR2 of NDR characteristic and be the negative differential resistance circuit SET-MOS2 on basis with SET/CMOS; Described NDR2 and SET-MOS2 series connection, the drain electrode of said PMOS pipe is connected between this NDR2 and the SET-MOS2; And a buffer, described first latch is connected with said second latch through this buffer.

Above-mentioned NDR1 and NDR2 comprise a single-electronic transistor SET and PMOS pipe; The source electrode of described PMOS pipe links to each other with the source electrode of single-electronic transistor SET; The grid of single-electronic transistor SET links to each other the drain-source voltage of this single-electronic transistor SET with the drain electrode of PMOS pipeVDsMust satisfy |VDs|<ECΣ, wherein,CΣBe total capacitance,eBe elementary charge.

Above-mentioned SET-MOS1 and SET-MOS2 comprise a single-electronic transistor SET and NMOS pipe; The source electrode of described NMOS pipe is connected with the drain electrode of single-electronic transistor SET; The drain electrode of said NMOS pipe is connected the drain-source voltage of this single-electronic transistor SET with the grid of said single-electronic transistor SETVDsMust satisfy |VDs|<ECΣ, wherein,CΣBe total capacitance,eBe elementary charge.

In order to let those skilled in the art better understand the present invention, below we are elaborated to each several part structure and operation principle respectively:

Single-electronic transistor is meant the corpuscular property that utilizes electron charge and the control of coulomb blockade oscillation effect is single or the device of a few electron transfer, and its double-gate structure is as shown in Figure 1.Single-electronic transistor is in series through Coulomb island by two tunnel junctions.The bias voltage that adds is coupled on the Coulomb island by grid capacitance, with the tunnelling current of control device. and the major parameter of single-electronic transistor has: tunnel junctions electric capacityCdWithCs, tunnel junctions resistanceRdWithRs, grid capacitanceCgWithCCtrlThrough bias voltage control electron tunneling, make single-electronic transistor have unique coulomb blockade oscillating characteristic.Promptly down fixing in the drain-source voltage, along with the increase of grid voltage, transistor drain current has cyclic variation.This characteristic must satisfy two conditions and could produce: the thermal fluctuation that the charging of (1) tunnel junctions can cause greater than ambient temperature, promptlyEc=e2/ 2CΣ>>kBT, in the formula:EcFor the charging of tunnel junctions can;CΣBe the total capacitance of single-electronic transistor,CΣ=Cg+ CCtrl+ Cd+ CseBe elementary charge;kBBe Boltzmann constant;TBe ambient temperature.(2) resistance of tunnel junctions must be much larger than quantum resistance, promptlyRd,Rs>>RQ=h/e2≈25.8 K Ω, in the formula:RQBe quantum resistance;hBe planck constant.Different with CMOS is that single-electronic transistor is at higher drain-source voltageVDsUnder can't get into saturation condition. along withVDsIncrease, coulomb blockade will disappear.Therefore, gate source voltageVGsAnd drain-source voltageVDsCan control the coulomb blockade district of single-electronic transistor simultaneously.In order to make single-electronic transistor normally carry out switch work, drain-source voltage must satisfy |VDs|<E CΣIn addition, single-electronic transistor can also pass through back gate voltageVCtrlControl its current characteristics.Different through setoveringVCtrl, translation can take place in the coulomb blockade oscillating curve of single-electronic transistor.

Japanology person Inokawa, and the colleague to propose a kind of be the negative differential resistance circuit (being called for short the SET-MOS circuit) on basis with SET/CMOS, its structure and characteristic such as Fig. 2 are shown in 3.The present invention utilizes the basic principle of SET through this circuit structure of research, in conjunction with the characteristic of CMOS pipe, has proposed another kind of mixing SET/CMOS circuit (abbreviating the NDR circuit as) with NDR characteristic, and its basic structure is as shown in Figure 4.This NDR circuit is in series by a double grid SET and a PMOS pipe.The source electrode of PMOS pipe links to each other with the source electrode of SET, and the grid of SET then links to each other with the drain electrode of PMOS pipe.In order to make single-electronic transistor produce coulomb blockage, SET drain-source voltage must satisfy |VDs|<ECΣ. for this reason, the gate bias of PMOS pipe is at fixed voltage among Fig. 2VPMake the voltage at SET drain-source two ends down,VDsRemain on a substantially invariable value |VDd-(VP-VTh)|, whereinVThBe the threshold voltage of PMOS. this value must be set enough lowly, promptly less thanE/ CΣ. at this moment, the PMOS pipe is biased in sub-threshold region.Through the PMOS pipe of connecting, the source voltage terminal of SET can not receive metal-oxide-semiconductor drain terminal voltageVDInfluence, andVDControl produce down coulomb oscillations and coulomb blockade characteristic. in addition, this circuit adopts the SET structure of double grid, through adjusting back gate voltageVCtrlThe phase place of control coulomb oscillations makes circuit obtain suitable NDR characteristic, and is as shown in Figure 5.

It is to be in series by two kinds of above-mentioned NDR hybrid circuits that the present invention proposes a kind of latch, and its structure is as shown in Figure 6.This latch utilizes two kinds of different NDR characteristics of change direction to constitute bistable state, and is as shown in Figure 7.Steady state point " 0 " is positioned at the intersection point place of trough of positive resistance region and the NDR circuit characteristic of SET-MOS circuit characteristic, and steady state point " 1 " is positioned at the intersection point place of negative differential resistance region of trough and the NDR circuit characteristic of SET-MOS circuit characteristic.Back gate voltage through adjustment SET V _Ctrl, and the bias voltage of two metal-oxide-semiconductors V _n, V _p, can change the position of two steady state points, so that obtain bigger output voltage swing.Through suitably adjustment, the position of steady state point " 0 " is greatly about 0.05V (logical zero), and the position of steady state point " 1 " is greatly about 0.55V (logical one).When the NMOS transfer tube is opened (word line, word line are high level), input point (bit line, bit line) with latch a little V _DConducting is latched a little V _DChange along with the variation of bit-line voltage.And arrive at the trailing edge of word line, when promptly transfer tube is closed, if V _DThe value that is not equal to two steady state points, then two kinds of situations of change can appear in circuit: 1. V _DBe positioned near the steady state point 1 ( V _D>0.3V) time, it will be pulled to about 0.55V; 2. V _DBe positioned near the steady state point 2 ( V _D<0.3V) time, it will be pulled to about 0.05V.And latching names a person for a particular job keeps the magnitude of voltage of one of them steady state point constant always, arrives up to next word line high level.In the level latch, adopt low-power consumption PTM model and the behavior of SET sub circuit model analog circuit of 65-nm CMOS.Its transient state simulation result is seen Fig. 8, and simulation parameter is seen table 1.

The tradition edge triggered flip flop generally is to adopt two S-R level series of latches to form.According to same thought, the d type flip flop that the present invention proposes is to be formed by above-mentioned latch cascade, and its structure is as shown in Figure 9.This d type flip flop is that trigger the lower edge, and trigger the upper edge as long as two metal-oxide-semiconductors exchanges of clock control are just passable.When clock is high level, first transfer tube conducting, the value of first latch changes along with the variation of D value.When the trailing edge of clock arrived, the magnitude of voltage of D will be by first latches, and first transfer tube is closed, and second transfer tube opened.Thereby the magnitude of voltage of first latches is obtained by second latch, and at this moment, no matter how the D value changes, and the Q value can not change yet, and arrives until next clock trailing edge.Therefore, the lower edge is triggered function and is realized, like Figure 10.Second latch is except the PMOS transfer tube of W=65nm, L=100nm, and all the other transistorized parameters are identical with table 1 in the circuit.

Figure 2012100480264100002DEST_PATH_IMAGE002

Table 1

What deserves to be mentioned is, in the circuit structure that this joint proposes,, can not obtain the edge and trigger function if directly together with two series of latches.Because; When clock was low level, the steady-state current of leakage current and the first latch stores point that flows through second transfer tube was suitable, thereby has destroyed original point of safes; The information dropout that this will cause being stored in first latch makes second latch obtain wrong value.The main cause that causes this problem is that the current driving ability of first latch and input impedance are too low.For this reason, the present invention has added a buffer between master and slave trigger, as shown in Figure 9.Because buffer has input impedance significantly, and first latch and PMOS transfer tube are kept apart, and has solved the problem of information dropout.If adopt pure CMOS to realize buffer, the D edge triggered flip flop that the present invention proposes needs 14 transistors, and if adopt SET/CMOS mixed structure realization buffer; Then need 16 transistors, but in any case, compare with the D edge triggered flip flop that pure CMOS constitutes; The structure that the present invention proposes all will significantly reduce required number of transistors; Improved the integrated level of chip, and its operating current also extremely low (nA level), chip power-consumption reduced effectively.

The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. the mixing SETCMOS d type flip flop based on negative differential resistance characteristic is characterized in that, comprising:

One first latch; It comprises a NMOS transfer tube, have the mixing SET/CMOS circuit NDR1 of NDR characteristic and be the negative differential resistance circuit SET-MOS1 on basis with SET/CMOS; Described NDR1 and SET-MOS1 series connection, the drain electrode of said NMOS pipe is connected between this NDR1 and the SET-MOS1;

One second latch; It comprises a PMOS transfer tube, have the mixing SET/CMOS circuit NDR2 of NDR characteristic and be the negative differential resistance circuit SET-MOS2 on basis with SET/CMOS; Described NDR2 and SET-MOS2 series connection, the drain electrode of said PMOS pipe is connected between this NDR2 and the SET-MOS2; And

One buffer, described first latch is connected with said second latch through this buffer.

2. the mixing SETCMOS d type flip flop based on negative differential resistance characteristic according to claim 1; It is characterized in that: said SET-MOS1 and SET-MOS2 comprise a single-electronic transistor SET and NMOS pipe; The source electrode of described NMOS pipe is connected with the drain electrode of single-electronic transistor SET; The drain electrode of said NMOS pipe is connected the drain-source voltage of this single-electronic transistor SET with the grid of said single-electronic transistor SETVDsMust satisfy |VDs|<ECΣ, wherein,CΣBe total capacitance,eBe elementary charge.

3. the mixing SETCMOS d type flip flop based on negative differential resistance characteristic according to claim 1; It is characterized in that: said NDR1 and NDR2 comprise a single-electronic transistor SET and PMOS pipe; The source electrode of described PMOS pipe links to each other with the source electrode of single-electronic transistor SET; The grid of single-electronic transistor SET links to each other the drain-source voltage of this single-electronic transistor SET with the drain electrode of PMOS pipeVDsMust satisfy |VDs|<ECΣ, wherein,CΣBe total capacitance,eBe elementary charge.

4. according to claim 2 or 3 described mixing SETCMOS d type flip flops based on negative differential resistance characteristic; It is characterized in that: said single-electronic transistor SET is in series through Coulomb island by two tunnel junctions; The bias voltage that adds is coupled on the Coulomb island by grid capacitance; With the tunnelling current of control device, the major parameter of this single-electronic transistor SET comprises: tunnel junctions electric capacity C _dWith C _s, tunnel junctions resistance R _dWith R _s, grid capacitance C _gWith C _CtrlWherein, the thermal fluctuation that the charging of tunnel junctions can cause greater than ambient temperature, promptly E _c =e ² / 2C _Σ >>k _B T, in the formula: E _cFor the charging of tunnel junctions can; C _Σ =C _g + C _Ctrl + C _d + C _sTotal capacitance for single-electronic transistor; eBe elementary charge; k _BBe Boltzmann constant; TBe ambient temperature; The resistance of tunnel junctions must be greater than quantum resistance, promptly R _d, R _s >>R _Q =h/e ² ≈25.8 K Ω, in the formula: R _QBe quantum resistance; hBe planck constant.

5. the mixing SETCMOS d type flip flop based on negative differential resistance characteristic according to claim 4 is characterized in that: the parameter of said NMOS transfer tube satisfies: channel width W _nBe 65nm, channel length L _nBe 100 nm, threshold voltage V _ThBe 0.423 V; The parameter of said PMOS transfer tube satisfies: channel width W _nBe 65nm, channel length L _nBe 100 nm, threshold voltage V _ThFor-0.365V; The parameter of said PMOS pipe satisfies: channel width W _pBe 100 nm, channel length L _pBe 65 nm, grid voltage V _PgBe 0.3 V, threshold voltage V _ThBe-0.365 V; The parameter of said NMOS pipe satisfies: channel width W _nBe 100nm, channel length L _nBe 65nm, threshold voltage V _ThBe 0.423 V, grid voltage V _nBe 0.26V; The parameter of said single-electronic transistor SET satisfies: tunnel junctions electric capacity C _s, C _dBe 0.15aF, tunnel junctions resistance R _s, R _dBe 1 M Ω, back gate voltage V _Ctrl1For-0.1V, back gate voltage V _Ctrl2Be 0.7V, back of the body gate capacitance C _CtrlBe 0.1aF, grid capacitance C _gBe 0.2aF.