CN102591998B - Grid capacitance model of high-voltage device - Google Patents

Grid capacitance model of high-voltage device Download PDF

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CN102591998B
CN102591998B CN 201110004409 CN201110004409A CN102591998B CN 102591998 B CN102591998 B CN 102591998B CN 201110004409 CN201110004409 CN 201110004409 CN 201110004409 A CN201110004409 A CN 201110004409A CN 102591998 B CN102591998 B CN 102591998B
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gate
capacitance
overlap
drain
source
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CN 201110004409
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CN102591998A (en )
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武洁
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上海华虹宏力半导体制造有限公司
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Abstract

本发明公开了一种高压器件的栅极电容模型,包括BSIM模型栅极电容、栅极场板与源极端之间形成的栅源交叠电容、或栅极场板与漏极端之间形成的栅漏交叠电容。 The present invention discloses a high-pressure gate capacitance model of the device, including the gate-source overlap capacitance formed between a gate capacitance BSIM model, the gate terminal and the source field plate or a gate field plate is formed between the drain terminal and gate-drain overlap capacitance. 本发明在现有BSIM模型栅极电容的基础上,加入了栅极场板引入的交叠电容,从而能够有效提高高压器件模型精度、提高高压集成电路仿真精度、节约电路设计周期。 The present invention is based on the existing model BSIM gate capacitance, adding the field plate gate overlap capacitance introduced, it is possible to improve the accuracy of the model high voltage devices, high voltage integrated circuit to improve the simulation accuracy, saving circuit design cycle.

Description

高压器件的栅极电容模型 The gate capacitance of the high voltage device model

技术领域 FIELD

[0001] 本发明涉及半导体集成电路制造领域,特别是涉及一种高压器件的栅极电容模型。 [0001] The present invention relates to a semiconductor integrated circuit manufacturing, and more particularly relates to a gate capacitance of the high voltage device model.

背景技术 Background technique

[0002] 用于高压集成电路设计的高压器件如高压M0S、高压LDMOS中,一般都会有场板技术的应用,以提高器件击穿电压。 [0002] The high voltage integrated circuit design for a high voltage device M0S high-pressure, high-voltage LDMOS, the application will generally have a field plate technology, to improve the device breakdown voltage. 场板技术为:在高压器件中,栅极除了覆盖在沟道区外,还延伸到沟道区外部,所述沟道区外部包括源极侧的源极有源区或源极场氧区、或漏极侧的漏极有源区或漏极场氧区,覆盖于所述源极有源区或源极场氧区、或漏极有源区或漏极场氧区上的栅极为栅极场板。 Technical field plate as follows: In a high pressure device, in addition to a gate region overlying the channel, but also extends outside the channel region, the channel region comprises outer active electrode region or source region of the field oxide source side of the source , a drain or drain-side active region or the drain field oxide region, the source covering the active region or the field oxide regions the source, drain or gate electrode on the active region or the drain region of the field oxide gate field plate. 根据各种高压器件的实际情况的不同,在源极侧或漏极侧的所述栅极场板分为只跨越在有源区、或同时跨越在有源区和场氧区的两种情况。 Depending on the actual situation of the various high-voltage device, in the gate field plate or a source side across the drain side only into the active region, or in both cases simultaneously across the active region and a field oxide region . 为了便于理解,现举两个实际例子对所述栅极场板进行说明。 For ease of understanding, now give two practical examples of the gate field plate will be described.

[0003] 如图1所示,为现有N型高压MOS的结构示意图,高压MOS器件形成于P型衬底上,在所述P型衬底上形成有场氧,如浅槽隔离场氧,并隔离出各有源区。 [0003] FIG. 1, is a schematic structural diagram of a conventional voltage MOS N-type, high-voltage MOS devices formed on the P-type substrate, field oxide is formed on the P-type substrate, such as shallow trench isolation field oxide regions and a source region each isolate. P阱形成沟道区。 A channel region formed in P-well. 源区由形成在所述P阱一侧N阱加上形成于该N阱中的N+掺杂区组成,并在N+掺杂区上形成金属接触引出源极。 A source region formed in said N-well from the P-well formed in the N side plus N + doped region in the well composition, and is formed on the N + doped region in contact with the lead source metal. 漏区由形成在所述P阱另一侧N阱加上形成于该N阱中的N+掺杂区组成,并在N+掺杂区上形成金属接触引出漏极。 A drain region formed in said N-well P-well on the other side plus the N-well formed in the N + doped region in the composition, and forming a drain electrode on the lead-out metal contact N + doped regions. 体区由一P阱加上形成于该P阱中的P+掺杂区组成,并在P+掺杂区上形成金属接触引出体电极。 Body region composed of a P-well coupled to the P-well is formed a P + doped region composition, and forming a metal contact electrode lead-out member on the P + doped region. 栅极由形成于沟道区上的栅极氧化层和栅极多晶硅组成,所述栅极氧化层的厚度为d。 A gate electrode formed on the channel region of the gate oxide and the gate polysilicon layer, the thickness of the gate oxide layer is d. 所述栅极还延伸到所述沟道区两侧并分别覆盖在所述源区和所述漏区的N阱上。 The gate also extends to both sides of the channel region and N-well are overlaid on the source region and the drain region. 覆盖在所述源区和所述漏区的N阱上的所述栅极即为栅极场板。 A gate overlying the source region and the N-well region of the drain is the gate field plate. 所述源区的N阱为源极有源区,所述漏区的N阱为漏极有源区。 N-well region of the source is a source of the active region, the drain region of the N-well active region is a drain. 如图1可知,所述栅极场板在漏极有源区上的横向尺寸为a。 1 can be seen, the transverse dimension of the gate field plate on the drain of the active region is a. 所述高压MOS器件的所述栅极场板并未覆盖在场氧区上。 The gate of the field plate does not cover the high-voltage MOS device on the field oxide regions.

[0004] 如图2所示,为现有N型高压LDMOS的结构示意图,高压LDMOS器件形成于P型衬底上,在所述P型衬底中形成有N型埋层、深N阱,在所述P型衬底上形成有场氧,如浅槽隔离场氧,并隔离出各有源区。 [0004] As illustrated, the schematic structural view of the conventional high-voltage LDMOS N-type, high-voltage LDMOS device 2 is formed on the P-type substrate, an N-type buried layer formed in said P-type substrate, a deep N-well, formed with field oxide, such as shallow trench isolation field oxide on the P-type substrate, the source region and each isolate. 在所述深N阱中形成有P阱,所述P阱形成沟道区。 Formed in the deep N-well in a P-well, the P-well channel region is formed. 源区由形成在所述P阱中的N+掺杂区组成,并在N+掺杂区上形成金属接触引出源极。 A source region of an N-well formed in the P + doped region in the composition, and forming a metal contact on the lead source N + doped regions. 漏区由部分所述深N阱、形成于所述深N阱中的N阱加上形成于该N阱中的N+掺杂区组成,并在N+掺杂区上形成金属接触引出漏极,在该N阱和所述P阱间间隔有一场氧、该场氧和所述P阱间间隔有部分所述深N阱。 N drain region by the deep N-well portion, formed in the deep N-well formed in N-well coupled to the N + doped region in the well composition, and the N + doped region forming a drain metal contact leads, between the N well and the P-well is interrupted by a oxygen, the intervals between deep N-well portion of the field oxide region and the P-well. 体区由形成于该P阱中的P+掺杂区组成,并在P+掺杂区上形成金属接触引出体电极。 A P body region formed in the P + doped region in the well composition, and forming a metal contact electrode lead-out member on the P + doped region. 栅极由形成于沟道区上的栅极氧化层和栅极多晶硅组成,所述栅极氧化层的厚度为d。 A gate electrode formed on the channel region of the gate oxide and the gate polysilicon layer, the thickness of the gate oxide layer is d. 所述栅极还延伸到所述沟道区的靠漏极侧的所述漏区的所述深N阱和所述场氧上。 Said gate further extends into the channel region of the drain region on the drain side of the deep N-well and said field oxide. 覆盖在所述漏区的所述深N阱和所述场氧上的所述栅极即为栅极场板。 Covering said drain region in said deep N-well and the gate on the gate oxide of the field is the field plate. 所述漏区的所述深N阱为漏极有源区,所述漏区的所述场氧为漏极场氧区。 Said drain region of said deep N-well active region is a drain, the drain region of the field oxide is a field oxide drain regions. 如图2可知,所述栅极场板在漏极有源区上的横向尺寸为a、在漏极场氧区上的横向尺寸为b、所述漏极场氧区的厚度为c ;所述高压LDMOS器件的所述栅极场板并未覆盖在源极有源区和场氧区上。 Seen in FIG. 2, the lateral dimension of the gate field plate on the drain of the active region is a, a transverse dimension on the drain region of the field oxide is b, the thickness of the drain of the field oxide regions C; the the gate of said field plate does not cover the high-voltage LDMOS device on the source of the active region and the field oxide regions. [0005] 在如图1和图2所示的现有N型高压MOS和现有N型高压LDMOS基础上做适当的变动的高压器件中也存在栅极场板技术。 [0005] Also in the presence of a gate field plate techniques as shown in FIG. 1 and conventional N-type voltage MOS device shown in FIG. 2 and the conventional high-voltage N-type high-voltage LDMOS done on the basis of the appropriate changes. 和如图1和图2所示的现有N型高压MOS和现有N型高压LDMOS相对应的P型高压MOS和高压LDM0S、和适当变动产生的各种P型高压器件中也存在栅极场板技术。 P-type high-voltage device and a variety of P-type high-pressure and high-voltage MOS LDM0S, mutatis mutandis, and FIGS. 1 and conventional MOS and N-type high-voltage N-type conventional high-voltage LDMOS shown in FIG. 2 corresponds to the gate there is produced field plate technology. 上述各种栅极场板技术能有效提高高压器件击穿电压,但是同时引入了较大的交叠(Overlap)电容。 The above gate field plate technique can improve the breakdown voltage of high voltage devices, but also introduces large overlap (the Overlap) capacitance. 高压电路设计中对具有开关特性高压器件的开关速度是有严格要求的,因此如何精确模拟场板技术引入的交叠电容是高压器件模型的关键技术之一。 High voltage circuit design for high-voltage switching device having a switching speed is strictly required characteristics, and therefore how to accurately overlap capacitance analog technology into the field plate is one of the key technologies in high-voltage device model. 当前业界没有标准的高压器件模型,更没有栅极场板交叠电容的精确模型方法。 There is no current industry standard high-pressure device models, and no field plate overlaps the gate capacitance of an accurate model method.

发明内容 SUMMARY

[0006] 本发明所要解决的技术问题是提供一种高压器件的栅极电容模型,能提高高压器件的模型精度、提高高压集成电路仿真精度、节约电路设计周期。 [0006] The present invention solves the technical problem is to provide a high gate capacitance device model, the model can improve the accuracy of high voltage devices, high voltage integrated circuit to improve the simulation accuracy, saving circuit design cycle.

[0007] 为解决上述技术问题,本发明提供一种高压器件的栅极电容模型,栅极电容模型包括BSIM模型栅极电容,所述栅极电容模型还包括栅极场板与源极端之间形成的栅源交叠电容、或所述栅极场板与漏极端之间形成的栅漏交叠电容。 [0007] To solve the above problems, the present invention provides a high voltage device model gate capacitance, the gate capacitance model BSIM model comprises a gate capacitance, the gate capacitance model further comprises a field plate between the gate and source terminals the gate-source overlap capacitance formed between a gate or a field plate and the drain terminal is formed gate-drain overlap capacitance.

[0008] 更进一步的改进是,所述栅源交叠电容包括所述栅极场板与源极有源区之间的交叠电容一、所述栅极场板与源极场氧区之间的交叠电容二,所述交叠电容一和所述交叠电容二之间并联连接。 [0008] A further improvement is that the gate-source overlap capacitance comprises an overlap capacitance, the gate field plate between the gate and the source field plate electrode and the source electrode of the active region of the field oxide regions the overlap capacitance between the two, connected in parallel between the overlap capacitance of a capacitor and the two overlap.

[0009] 更进一步的改进是,所述栅漏交叠电容包括所述栅极场板与漏极有源区之间的交叠电容三、所述栅极场板与漏极场氧区之间的交叠电容四,所述交叠电容三和所述交叠电容四之间并联连接。 [0009] A further improvement is that the gate-drain overlap capacitance comprises three overlap capacitance between the gate and drain of active field plate region, a gate field plate and the drain of the field oxide regions four overlap capacitance between the third and the overlap capacitance capacitor connected in parallel between the four overlapping.

[0010] 更进一步的改进是,所述栅源交叠电容、所述交叠电容一、所述交叠电容二的计算公式如下: [0010] A further improvement is that the gate-source overlap capacitance, a capacitance of the overlap, the overlapping of the two capacitors is calculated as follows:

[001 1 ] [0011]

Figure CN102591998BD00041

[0014]其中: [0014] wherein:

[0015] Cgs overlap是所述栅源交叠电容Kgs lroly m aetive是每单位沟道宽度下的所述交叠电容一;cgsJly mf1-是每单位沟道宽度下的所述交叠电容二;胃是高压器件的沟道宽度; [0015] Cgs overlap is the gate-source overlap capacitance Kgs lroly m aetive is the channel width of the overlap capacitance per a unit; cgsJly mf1- is the channel width of the overlap capacitance per unit II; the stomach is the channel width of the high voltage device;

Lpoly_on—source_active Lpoly_on-source_active

是所述栅极场板与所述源极有源区上的长度;L Is the length of the source electrode on the active area of ​​the gate field plate; L

poly_on_source_field poly_on_source_field

是所述栅极 It is the gate

场板与所述源极场氧区上的长度;CS0A和CSOF是两个模型修正因子;vgsal、vgsa2、vgsfl和vgsf2是电压系数;Toxaetive是栅氧厚度;Toxfield是场氧厚度;Stl是真空介电常数;ε Si()2是二氧化硅介电常数;vgs为栅源电压。 Field plate length of the source of the field oxide regions; CS0A CSOF and two correction factor models; vgsal, vgsa2, vgsfl and vgsf2 voltage coefficient; Toxaetive is gate oxide thickness; Toxfield is the field oxide thickness; Stl vacuum dielectric constant; ε Si () 2 is the dielectric constant of silicon dioxide; Vgs is the gate-source voltage.

[0016] 更进一步的改进是,所述栅漏交叠电容、所述交叠电容三、所述交叠电容四的计算公式如下: [0016] A further improvement is that the gate-drain overlap capacitance, said three overlap capacitance, the capacitance of the overlap calculation formula IV as follows:

[001 7] [0017]

Figure CN102591998BD00042
Figure CN102591998BD00051

[0020]其中: [0020] wherein:

[0021] Cgd overlap是所述栅漏交叠电容Kgd pt5ly m artive是每单位沟道宽度下的所述交叠电容三;cgd p()ly m f1-是每单位沟道宽度下的所述交叠电容四;胃是高压器件的沟道宽度; [0021] Cgd overlap said gate-drain overlap capacitance Kgd pt5ly m artive is the channel width per unit of three overlap capacitance; cgd p () ly m f1- is the channel width per unit of four overlap capacitance; stomach is the channel width of the high voltage device;

是所述栅极场板与所述漏极有源区上的长度山 Is the gate field plate on the drain region of the active length of the mountain

是所述栅极场 Said gate field

板与所述漏场氧区上的长度KDOA和⑶OF是两个模型修正因子;vgdal、vgda2、vgdfl和vgdf2是电压系数;Toxac:tive;是栅氧厚度;Toxfie;ld是场氧厚度;ε ^是真空介电常数;ε Si02是二氧化硅介电常数;vgd为栅漏电压。 Said drain plate and ⑶OF KDOA length on the field oxide regions are two correction factor models; vgdal, vgda2, vgdfl and vgdf2 voltage coefficient; Toxac: tive; is the gate oxide thickness; Toxfie; ld is the field oxide thickness; [epsilon] ^ is the permittivity of vacuum; ε Si02 dielectric constant of silicon dioxide; a gate-drain voltage VGD.

[0022] 本发明在现有BSIM模型栅极电容的基础上,加入了栅极场板引入的交叠电容,从而能够有效提闻闻压器件的1旲型精度、提闻闻压集成电路仿真精度、节约电路设计周期。 [0022] The present invention is based on the existing model BSIM gate capacitance, adding the field plate gate overlap capacitance introduced, it is possible to effectively improve the accuracy of the smell 1 Dae-type pressure device, integrated circuit simulation mentioned pressure smell accuracy, saving circuit design cycle.

附图说明 BRIEF DESCRIPTION

[0023] 下面结合附图和具体实施方式对本发明作进一步详细的说明: [0023] The present invention will be further described in detail in conjunction with accompanying drawings and specific embodiments:

[0024] 图1是现有N型闻压MOS的结构不意图; [0024] FIG. 1 is a conventional N-type MOS structure smell not intended pressure;

[0025] 图2是为现有N型高压LDMOS的结构示意图; [0025] FIG. 2 is a schematic view of a conventional N-type high-voltage LDMOS;

[0026] 图3是本发明实施例模型等效电路图。 [0026] FIG. 3 is an equivalent circuit diagram of the embodiment of the present invention model.

具体实施方式 detailed description

[0027] 如图3所示,是本发明实施例模型等效电路图。 [0027] FIG. 3 is a circuit diagram of an equivalent model of embodiment of the present invention. 本发明实施例的高压器件的栅极电容模型包括BSIM模型中的栅极电容,所述栅极电容模型还包括栅极场板与源极端之间形成的栅源交叠电容、或所述栅极场板与漏极端之间形成的栅漏交叠电容。 The gate capacitance of the high voltage device model according to an embodiment of the present invention includes a gate capacitance of BSIM model, the model also includes the gate capacitance of the gate-source overlap capacitance formed between the gate and source terminals of the field plate, or the gate the gate electrode is formed between the field plate and the drain terminal of the drain overlap capacitance.

[0028] 所述栅源交叠电容包括所述栅极场板与源极有源区之间的交叠电容一、所述栅极场板与源极场氧区之间的交叠电容二,所述交叠电容一和所述交叠电容二之间并联连接。 Overlap capacitance between the overlap capacitance between a [0028] The gate-source overlap capacitance comprises the gate field plate and the source of the active region, the gate and the source field plate two field oxide regions connected in parallel between the overlap capacitance of a capacitor and the two overlap. 所述栅源交叠电容、所述交叠电容一、所述交叠电容二的计算公式如下: The gate-source overlap capacitance, a capacitance of the overlap, the overlapping of the two capacitors is calculated as follows:

Figure CN102591998BD00052

[0032]其中: [0032] wherein:

[0033] Cgs overlap是所述栅源交叠电容;Cgs poly on active是每单位沟道宽度下的所述交叠电容一;Cgs P()ly ()n f1-是每单位沟道宽度下的所述交叠电容二;胃是高压器件的沟道宽度;Lpoly_on_Source_active是所述栅极场板与所述源极有源区上的长度;Lpoly on source field是所述栅极场板与所述源极场氧区上的长度;CS0A和CSOF是两个模型修正因子;vgsal、vgsa2、vgsfl和vgsf2是电压系数Joxaetive是栅氧厚度,能用BSIM模型参数Tox代替Joxfield是场氧厚度;ε ^是真空介电常数;ε Si02是二氧化硅介电常数;vgs为栅源电压。 [0033] Cgs overlap is the gate-source overlap capacitance; Cgs poly on active is the channel width per unit of an overlap capacitance; Cgs P () ly () n f1- the channel width per unit the two overlap capacitance; stomach is the channel width of the high voltage device; Lpoly_on_Source_active is the length of the active area of ​​the gate electrode and the source field plate; Lpoly on source field is the field plate and the gate the length of the source of said field oxide region; CS0A CSOF and two correction factor models; vgsal, vgsa2, vgsfl vgsf2 voltage and gate oxide thickness is Joxaetive coefficient, can be used instead of BSIM model parameters Joxfield Tox is the thickness of the field oxide; [epsilon] ^ is the permittivity of vacuum; ε Si02 dielectric constant of silicon dioxide; Vgs is the gate-source voltage.

[0034] 所述栅漏交叠电容包括所述栅极场板与漏极有源区之间的交叠电容三、所述栅极场板与漏极场氧区之间的交叠电容四,所述交叠电容三和所述交叠电容四之间并联连接。 [0034] The gate-drain overlap capacitance comprises the three overlap capacitance between the gate and drain of active field plate region, the overlap capacitance between the gate field plate and the drain field oxide region four connected in parallel between said three overlap capacitance and the overlap capacitance IV. 所述栅漏交叠电容、所述交叠电容三、所述交叠电容四的计算公式如下:[0035] The gate-drain overlap capacitance, said three overlap capacitance, the capacitance of the overlap calculation formula IV as follows: [0035]

Figure CN102591998BD00061

[0038]其中: [0038] wherein:

[0039] Cgd overlap是所述栅漏交叠电容;Cgd poly on active是每单位沟道宽度下的所述交叠电容三;Cgd p()ly m f1-是每单位沟道宽度下的所述交叠电容四;胃是高压器件的沟道宽度; [0039] Cgd overlap said gate-drain overlap capacitance; Cgd poly on active is the channel width per unit of three overlap capacitance; Cgd p () ly m f1- is that the channel width per unit four said overlap capacitance; stomach is the channel width of the high voltage device;

Lpoly— _on—drain—active Lpoly- _on-drain-active

是所述栅极场板与所述漏极有源区上的长度山 Is the gate field plate on the drain region of the active length of the mountain

poly_on—drain—field poly_on-drain-field

是所述栅极场 Said gate field

板与所述漏场氧区上的长度KDOA和⑶OF是两个模型修正因子;vgdal、vgda2、vgdfl和vgdf2是电压系数Joxaetive是栅氧厚度,能用BSIM模型参数Tox代替Joxfield是场氧厚度;ε ^是真空介电常数;ε Si02是二氧化硅介电常数;vgd为栅漏电压。 Said drain plate and ⑶OF KDOA length on the field oxide regions are two correction factor models; vgdal, vgda2, vgdfl vgdf2 voltage and gate oxide thickness is Joxaetive coefficient, can be used instead of BSIM model parameters Joxfield Tox is the thickness of the field oxide; ε ^ is the permittivity of vacuum; ε Si02 dielectric constant of silicon dioxide; a gate-drain voltage VGD.

[0040] 因为现有技术中存在着多种不同的高压器件,如各种N型或P型的高压M0S、或高压LDM0S。 [0040] Since there are a variety of different devices of the prior art high-pressure, high-pressure M0S various P-type or N-type, or high LDM0S. 对于各种不同的高压器件都可以应用本发明实施例的栅极电容模型。 For a variety of high-voltage device according to the present invention can be applied to an embodiment of the gate capacitance model. 因为根据各种高压器件的实际情况的不同,在源极侧或漏极侧的所述栅极场板分为只跨越在有源区、或同时跨越在有源区和场氧区的两种情况。 Depending on the actual situation because various high-voltage device, in the gate field plate or a source side across the drain side only into the active region, or active region simultaneously across the field oxide regions and two Happening. 故应用本发明实施例的栅极电容模型时,对于未被所述栅极场板跨越的区域,其相应的长度为0,对应该区域的交叠电容也为O。 Therefore, the application of the gate capacitance model embodiment of the present invention, for the area not covered by the gate field plate across its length corresponding to 0, the capacitance of the overlap region should also O. 为了方便理解,现分别以如图1和图2所示的高压器件进行说明。 To facilitate understanding, FIG. 1, respectively and is now a high pressure device shown in FIG. 2 will be described.

[0041] 对于如图1所示的N型高压MOS器件,根据上述公式可知,所述高压MOS器件的 [0041] For the N-type high-voltage MOS device shown in Figure 1, seen from the above equation, the high-voltage MOS device

Lpoly—on—source—field 矛口^jPoly on drain dield Lpoly-on-source-field lance mouth ^ jPoly on drain dield

的大小都为0,故所述高压MOS器件的交叠电容二和交叠 Size is 0, so that the high-voltage MOS device and two overlapping overlap capacitance

电容四都为O。 Capacitance four are O.

[0042] 对于如图2所示的N型高压LDMOS器件,根据上述公式可知,所述高压LDMOS器件 [0042] For the N-type high-voltage LDMOS device shown in Figure 2, seen from the above equation, the high voltage LDMOS device

的LptjlHstjurc^field和Lptjly ms(Mra ac;tiTC的大小都为0,故所述高压LDMOS器件的交叠电容一和交叠电容二都为O。所述高压LDMOS器件的Lpoly_on—drain—active的大小为a、L poly_on—drain—field The LptjlHstjurc ^ field and Lptjly ms (Mra ac; tiTC size is 0, so that the high voltage LDMOS device an overlap capacitance and the overlap capacitance O. are two high voltage LDMOS device of Lpoly_on-drain-active the size of a, L poly_on-drain-field

的大 Great

小为b、T0Xfield的大小为C ;将上述尺寸带入上述公式可得所述高压LDMOS器件的交叠电容三和交叠电容四。 Is a small b, T0Xfield size are C; the above dimensions into the above formula available to the overlap capacitance and the overlap capacitance four three high voltage LDMOS device.

[0043] 以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。 [0043] by the above specific embodiments of the present invention is described in detail, it is not intended to limit the present invention. 在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。 Without departing from the principles of the present invention, those skilled in the art can make various changes and modifications, which should also be regarded as the protection scope of the present invention.

Claims (1)

  1. 1.一种高压器件的栅极电容仿真模型,栅极电容模型包括BSIM模型栅极电容,其特征在于:所述栅极电容模型还包括栅极场板与源极端之间形成的栅源交叠电容和/或所述栅极场板与漏极端之间形成的栅漏交叠电容; 所述栅源交叠电容包括所述栅极场板与源极有源区之间的交叠电容一、所述栅极场板与源极场氧区之间的交叠电容二,所述交叠电容一和所述交叠电容二之间并联连接; 所述栅漏交叠电容包括所述栅极场板与漏极有源区之间的交叠电容三、所述栅极场板与漏极场氧区之间的交叠电容四,所述交叠电容三和所述交叠电容四之间并联连接; 所述栅源交叠电容、所述交叠电容一、所述交叠电容二的计算公式如下: A simulation model of a gate capacitance of the high voltage device, the gate capacitance model comprises a model BSIM gate capacitance, wherein: said model further comprises a gate capacitance formed between the gate and source cross the gate and source terminals of the field plate the gate capacitance is formed between the stack and / or the gate terminal of the field plate and the drain-drain overlap capacitance; the gate-source overlap capacitance comprises the gate overlap capacitance between the field plate and the source of the active region one, two overlap capacitance between the gate and the source field plate field oxide region, the overlap and a capacitor connected in parallel between the two overlap capacitance; the gate-drain overlap capacitance comprises the four overlap capacitance between the gate overlap capacitance between the three active field plate and the drain region, the gate field plate and the drain field oxide region, the overlap capacitance and the overlap capacitance three connected in parallel between four; the gate-source overlap capacitance, a capacitance of the overlap, the overlapping of the two capacitors is calculated as follows:
    Figure CN102591998BC00021
    其中: Cgs overlap是所述栅源交叠电容;Cgs P()ly m ac;tive是每单位沟道宽度下的所述交叠电容一;Cgs P()ly ()n fi咖是每单位沟道宽度下的所述交叠电容二;胃是高压器件的沟道宽度;Lp()lyon_source_active是所述栅极场板在所述源极有源区上的长度山p()ly—m—sfield是所述栅极场板在所述源极场氧区上的长度;CS0A和CSOF是两个模型修正因子;vgsal、vgsa2、vgsfl和vgsf2是电压系数;Toxaetive是栅氧厚度;Toxfield是场氧厚度;ε。 Wherein: Cgs overlap is the gate-source overlap capacitance; Cgs P () ly m ac; tive is the channel width per unit of an overlap capacitance; Cgs P () ly () n fi coffee per unit overlapping the channel width of the two capacitors; stomach is the channel width of the high voltage device; Lp () lyon_source_active is the gate length of the field plate on the pole p mountain active area of ​​the source () ly-m -sfield gate length of the field plate is on the source of the field oxide regions; CS0A CSOF and two correction factor models; vgsal, vgsa2, vgsfl and vgsf2 voltage coefficient; Toxaetive is gate oxide thickness; Toxfield is field oxide thickness; ε. 是真空介电常数;ε Si02是二氧化硅介电常数;vgs为栅源电压; 所述栅漏交叠电容、所述交叠电容三、所述交叠电容四的计算公式如下: Is the permittivity of vacuum; ε Si02 dielectric constant of silicon dioxide; Vgs is the gate-source voltage; a gate-drain overlap capacitance, said three overlap capacitance, the capacitance of the overlap calculation formula IV as follows:
    Figure CN102591998BC00022
    其中: Cgd overlap是所述栅漏交叠电容;cgd—P()ly—m—artiTC是每单位沟道宽度下的所述交叠电容三;cgd,ly—。 Wherein: Cgd overlap said gate-drain overlap capacitance; cgd-P () ly-m-artiTC is the channel width per unit of three overlap capacitance; cgd, ly-. „—field是每单位沟道宽度下的所述交叠电容四;胃是高压器件的沟道宽度;Lp()ly „drain_active是所述栅极场板在所述漏极有源区上的长度;Lp()ly—m—dMin—field是所述栅极场板在所述漏极场氧区上的长度;CD0A和CDOF是两个模型修正因子;vgdal、vgda2、vgdfl和vgdf2是电压系数;Toxartive是栅氧厚度;Toxfield是场氧厚度;ε ^是真空介电常数;ε _2是二氧化娃介电常数;vgd为栅漏电压。 "-field is the channel width of the overlap capacitance per unit four; stomach is the channel width of the high voltage device; Lp () ly" drain_active is the gate field plate on the drain region of the active length; Lp () ly-m-dMin-field is a length of the gate field plate on the drain field oxide region; CD0A and CDOF are two correction factor models; vgdal, vgda2, vgdfl voltage and vgdf2 coefficient; Toxartive is gate oxide thickness; Toxfield is the field oxide thickness; ε ^ is the permittivity of vacuum; ε _2 baby dioxide is a dielectric constant; is the gate-drain voltage VGD.
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