CN102569326A - Image sensor and production method thereof - Google Patents

Image sensor and production method thereof Download PDF

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Publication number
CN102569326A
CN102569326A CN201210058889XA CN201210058889A CN102569326A CN 102569326 A CN102569326 A CN 102569326A CN 201210058889X A CN201210058889X A CN 201210058889XA CN 201210058889 A CN201210058889 A CN 201210058889A CN 102569326 A CN102569326 A CN 102569326A
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groove
region
substrate
image
imageing sensor
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霍介光
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Galaxycore Shanghai Ltd Corp
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Galaxycore Shanghai Ltd Corp
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Abstract

The invention discloses an image sensor and a production method of the image sensor. The image sensor includes one or more pixel units and a peripheral circuit region, each pixel unit comprises a photosensitive region and a pixel circuit region, wherein the surface of the photosensitive region is higher than that of the pixel circuit region and the peripheral circuit region. Unlike the prior art, in the image sensor, the photosensitive region projects outwards from the photosensitive surface of the image sensor, thus the photosensitive optical path of the photosensitive region (namely the photodiode) is shortened, the influence of the metal interconnection structure on the photosensitive surface on the light collection is reduced, and further the sensitivity of the image sensor is effectively improved.

Description

Imageing sensor and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of imageing sensor and preparation method thereof.
Background technology
Along with developing rapidly of semiconductor technology, cmos image sensor is widely used in the various electronic equipments, uses as the image capture device that the digital imagery function is provided.
For the typical C mos image sensor, comprise photo-sensitive cell (being photodiode) and control element as the one of which.Wherein, photo-sensitive cell is used to collect luminous energy and converts charge signal into, and control element then is used to control the signal processing of the charge signal that is generated.These control elements need come to be electrically connected mutually through metal interconnect structure, and are drawn out to outside the imageing sensor, to realize the signal output of imageing sensor.
Different according to metal interconnect structure and photo-sensitive cell relative position, cmos image sensor can be divided into front illuminated formula imageing sensor and back side illuminaton (back-illuminated type) imageing sensor.Wherein, the metal interconnect structure of back side illumination image sensor (comprise in passivation layer and the passivation layer metal interconnected) and the photosurface of photo-sensitive cell are positioned at the both sides of image sensor chip.When sensitization, light is by the back side of back side illumination image sensor, but not the front at metal interconnect structure place shines on the photo-sensitive cell.This back side illumination image sensor needs the attenuate silicon chip when making, thereby the product yield is lower.The metal interconnect structure of front illuminated formula imageing sensor and the photosurface of photo-sensitive cell are positioned at the same side of image sensor chip.When sensitization, light sees through metal interconnect structure and shines on the photo-sensitive cell.Metal interconnect structure can partly absorb light, and this can influence the collecting efficiency of light, thereby reduces the sensitivity of imageing sensor.
Summary of the invention
Therefore, a kind of imageing sensor with higher sensitivity need be provided.
In order to address the above problem; According to an aspect of the present invention; A kind of imageing sensor is provided; Said imageing sensor comprises one or more pixel cells and peripheral circuit region, and each pixel cell comprises photosensitive region and image element circuit zone, and the surface of wherein said photosensitive region is higher than the surface of said image element circuit zone and said peripheral circuit region.
Be different from prior art; In the imageing sensor aspect above-mentioned; Its photosensitive region by the photosurface of imageing sensor to outer process; This has shortened the light path of photosensitive region (being photodiode) sensitization, thereby has reduced the influence that the metal interconnect structure on the photosurface is gathered light, and then the sensitivity that has improved imageing sensor effectively.
In one embodiment, high at least 1000 dusts in surface of the surface ratio of said photosensitive region said image element circuit zone and said peripheral circuit region.
In one embodiment, said photosensitive region is platform shape convexity.The protruding photosensitive region of platform shape is easy to form, and cost of manufacture is lower.
In one embodiment, the side of the photosensitive region of said shape convexity is spent less than 90 with respect to the slope of its bottom surface.The photosensitive region of this shape can avoid electric conducting material to remain in the side of photosensitive region, and makes and can not be short-circuited between the part of devices in photodiode and the pixel control circuit.
In one embodiment, said imageing sensor comprises that also in passivation layer and the said passivation layer one or more layers is metal interconnected, and wherein, the surface of said photosensitive region is higher than said one or more layers metal interconnected bottom of the bottom in metal interconnected.This makes the photosensitive region surface can be reduced to below 1 micron to the distance between the passivation layer, thus the sensitivity of further having shortened light path and having improved imageing sensor.
In one embodiment, said peripheral circuit region and said image element circuit zone is surperficial concordant.This can reduce the process complexity of making this imageing sensor, thereby reduces cost of manufacture.
According to an aspect of the present invention, a kind of manufacture method of imageing sensor is provided also, has comprised the steps: that a. provides substrate, said substrate comprises photosensitive region, image element circuit zone and peripheral circuit region; C. the said substrate of partial etching forms second groove and forms the 3rd groove at said peripheral circuit region in said image element circuit zone, so that the surface of said photosensitive region is higher than the surface of said image element circuit zone and said peripheral circuit region; E. form photodiode at said photosensitive region, form the pixel control circuit in said image element circuit zone, and form peripheral control circuit at said peripheral circuit region.
Be different from prior art, the manufacture method of the imageing sensor through adopting above-mentioned aspect can form the front illuminated formula imageing sensor with short sensitization light path.Because reduced the influence that the metal interconnect structure on the photosurface is gathered light, formed imageing sensor has higher sensitivity.
In one embodiment, before said step c, also comprise: b. forms first groove in said image element circuit zone with said peripheral circuit region, and the bottom of said first groove is lower than the bottom of said second groove and said the 3rd groove; And after said step c, also comprise: d. in said first groove filled dielectric material to form dielectric isolation region.
In one embodiment, said step b comprises: on said substrate, form hard mask layer; Graphical said hard mask layer; The said substrate of partial etching is to form first groove in said substrate.
In one embodiment, said step c comprises: in said first groove, fill organic photoresist; The said substrate of etching and said organic photoresist forming second groove in said image element circuit zone, and form the 3rd groove at said peripheral circuit region, and wherein said second groove and said the 3rd groove are shallower than said first groove; Remove said organic photoresist.
In one embodiment, said steps d comprises: filled dielectric material in said first groove, second groove and said the 3rd groove; Remove the dielectric material in said second groove and said the 3rd groove.
In one embodiment, after said step c, also comprise: g. partial etching substrate, in said second groove and said the 3rd groove, to form first groove; H. in said first groove filled dielectric material to form dielectric isolation region.
In one embodiment, said step g comprises: on said substrate, form hard mask layer; Graphical said hard mask layer exposes the subregion in said second groove and said the 3rd groove; With said hard mask layer is mask, and the said substrate of etching is to form first groove in said second groove and said the 3rd groove.
In one embodiment, said step h comprises: filled dielectric material in said first groove, second groove and said the 3rd groove; Remove the dielectric material in said second groove and said the 3rd groove.
In one embodiment, after said step e, comprise also that: f. forms on said substrate that one or more layers is metal interconnected.
In one embodiment; Said step f comprises: it is metal interconnected to adopt dual-damascene technics to form said one or more layers metal interconnected bottom, and makes said photosensitive region surface be higher than said one or more layers metal interconnected bottom of the bottom in metal interconnected.
Above characteristic of the present invention and other characteristics are partly set forth embodiment hereinafter clearly.
Description of drawings
Through with reference to the detailed description of being done below the advantages, can more easily understand characteristic of the present invention, purpose and advantage to non-limiting example.Wherein, same or analogous Reference numeral is represented same or analogous device.
Fig. 1 shows imageing sensor 100 according to an embodiment of the invention;
Fig. 2 shows imageing sensor 200 according to another embodiment of the present invention;
Fig. 3 shows the manufacture method 300 according to the imageing sensor of further embodiment of this invention;
Fig. 4 shows the manufacture method 400 according to the imageing sensor of further embodiment of this invention;
Fig. 5 a to Fig. 5 f shows the generalized section of the imageing sensor manufacture method 400 of Fig. 4;
Fig. 6 shows the manufacture method 600 according to the imageing sensor of further embodiment of this invention;
Fig. 7 a to Fig. 7 f shows the generalized section of the imageing sensor manufacture method 600 of Fig. 6.
Embodiment
Go through enforcement and the use of embodiment below.Yet, should be appreciated that the specific embodiment discussed only exemplarily explanation implement and use ad hoc fashion of the present invention, and unrestricted scope of the present invention.
Fig. 1 shows imageing sensor 100 according to an embodiment of the invention.
As shown in Figure 1; This imageing sensor 100 comprises one or more pixel cells 101 and peripheral circuit region 103; Each pixel cell 101 comprises photosensitive region 101a and image element circuit zone 101b; Wherein, the surface of photosensitive region 101a is higher than the surface of image element circuit zone 101b and peripheral circuit region 103.
Wherein, Here the surface of the surface of alleged photosensitive region 101a, image element circuit zone 101b and the surface of peripheral circuit region 103 be meant form this imageing sensor 100 substrate (for example; Semiconductor crystal wafer) in corresponding to the substrate surface in zone, but not the surface of the metal interconnect structure on the substrate.
Particularly; The photosensitive region 101a of each pixel cell 101 comprises the photodiode that is used to carry out opto-electronic conversion; Image element circuit zone 101b then comprises the pixel control circuit; This pixel control circuit is used to control the transfer of the photogenerated charge that photodiode forms, and the circuit structure that it can adopt 3 transistors (3T) or 4 transistors (4T) usually promptly comprises 3 to 4 field-effect transistors.In addition, the peripheral circuit region 103 of imageing sensor 100 comprises peripheral control circuit, and its sensitization, signal that is used to control the array of pixel cell reads and/or other picture signals are handled.Peripheral control circuit can comprise a plurality of field-effect transistors.Can find out, all include a plurality of transistors usually in image element circuit zone 101b and the peripheral circuit region 103, in certain embodiments, these transistors can be through dielectric isolation region 113 electricity isolation each other.
Need to prove, the transistorized concrete structure in the control circuit of the not shown imageing sensor 100 of Fig. 1, and only schematically show the part dielectric isolation region 113 in the control circuit, this dielectric isolation region 113 is used for the isolation control circuit different transistors.In addition; One skilled in the art will recognize that the difference according to embodiment, peripheral control circuit and pixel control circuit also can comprise the transistor of other types; The transistor that perhaps alternatively is fit to by other types constitutes, and for example is made up of bipolar transistor.
Can find out that by Fig. 1 this imageing sensor 100 is front illuminated formula imageing sensors, have metal interconnect structure 105 on its photosurface (being the side that photodiode exposes).This metal interconnect structure 105 comprise in passivation layer 107 and the passivation layer 107 one or more layers metal interconnected 109.Wherein, Metal interconnected 109 of different layers passes through contact hole 111 mutual electric connections, and contact hole 111 also leads to metal interconnected 109 with the transistorized electrode (the for example grid shown in source electrode, drain electrode and Fig. 1 115) in image element circuit zone 101b and the peripheral circuit region 103.Need to prove that alleged passivation layer 107 comprises metal interconnected 109 interlayer dielectric layer between multiple layer metal interconnection 109, that be used to isolate different layers here.
For imageing sensor shown in Figure 1 100, the bottom metal interconnected 109 in its multiple layer metal interconnection 109 is to adopt mosaic technology to make with the contact hole 111 under it.In this imageing sensor 100, be used for connecting the passivation layer 107 that the bottom metal interconnected 109 and the contact hole 111 of the bottom of control circuit are positioned at the bottom, and the bottom metal interconnected 109 is positioned on the passivation layer 107 of the bottom.Therefore, the bottom surface of the bottom metal interconnected 109 is higher than the surface of photosensitive region 101a, and perhaps the bottom surface of this bottom metal interconnected 109 is concordant basically with the surface of this photosensitive region 101a.
For imageing sensor 100; Its photosensitive region 101a by photosurface to outer process; This has shortened the light path of photosensitive region 101a sensitization, thereby has reduced the influence that 105 pairs of light of the metal interconnect structure on the photosurface are gathered, and then the sensitivity that has improved imageing sensor 100 effectively.In addition, because photosensitive region 101a is a stereochemical structure, this makes that the degree of depth that ion injects is controlled easily, thereby can improve the consistency of photodiode in the different pixels unit 101 when adopting the ion injection mode to make photodiode therein.In addition, the cross interference between the photosensitive region 101a of the stereochemical structure adjacent pixel unit 101 that also helps reducing to cause owing to scattering of light.
In certain embodiments, high at least 1000 dusts in surface of the surface ratio image element circuit of photosensitive region 101a zone 101a and peripheral circuit region 103.In a preferred embodiment, surperficial high 5000 dust to 8000 dusts of the surface ratio image element circuit of photosensitive region 101a zone 101a and peripheral circuit region 103.
In the embodiment shown in fig. 1, it is protruding that the photosensitive region 101a of each pixel cell 101 is the platform shape, and for example the shape of this photosensitive region 101a is round platform, terrace with edge, and perhaps the side has the convexity of radian.For the protruding photosensitive region 101a of platform shape; Light both can enter in the photosensitive region 101a through platform shape convex upper surface; But also can enter in the photosensitive region 101a through the protruding side of platform shape, this has effectively increased photosensitive area, has improved the sensitivity of imageing sensor 100.In addition, in practical application, the protruding photosensitive region 101a of platform shape also is easy to make and forms.In certain embodiments, peripheral circuit region 103 and image element circuit zone 101b's is surperficial concordant.For example, can come attenuate peripheral circuit region 103 and image element circuit zone 101b simultaneously through the mode of an etching.This can reduce the complex manufacturing technology degree of making this imageing sensor 100, thereby reduces cost of manufacture.
In one embodiment, less than 90 degree, for example being 45 degree spends to 75 with respect to the slope of its bottom surface (promptly with surperficial concordant face of the image element circuit zone 101a) in the side of the photosensitive region 101a that the platform shape is protruding.Like this, the upper surface width everywhere of the photosensitive region 101a of platform shape convexity is less than the width of its relevant position, bottom surface basically.Because semiconductor fabrication process adopts Surface-micromachining process usually; Therefore; Protruding photosensitive region 101a can avoid the electric conducting material in the manufacturing process to remain in the side of the protruding photosensitive region 101a of platform shape, thereby can not be short-circuited because electric conducting material is residual between the part of devices in photodiode and the pixel control circuit.
Fig. 2 shows imageing sensor 200 according to another embodiment of the present invention.
As shown in Figure 2, be different from the imageing sensor 100 shown in Fig. 1, be higher than the bottom of one or more layers bottom metal interconnected 209 in metal interconnected 209 on the surface of the photosensitive region 201b of this imageing sensor 200.This makes metal interconnect structure 205 reduce the thickness of one deck metal interconnected 209 at least, thus the sensitivity of further having shortened light path and having improved imageing sensor 200.In practical application, the metal interconnect structure 205 of this structure makes photosensitive region 201b surface can be reduced to below 1 micron to the distance between metal interconnect structure 205 surfaces.In certain embodiments, metal interconnected 209 of the bottom with and under contact hole 211 can adopt dual-damascene technics to form.
Need to prove, in some instances, can also adopt dual-damascene technics to form than upper strata metal interconnected 209 in the multiple layer metal interconnection 209, to reduce the height of the contact hole 211 between metal interconnected 209.Like this, the integral thickness of metal interconnect structure 205 can further reduce, thereby further reduces the influence of 205 pairs of imageing sensor 200 sensitization of metal interconnect structure.
Fig. 3 shows the manufacture method 300 according to the imageing sensor of further embodiment of this invention.
As shown in Figure 3, this manufacture method 300 comprises:
Execution in step S302 provides substrate, and this substrate comprises photosensitive region, image element circuit zone and peripheral circuit region;
Execution in step S304, the partial etching substrate forms second groove and forms the 3rd groove at peripheral circuit region in the image element circuit zone, so that the surface of photosensitive region is higher than the surface of image element circuit zone and peripheral circuit region;
Execution in step S306 forms photodiode at photosensitive region, forms the pixel control circuit in the image element circuit zone, and forms peripheral control circuit at peripheral circuit region.
Can find out from above-mentioned steps; In this manufacture method 300; It makes photosensitive region protruding relatively by substrate surface through the image element circuit zone of etched substrate and the mode of peripheral circuit region; And then make corresponding electronic device in its zones of different based on this substrate, comprise control circuit element and photo-sensitive cell.
Be appreciated that in peripheral circuit region and the image element circuit zone to include a plurality of transistors usually, thereby also need form dielectric isolation region therein to isolate different transistors.In certain embodiments, dielectric isolation region can adopt groove isolation construction, and this groove isolation construction needs etched substrate.Therefore, alternatively, can be before the step S304 in advance etched substrate in order to making dielectric isolation region; Perhaps alternatively, etched substrate again after step S304.
Fig. 4 shows the manufacture method 400 according to the imageing sensor of further embodiment of this invention.In this manufacture method 400, substrate quilt etching is in advance prepared against the making dielectric isolation region.
As shown in Figure 4, this manufacture method 400 comprises:
Execution in step S402 provides substrate, and this substrate comprises photosensitive region, image element circuit zone and peripheral circuit region;
Execution in step S404 forms first groove in said image element circuit zone with said peripheral circuit region, and the bottom of said first groove is lower than the bottom of said second groove and said the 3rd groove;
Execution in step S406, the partial etching substrate forms second groove and forms the 3rd groove at peripheral circuit region in the image element circuit zone, so that the surface of photosensitive region is higher than the surface of image element circuit zone and peripheral circuit region;
Execution in step S408, filled dielectric material is to form dielectric isolation region in said first groove;
Execution in step S410 forms photodiode at photosensitive region, forms the pixel control circuit in the image element circuit zone, and forms peripheral control circuit at peripheral circuit region.
Fig. 5 a to Fig. 5 f shows the generalized section of the imageing sensor manufacture method 400 of Fig. 4.Connect down,, this imageing sensor manufacture method 400 is further explained with reference to figure 4 and Fig. 5 a to Fig. 5 f.
Shown in Fig. 5 a, substrate 501 is provided, this substrate 501 comprises photosensitive region 503, image element circuit zone 505 and peripheral circuit region 507.
Then, on substrate 501, form hard mask layer 509, this hard mask layer 509 can be silicon nitride, silicon oxynitride, carborundum or its combination.In certain embodiments, before forming hard mask layer 509, can also on substrate 501, form laying, for example silicon oxide layer.Stress mismatch between the laying between hard mask layer 509 and the substrate 501 can reduce.
Afterwards, graphical hard mask layer 509, the surface of exposing the part substrate 501 of image element circuit zone 505 and peripheral circuit region 507.With this hard mask layer 509 is mask etching substrate 501, thereby in substrate 501, forms first groove 511.Wherein, form the dielectric isolation region of image element circuit zone 505 and peripheral circuit region 507 after the Lower Half of this first groove 511 is used for.In certain embodiments, the degree of depth of this first groove 511 is 8000 to 10000 dusts.
Then, on substrate 501, apply the organic photoresist 513 of one deck, for example anti-reflective coating layer material (Anti-Reflect Coating).This organic photoresist 513 covers the surface of hard mask layer 509 and fills first groove 511.This organic photoresist 513 has higher etching selection ratio with hard mask layer 509, and for example its etching selection ratio was above 1: 5.Again then, the position of reverse this organic photoresist 513 to hard mask layer 509 of etching only keeps the organic photoresist 513 of part in first groove 511.
Shown in Fig. 5 b, graphical again hard mask layer 509 removes the hard mask layer 509 on image element circuit zone 505 and the peripheral circuit region 507.Afterwards, continue etched substrate 501, form second groove 517 in image element circuit zone 505 and form the 3rd groove 519, so that the surface of photosensitive region 503 is higher than the surface of image element circuit zone 505 and peripheral circuit region 507 at peripheral circuit region 507.Wherein, the degree of depth of second groove 517 and the 3rd groove 519 is shallower than first groove 511, so that second groove 517 and leave the opening corresponding to first groove 511 with the 3rd groove 519 bottoms.This opening can be used for filled dielectric material, to form dielectric isolation region.
In certain embodiments, can adopt dry etch process to come etching second groove 517 and the 3rd groove 519.Because dry etch process is an anisotropic etching, therefore, the side of formed second groove 517 and the 3rd groove 519 is slope, slope shape.The ramped shaped side of second groove 517 and the 3rd groove 519 makes the protruding shape in photosensitive region 503 places be platform shape.Less than 90 degree, for example being 45 degree spends to 75 with respect to the slope of its bottom surface the surperficial concordant face of image element circuit zone 505 (promptly with) in the side of the photosensitive region 503 that the platform shape is protruding.
Shown in Fig. 5 c, filled dielectric material in first groove 511, second groove 517 and the 3rd groove 519.For example, adopt chemical vapor deposition method cvd silicon oxide on substrate 501.Preferably, can adopt high density plasma CVD technology to deposit this dielectric material with preferable step coverage property.Generally speaking, understood on the substrate 501 and deposit a part of dielectric material and can not fully fill to avoid each groove.Therefore, afterwards, can remove the dielectric material of crossing deposition on the substrate 501 through CMP process, and stop on the hard mask layer 509.
Then, remove the dielectric material in second groove 517 and the 3rd groove 519, and only keep the dielectric material in first groove 511.In certain embodiments, can remove this dielectric material through reverse etching technics, until reverse etching stopping on second groove 517 and the 3rd groove 519 substrate of bottom portion 501.Like this, residual dielectric material has promptly constituted dielectric isolation region 521 in first groove 511.
Shown in Fig. 5 d, after forming dielectric isolation region 521, remove hard mask layer with and under laying.Like this, substrate 501 promptly is shaped in the protruding shape of photosensitive region.
Shown in Fig. 5 e, substrate 501 is carried out ion doping, in image element circuit zone 505 and/or peripheral circuit region 507, to form trap 523.Then, form gate oxide 525 on substrate 501 surfaces.Afterwards, substrate 501 is carried out ion inject, in photosensitive region 503, to form photodiode.Because photosensitive region 503 is protruding stereochemical structures, therefore when adopting the ion injection mode in photosensitive region 503, to make photodiode, the degree of depth that ion injects is controlled easily, thereby can improve the consistency of photodiode performance in the different pixels unit.
Again then, on the substrate 501 of image element circuit zone 505 and peripheral circuit region 507, form grid 527, and in the substrate 501 of image element circuit zone 505 and peripheral circuit region 507, make each transistorized source region and drain region (not shown).It will be understood by those skilled in the art that forming photodiode can adopt with the basic similar processing mode of existing processing procedure with transistorized technology and carry out, and repeats no more at this.
Shown in Fig. 5 f, at photosensitive region 503 formation photodiodes and after image element circuit zone 505 and peripheral circuit region 507 formation transistors.Continuation forms metal interconnect structure 529 on substrate 501.This metal interconnect structure 529 comprises that one or more layers is metal interconnected 531, wherein, this multiple layer metal interconnection 531 by passivation layer 533 each other electricity isolate.In the present embodiment, adopt dual-damascene technics to form the bottom metal interconnected 531 of metal interconnect structure 529, and the bottom of this bottom metal interconnected 531 is lower than the surface of photosensitive region 503.Be appreciated that in certain other embodiments metal interconnect structure 529 can also adopt mosaic technology to make; Perhaps make metal interconnect structure 529 through etching technics, i.e. plated metal interconnection material (for example aluminium) on the passivation layer 533 of the bottom, and this interconnect materials of partial etching is to form the bottom metal interconnected 531.
Through above-mentioned processing procedure, can form front illuminated formula imageing sensor with short sensitization light path.Because reduced the influence that the metal interconnect structure on the photosurface is gathered light, this imageing sensor has higher sensitivity.
Fig. 6 shows the manufacture method 600 according to the imageing sensor of further embodiment of this invention.In this manufacture method 600, dielectric isolation region is photosensitive region latter made by relative lifting.
As shown in Figure 6, the manufacture method 600 of this imageing sensor comprises:
Execution in step S602 provides substrate, and this substrate comprises photosensitive region, image element circuit zone and peripheral circuit region;
Execution in step S604, the partial etching substrate forms second groove and forms the 3rd groove at peripheral circuit region in the image element circuit zone, so that the surface of photosensitive region is higher than the surface of image element circuit zone and peripheral circuit region;
Execution in step S606, the partial etching substrate is to form first groove in said second groove and said the 3rd groove;
Execution in step S608, filled dielectric material is to form dielectric isolation region in said first groove;
Execution in step S610 forms photodiode at photosensitive region, forms the pixel control circuit in the image element circuit zone, and forms peripheral control circuit at peripheral circuit region.
Fig. 7 a to Fig. 7 f shows the generalized section of the imageing sensor manufacture method 600 of Fig. 6.Next, with reference to figure 6 and Fig. 7 a to Fig. 7 f, this imageing sensor manufacture method 600 is further explained.
Shown in Fig. 7 a, substrate 701 is provided, this substrate 701 comprises photosensitive region 703, image element circuit zone 705 and peripheral circuit region 707.
Then, on substrate 701, form hard mask layer 709, this hard mask layer 709 can be silicon nitride, silicon oxynitride, carborundum or its combination.In certain embodiments, before forming hard mask layer 709, can also on substrate 701, form laying 711, for example silicon oxide layer.Stress mismatch between the laying 711 between hard mask layer 709 and the substrate 701 can reduce.
Afterwards, graphical hard mask layer 709, the surface of exposing the substrate 701 of image element circuit zone 705 and peripheral circuit region 707.With this hard mask layer 709 is mask etching substrate 701, thereby forms second groove 713 that is arranged in substrate 701 in substrate image element circuit zone 705, and forms the 3rd groove 715 that is arranged in substrate 701 at peripheral circuit region 707.Formed second groove 713 and the 3rd groove 715 make that substrate 701 surfaces of photosensitive region 703 are protruding relatively.In some instances, the degree of depth of this second groove 713 and the 3rd groove 715 is at least 1000 dusts, for example is 3000 to 5000 dusts.Be appreciated that; In some instances; Hard mask layer 709 in image element circuit zone 705 and the peripheral circuit region 707 with and under laying 711 can be removed respectively; Forming second groove 713 and the 3rd groove 715 respectively, thereby make that the surperficial irrelevancy of second groove 713 and the 3rd groove 715 is neat.
In certain embodiments, can adopt dry etch process to come etching second groove 713 and the 3rd groove 715.Because dry etch process is an anisotropic etching, therefore, the side of formed second groove 713 and the 3rd groove 715 is slope, slope shape.The ramped shaped side of second groove 713 and the 3rd groove 715 makes the protruding shape in photosensitive region 703 places be platform shape.Less than 90 degree, for example being 45 degree spends to 75 with respect to the slope of its bottom surface the surperficial concordant face of image element circuit zone 705 (promptly with) in the side of the photosensitive region 703 that the platform shape is protruding.
Shown in Fig. 7 b, remove remaining hard mask layer 709 and laying 711.Again form one deck hard mask layer 717 on substrate 701 surfaces.In some instances, this hard mask layer also can form one deck laying 717 times.
Shown in Fig. 7 c, graphical hard mask layer 717, the surface of exposing the part substrate 701 in image element circuit zone 705 and the peripheral circuit region 707.Then, be mask etching substrate 701 with this hard mask layer 717, thereby in image element circuit zone 705 and peripheral circuit region 707, form first groove 719.
Shown in Fig. 7 d, filled dielectric material in first groove 719.For example, adopt chemical vapor deposition method cvd silicon oxide on substrate 701.Preferably, can adopt high density plasma CVD technology to deposit this dielectric material with preferable step coverage property.Generally speaking, understood on the substrate 701 and deposit a part of dielectric material and can not fully fill to avoid each groove.Therefore, afterwards, can remove the dielectric material of crossing deposition on the substrate 701 through CMP process, and stop on the hard mask layer.
Then, remove the dielectric material in second groove 713 and the 3rd groove 715, and only keep the dielectric material in first groove 719.In certain embodiments, can remove this dielectric material through reverse etching technics, until reverse etching stopping on second groove 713 and the 3rd groove 715 substrate of bottom portion 701.Like this, residual dielectric material has promptly constituted dielectric isolation region 721 in first groove 711.After forming dielectric isolation region 721, remove hard mask layer.
Shown in Fig. 7 e, substrate 701 is carried out ion doping, in image element circuit zone 705 and/or peripheral circuit region 707, to form trap 723.Then, form gate oxide 725 on substrate 701 surfaces.Afterwards, substrate 701 is carried out ion inject, in photosensitive region 703, to form photodiode.Because photosensitive region 703 is protruding stereochemical structures, therefore when adopting the ion injection mode in photosensitive region 703, to make photodiode, the degree of depth that ion injects is controlled easily, thereby can improve the consistency of photodiode in the different pixels unit.
Again then, on the substrate 701 of image element circuit zone 705 and peripheral circuit region 707, form grid 727, and in the substrate 701 of image element circuit zone 705 and peripheral circuit region 707, make each transistorized source region and drain region (not shown).It will be understood by those skilled in the art that forming photodiode can adopt with the basic similar processing mode of existing processing procedure with transistorized technology and carry out, and repeats no more at this.
Shown in Fig. 7 f, at photosensitive region 703 formation photodiodes and after image element circuit zone 705 and peripheral circuit region 707 formation transistors.Continuation forms metal interconnect structure 729 on substrate 701.This metal interconnect structure 729 comprises that one or more layers is metal interconnected 731, wherein, this multiple layer metal interconnection 731 by passivation layer 733 each other electricity isolate.In the present embodiment, adopt dual-damascene technics to form the bottom metal interconnected 731 of metal interconnect structure 729, and the bottom of this bottom metal interconnected 731 is lower than the surface of photosensitive region 703.Be appreciated that in certain other embodiments metal interconnect structure 729 can also adopt mosaic technology to make.
Through above-mentioned processing procedure, can form front illuminated formula imageing sensor with short sensitization light path.Because reduced the influence that the metal interconnect structure on the photosurface is gathered light, this imageing sensor has higher sensitivity.
Although in accompanying drawing and aforesaid description sets forth in detail with the present invention has been described, should think that this is illustrated and describes is illustrative and exemplary, rather than restrictive; The invention is not restricted to above-mentioned execution mode.
The those skilled in the art in those present technique fields can be through research specification, disclosed content and accompanying drawing and appending claims, and understanding and enforcement are to other changes of the execution mode of disclosure.In claim, word " comprises " element and the step of not getting rid of other, and wording " one " is not removed plural number.In the practical application of invention, the function of a plurality of technical characterictics of being quoted during a part possibility enforcement of rights requires.Any Reference numeral in the claim should not be construed as the restriction to scope.

Claims (16)

1. imageing sensor; It is characterized in that; Said imageing sensor comprises one or more pixel cells and peripheral circuit region; Each pixel cell comprises photosensitive region and image element circuit zone, and the surface of wherein said photosensitive region is higher than the surface of said image element circuit zone and said peripheral circuit region.
2. imageing sensor according to claim 1 is characterized in that, high at least 1000 dusts in surface of the surface ratio of said photosensitive region said image element circuit zone and said peripheral circuit region.
3. imageing sensor according to claim 1 is characterized in that, it is protruding that said photosensitive region is the platform shape.
4. imageing sensor according to claim 3 is characterized in that, the side of the photosensitive region of said shape convexity is spent less than 90 with respect to the slope of its bottom surface.
5. imageing sensor according to claim 1; It is characterized in that; Said imageing sensor comprises that also in passivation layer and the said passivation layer one or more layers is metal interconnected; Wherein, the surface of said photosensitive region is higher than said one or more layers metal interconnected bottom of the bottom in metal interconnected.
6. imageing sensor according to claim 1 is characterized in that, said peripheral circuit region is surperficial concordant with said image element circuit zone.
7. the manufacture method of an imageing sensor is characterized in that, comprises the steps:
A., substrate is provided, and said substrate comprises photosensitive region, image element circuit zone and peripheral circuit region;
C. the said substrate of partial etching forms second groove and forms the 3rd groove at said peripheral circuit region in said image element circuit zone, so that the surface of said photosensitive region is higher than the surface of said image element circuit zone and said peripheral circuit region;
E. form photodiode at said photosensitive region, form the pixel control circuit in said image element circuit zone, and form peripheral control circuit at said peripheral circuit region.
8. manufacture method according to claim 7 is characterized in that,
Before said step c, also comprise: b. forms first groove in said image element circuit zone with peripheral circuit region, and the bottom of said first groove is lower than the bottom of said second groove and said the 3rd groove; And
After said step c, also comprise: d. in said first groove filled dielectric material to form dielectric isolation region.
9. manufacture method according to claim 8 is characterized in that, said step b comprises:
On said substrate, form hard mask layer;
Graphical said hard mask layer;
The said substrate of partial etching is to form first groove in said substrate.
10. manufacture method according to claim 8 is characterized in that, said step c comprises:
In said first groove, fill organic photoresist;
The said substrate of etching and said organic photoresist forming second groove in said image element circuit zone, and form the 3rd groove at said peripheral circuit region, and wherein said second groove and said the 3rd groove are shallower than said first groove;
Remove said organic photoresist.
11. manufacture method according to claim 8 is characterized in that, said steps d comprises:
Filled dielectric material in said first groove, second groove and said the 3rd groove;
Remove the dielectric material in said second groove and said the 3rd groove.
12. manufacture method according to claim 7 is characterized in that, after said step c, also comprises:
G. partial etching substrate is to form first groove in said second groove and said the 3rd groove;
H. in said first groove filled dielectric material to form dielectric isolation region.
13. manufacture method according to claim 12 is characterized in that, said step g comprises:
On said substrate, form hard mask layer;
Graphical said hard mask layer exposes the subregion in said second groove and said the 3rd groove;
With said hard mask layer is mask, and the said substrate of etching is to form first groove in said second groove and said the 3rd groove.
14. manufacture method according to claim 12 is characterized in that, said step h comprises:
Filled dielectric material in said first groove, said second groove and said the 3rd groove;
Remove the dielectric material in said second groove and said the 3rd groove.
15. manufacture method according to claim 7 is characterized in that, after said step e, also comprises:
F. it is metal interconnected on said substrate, to form one or more layers.
16. manufacture method according to claim 15 is characterized in that, said step f comprises:
It is metal interconnected to adopt mosaic technology to form said one or more layers metal interconnected bottom, and makes said photosensitive region surface be higher than said one or more layers metal interconnected bottom of the bottom in metal interconnected.
CN201210058889XA 2012-03-07 2012-03-07 Image sensor and production method thereof Pending CN102569326A (en)

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