CN102545878B - Semiconductor chip - Google Patents

Semiconductor chip Download PDF

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Publication number
CN102545878B
CN102545878B CN201110407965.9A CN201110407965A CN102545878B CN 102545878 B CN102545878 B CN 102545878B CN 201110407965 A CN201110407965 A CN 201110407965A CN 102545878 B CN102545878 B CN 102545878B
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CN
China
Prior art keywords
coupled
power
grid
output
bias voltage
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CN201110407965.9A
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Chinese (zh)
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CN102545878A (en
Inventor
曾子建
曹太和
刘剑
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瑞昱半导体股份有限公司
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Priority to CN2008100922259A priority Critical patent/CN101562447B/en
Publication of CN102545878A publication Critical patent/CN102545878A/en
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Abstract

The invention provides a current leakage preventing circuit and a semiconductor chip. The semiconductor chip is suitable for being coupled to a power supply end and an output end and comprises a core circuit, a resistance unit and a one-way current unit. The core circuit is coupled to the output end. The resistance unit is coupled to the output end. The one-way current unit is coupled between the resistance unit and the power supply end. When the one-way current unit is used for supplying power in the power supply end, current is allowed to be conducted from the output end to the power supply end; when the one-way current unit is not used for supplying power in the power supply end, current is substantially prevented from being conducted from the output end to the power supply end, wherein the core circuit, the resistance unit and the one-way current unit are arranged in the same semiconductor substrate.

Description

Semiconductor chip

The application is the divisional application of following patent application:

Application number: 200810092225.9

The applying date: on April 17th, 2008

Denomination of invention: creepage preventing circuit and semiconductor chip

Technical field

The invention relates to a kind of creepage preventing circuit and a kind of semiconductor chip, refer to a kind of creepage preventing circuit and a kind of semiconductor chip that prevent from promoting (pull-up) ohmic leakage especially.

Background technology

High-definition multi-media interface (High Definition Multimedia Interface, HDMI) being a kind of for transmitting audio/video connector interface that is uncompressed, enciphered digital crossfire, most audio/video source (such as: box, blue light disc player etc. on machine) can being coupled to an audio devices and/or video-frequency monitor (such as: digital television).

Consult Fig. 1, it shows the schematic diagram of the audio-video system be made up of the AV device at the multiple HDMI of having interface.As shown in Figure 1, HDMI specifications have specification one consumption electronic products to control (ConsumerElectronics Control, CEC) holding wire 11, can be used for controlling all devices being coupled to HDMI interface, digital camera (camcorder) 100 such as shown in Fig. 1, digital video recorder (Digital Video Recorder, DVR) 200, game machine (game console) 300 and television set (TV) 400 etc.

Consult Fig. 2, the detailed circuit schematic of part device in its display Fig. 1.What the AV device 12,13 shown in Fig. 2 can be AV device in Fig. 1 appoints the two, has the connection of CEC holding wire 11 therebetween.In general, each device 12,13 comprises a circuit board 121,131 and and is arranged on chip 122,132 on corresponding circuit board 121,131, and each chip 122,132 at output 123,133 to open drain electrode (open-drain) or similar mode to drive CEC holding wire 11.Therefore, the suggestion of HDMI specifications arranges the lifting resistance 124,134 of a 27K Ω on the circuit board 121,131 of each device 12,13, to give the high voltage level of set output terminal 123,133.Each promotes the shift ratio of the resistance value of resistance 124,134 generally in the scope of ± 5%.When one of them device (such as device 12) is not supplied electric power, another device (such as device 13) is supplied electric power, must prevent electric current from leaking into the power end 126 of device 12 via the resistance 124 of CEC holding wire 11 and device 12 from device 13, vice versa.Therefore, the suggestion of HDMI specifications arranges a diode 125,135 of connecting with corresponding resistance 124,134, with the direction of Limited Current on the circuit board 121,131 of each device 12,13.

If adopt the suggestion of HDMI specifications, must resistance 124,134 and these elements of diode 125,135 be prepared more, and the price of diode 125,135 is also high, the production cost of each device 12,13 can be caused higher, and, the voltage drop that each diode 125,135 produces when forward bias voltage drop is not 0, the equivalent resistance of corresponding resistance 124,134 can be made to become large, and error can reduce along with the voltage VDD of corresponding power end 126,136 and raise.

Summary of the invention

Therefore, namely object of the present invention is providing a kind of creepage preventing circuit that can reduce production cost and eliminate voltage drop.

So creepage preventing circuit of the present invention is applicable to be coupled to a power end and an output, and comprise a switch element and a bias voltage generation unit.This switch element comprises a P-type crystal pipe.This P-type crystal pipe comprises a first end, being coupled to this power end and is coupled to the second end of this output, a grid and a base stage.This bias voltage generation unit exports the base stage of a bias voltage to this P-type crystal pipe, and when this power end is supplied electric power, make this bias voltage equal in fact the voltage of this power end, and when this power end is not supplied electric power, make this bias voltage equal in fact the voltage of this output.

And namely another object of the present invention is providing a kind of semiconductor chip that can reduce production cost.

So semiconductor chip of the present invention is applicable to be coupled to a power end and an output, and comprise a core circuit, a resistance unit and a unidirectional current unit.This core circuit is coupled in this output.This resistance unit is coupled in this output.This unidirectional current element coupling is between this resistance unit and this power end, be used for when this power end is supplied electric power, allow electric current from this power end conducting to this output, and when this power end is not supplied electric power, prevent in fact electric current from this output conducting to this power end.Wherein, this core circuit, this resistance unit and this unidirectional current unit are arranged in the middle of same semiconductor base.

Accompanying drawing explanation

Fig. 1 is a schematic diagram, and the audio-video system be made up of the AV device at the multiple HDMI of having interface is described;

Fig. 2 is a circuit diagram, illustrates knownly how to prevent leakage current;

Fig. 3 is a circuit diagram, and the first embodiment of creepage preventing circuit of the present invention is described;

Fig. 4 is a circuit diagram, and the second embodiment of creepage preventing circuit of the present invention is described;

Fig. 5 is a circuit diagram, and the operation principle of the second embodiment is described;

Fig. 6 is a circuit diagram, and a bias voltage generation unit of the second embodiment is described;

Fig. 7 is a circuit diagram, and a switch element of the second embodiment is described;

Fig. 8 is a circuit diagram, and the first embodiment of a variable resistance unit of the second embodiment is described; And

Fig. 9 is a circuit diagram, and the second embodiment of the variable resistance unit of the second embodiment is described.

Number in the figure is described as follows:

100 digital cameras

200 digital recorder shadow machines

300 game machines

400 television sets

11CEC holding wire

12,13 AV devices

121,131 circuit boards

122,132 chips

123,133 outputs

124,134 resistance is promoted

125,235 diodes

126,136 power ends

2 creepage preventing circuits

21 promote resistance

22 diodes

3 circuit boards

30 chips

31 outputs

32 acp chips

4 power ends

5 creepage preventing circuits

51 bias voltage generation units

511~513PMOS

514~515NMOS

516 ~ 518 resistance

53 switch elements

531~534PMOS

535~537NMOS

538 ~ 541 resistance

55,55 ' variable resistance unit

551 switches

552 resistance

553 switches

554 resistance

6 circuit boards

60 chips

61 outputs

62 core circuits

7 power ends

8 earth terminals

9PMOS

91,92 junction diodes

Embodiment

Aforementioned and other technology contents, feature and effect for the present invention, in the detailed description of following cooperation with reference to graphic two embodiments, can clearly present.In addition, although the present invention is described for the CEC signal output part in HDMI interface, but those skilled in the art should understand, application of the present invention is not as limit, other drain or the similar low speed signal transmission specification opened drain electrode mode and output signal to open in audio-visual interface, audio-visual interface such as such as DVI, DisplayPort, UDI etc., all can adopt technology of the present invention.

Consult Fig. 3, its display is according to the circuit diagram of the creepage preventing circuit 2 shown in first embodiment of the invention.Creepage preventing circuit 2 is built in being in a chip 30, and is coupled to power end 4 and an output 31.Chip 30 is arranged on a circuit board 3, and comprise the core circuit 32 that is coupled to output 31.Creepage preventing circuit 2 comprises a lifting resistance 21 and a diode 22.The anode of diode 22 is coupled to power end 4, and its negative electrode is coupled to output 31 via lifting resistance 21, by the interior diode 22 be built in chip 30, then when chip 30 or when being assembled with the AV device powered-down of chip 30 (now the voltage VDD of power end 4 equals 0), because diode 22 is in the state of reverse bias (reverse biased), the signal be positioned on CEC holding wire can not produce leakage current to power end 4 through the lifting resistance 21 being built in chip 30.It is noted that at this, due to manufacture of semiconductor skew, promote the shift ratio of the resistance value of resistance 21 generally in the scope of ± 20%.The shift ratio of the resistance value promoting resistance 21 can be reduced in the scope of ± 5% by adjustment manufacture of semiconductor, to make lifting resistance 21, there is more accurate resistance value.

The present embodiment is by building in chip 30 by lifting resistance 21 and diode 22, do not need many preparation resistance and these elements of diode, production cost can be reduced, but the problem that the voltage drop that diode 22 produces when forward bias voltage drop can affect the equivalent resistance promoting resistance 21 still exists.In addition; although the diode 22 be built within above-described embodiment in chip 30 is example explanation; but the present invention is not as limit; other equivalence can reach diode reverse bias effect to avoid being built in the semiconductor circuit components in chip or circuit configurations in leakage current generation; also belong to scope, below the second embodiment of the present invention of description is one example.

Consult Fig. 4, its display is according to the circuit diagram of the creepage preventing circuit 5 shown in second embodiment of the invention.Creepage preventing circuit 5 is built in being in a chip 60, and is coupled to power end 7, earth terminal 8 and an output 61.Chip 60 is arranged on a circuit board 6, and comprise the core circuit that is coupled to output 61.Creepage preventing circuit 5 comprises bias voltage generation unit 51, switch element 53 and a variable resistance unit 55.Before these unit 51,53,55 of detailed description, the operation principle of the present embodiment will be first described below.

Consult Fig. 5, the operation principle of the creepage preventing circuit 5 of its display second embodiment of the invention.The profile of one typical P-type mos (PMOS) 9 is as shown in Fig. 5 (a), and as shown in Fig. 5 (b), the source S, one being coupled to power end 7 that comprises PMOS 9 is coupled to the drain D of output 61, a grid G and a base stage B (when bulk/body, PMOS in figure and N-type well).In time normally operating, can wish to make the base stage B of PMOS 9 and source S equipotential (representing to be coupled in figure), to eliminate the matrix effect (body effect) of PMOS 9.But, when power end 7 is not supplied electric power (now the voltage VDD of power end 7 equals 0), even if PMOS 9 not conducting, electric current still may leak into power end 7 from output 61 via the parasitic junction diode 91 (being now forward bias voltage drop) between the drain D of PMOS 9 and base stage B.As shown in Fig. 5 (c), in this case, if make the base stage B of PMOS 9 and drain D equipotential (representing to be coupled in figure), then electric current cannot leak into power end 7 from output 61 via the parasitic junction diode 92 (being now reverse bias) between the base stage B of PMOS 9 and source S.Therefore, if the diode 22 in Fig. 3 is replaced to PMOS 9, and when power end 4 is supplied electric power, make PMOS 9 operate in base stage B and power end 4 equipotential, the matrix effect of PMOS 9 can be eliminated; And when power end 4 is not supplied electric power, make PMOS 9 not conducting, and make PMOS 9 operate in base stage B and output 31 equipotential, then can prevent leakage current.In addition, the voltage drop produced when conducting due to PMOS 9 again closely 0 (much smaller than diode 22 in forward bias voltage drop time the voltage drop that produces), then diode 22 is replaced to PMOS 9 and can also eliminate voltage drop that diode 22 produces when forward bias voltage drop to the impact of equivalent resistance promoting resistance 21.

After understanding the illustrating of operation principle for the present embodiment in as Fig. 5, next how detailed description bias voltage generation unit 51, switch element 53 and variable resistance unit 55 realize.Due to MOS originally as source S end points and originally may change as drain D and source S respectively along with change in voltage as the end points of drain D, in order to avoid obscuring, when following description which couple relation, use first end T1 respectively instead and the second end T2 represents, when first end T1 is as source S, second end T2 is then as drain D, and when first end T1 is as drain D, the second end T2 is then as source S.

Consult Fig. 6, the circuit diagram of the bias voltage generation unit 51 of its display shown in Fig. 4.Bias voltage generation unit 51 exports a bias voltage VBIAS, and when power end 7 is supplied electric power, make bias voltage VBIAS equal in fact the voltage VDD of power end 7, and when power end 7 is not supplied electric power, make bias voltage VBIAS equal in fact the voltage of output 61.Bias voltage generation unit 51 comprises one the one PMOS 511, the 2nd PMOS 512, the 3rd PMOS 513,1 first N-type metal-oxide semiconductor (MOS) (NMOS) 514, the 2nd NMOS 515,1 first resistance 516,1 second resistance 517 and one the 3rd resistance 518.

The grid G and one that the second end T2, one that a first end T1, one being coupled to output 61 is coupled to the node of output offset voltage VBIAS is coupled to power end 7 via the first resistance 516 of comprising one PMOS 511 is coupled to the base stage B of bias voltage VBIAS.2nd PMOS 512 comprises the base stage B that a first end T1, being coupled to power end 7 is coupled to the second end T2 of the node of output offset voltage VBIAS, a grid G and is coupled to bias voltage VBIAS.3rd PMOS 513 comprises the second end T2, that a first end T1, being coupled to output 61 is coupled to the grid G of the 2nd PMOS 512 is coupled to power end 7 grid G via the second resistance 517, and the base stage B that is coupled to bias voltage VBIAS.One NMOS 514 comprises the second end T2, that a first end T1, is coupled to the grid G of the 2nd PMOS 512 is coupled to power end 7 grid G via the 3rd resistance 518, and the base stage B that is coupled to earth terminal 8.2nd NMOS 515 comprises the grid G that the second end T2, that a first end T1, being coupled to earth terminal 8 is coupled to the first end T1 of a NMOS 514 receives a bias voltage control signal (from core circuit 62), and the base stage B that is coupled to earth terminal 8.

When power end 7 is supplied electric power (now the voltage VDD of power end 7 is greater than 0) and the voltage of output 61 is not more than the voltage VDD of power end 7,3rd PMOS 513 not conducting, and NOMS 514 conducting, if bias voltage control signal makes the 2nd NMOS 515 conducting, then the voltage of earth terminal 8 can be passed to the grid G of the 2nd PMOS 512, to make the 2nd PMOS 512 conducting, and due to a now PMOS 511 not conducting, the voltage VDD finally will bias voltage VBIAS being caused to equal power end 7.When power end 7 is not supplied electric power (now the voltage VDD of power end 7 equals 0) and the voltage of output 61 is greater than the voltage VDD of power end 7, 3rd PMOS 513 conducting, and a NOMS 514 not conducting, the voltage of output 61 can be passed to the grid G of the 2nd PMOS 512, to make the 2nd PMOS 512 not conducting, and due to now PMOS 511 conducting, the voltage finally will bias voltage VBIAS being caused to equal output 61, now, due to not from output 61 to the current path of power end 7 and earth terminal 8, the generation of leakage current can be prevented.

It should be noted that, first to the 3rd resistance 516 ~ 518 is optionally (optional), to prevent MOS 511,513,514 at static discharge (Electrical Static Discharge, ESD) period impairedly adds, when not needing to consider ESD, can remove these resistance 516 ~ 518, now, the grid G of MOS 511,513,514 is all coupled to power end 7.2nd NMOS515 and bias voltage control signal are also optionally, add in order to common output 61, or in order to be supplied electric power at power end 7 and output 61 voltage is greater than the voltage of power end 7 time prevent electric current from adding from output 61 adverse current to power end 7, in other cases, the 2nd NMOS515 and bias voltage control signal can be removed, now, the first end T1 of a NMOS 514 is coupled to earth terminal 8.

Consult Fig. 7, switch element 53 comprises one the 4th PMOS 531, the 5th PMOS 532, the 6th PMOS 533, the 7th PMOS 534, the 3rd NMOS 535, the 4th NMOS 536, the 5th NMOS 537, the 4th resistance 538,1 the 5th resistance 539,1 the 6th resistance 540 and one the 7th resistance 541.Wherein it is especially noted that the 4th PMOS 531 instead of the position of diode 22 in Fig. 3 and played same function, that is the leakage phenomenon from output 61 to power end 7 can not be produced when power end 7 is not supplied electric power.

4th PMOS 531 comprises the base stage B that a first end T1, being coupled to power end 7 is coupled to the second end T2 of variable resistance unit 55, a grid G and receives bias voltage VBIAS.The base stage B that the first end T1, that 5th PMOS 532 comprises reception one switch-over control signal (from core circuit 62) is coupled to the second end T2 of the grid G of the 4th PMOS 531, a grid G and receives bias voltage VBIAS.6th PMOS 533 comprises the base stage B that grid G and that the second end T2, that a first end T1, being coupled to output 61 is coupled to the grid G of the 4th PMOS 531 is coupled to power end 7 via the 4th resistance 538 receives bias voltage VBIAS.7th PMOS 534 comprises the base stage B that grid G and that the second end T2, that a first end T1, being coupled to output 61 is coupled to the grid G of the 5th PMOS 532 is coupled to power end 7 via the 5th resistance 539 receives bias voltage VBIAS.The grid G and one that the second end T2, that the first end T1, that 3rd NMOS 535 comprises a reception switch-over control signal is coupled to the grid G of the 4th PMOS 531 is coupled to power end 7 via the 6th resistance 540 is coupled to the base stage B of earth terminal 8.The grid G and one that the second end T2, one that a first end T1, one is coupled to the grid G of the 5th PMOS 532 is coupled to power end 7 via the 7th resistance 541 of comprising 4th NMOS 536 is coupled to the base stage B of earth terminal 8.5th NMOS 537 comprises that a first end T1, being coupled to earth terminal 8 is coupled to the second end T2 of the first end T1 of the 4th NMOS 536, a grid G and receiving an output enable signal (from core circuit 62) is coupled to the base stage B of earth terminal 8.

When power end 7 is supplied electric power (now the voltage VDD of power end 7 is greater than 0) and the voltage of output 61 is not more than the voltage VDD of power end 7, 7th PMOS 534 not conducting, and the 4th NOMS 536 conducting, if output enable signal makes the 5th NMOS 537 conducting, then the voltage of earth terminal 8 can be passed to the grid G of the 5th PMOS 532, to make the 5th PMOS 532 conducting, now the 3rd NMOS 535 conducting simultaneously, and the 6th PMOS 533 not conducting, then switch-over control signal can be passed to the grid G of the 4th PMOS 531, to control the 4th PMOS 531 whether conducting.When power end 7 is not supplied electric power (now the voltage VDD of power end 7 equals 0) and the voltage of output 61 is greater than the voltage VDD of power end 7, 7th PMOS 534 conducting, and the 4th NMOS 536 not conducting, the voltage of output 61 can be passed to the grid G of the 5th PMOS 532, to make the 5th PMOS 532 not conducting, and now the 3rd NMOS 535 also not conducting, and the 6th PMOS 533 conducting, the voltage of output 61 can be passed to the grid G of the 4th PMOS 531, to make the 4th PMOS531 not conducting, now, due to not from output 61 to power end 7, the current path of earth terminal 8 and switch-over control signal, leakage current can be prevented.

It should be noted that the 4th to the 7th resistance 538 ~ 541 is optionally, in order to prevent MOS533 ~ 536 impaired and add during ESD, when not needing to consider ESD, can remove these resistance 538 ~ 541, now, the grid G of MOS 533 ~ 536 is all coupled to power end 7.5th NMOS 537 and output enable signal are also optionally, add in order to common output 61, or in order to be supplied electric power at power end 7 and output 61 voltage is greater than the voltage of power end 7 time prevent electric current from adding from output 61 adverse current to power end 7, in other cases, the 5th NMOS 537 and output enable signal can be removed, now, the first end T1 of the 4th NMOS 536 is coupled to earth terminal 8.Whether switch-over control signal promotes resistance as one for controlling variable resistance unit 55, when switch-over control signal makes the 4th PMOS 531 conducting, variable resistance unit 55 can give the high voltage level of set output terminal 61, and when switch-over control signal makes the 4th PMOS 531 not conducting, variable resistance unit 55 is effect not.

Consult Fig. 8 and Fig. 9, variable resistance unit 55,55 ' comprises plural switch 551,553 and electrical complex 552,554.In the present embodiment, each switch 551,553 realizes with a PMOS, and each PMOS comprises the base stage of a reception bias voltage VBIAS.Switch 551,553 can be controlled, and to change the couple state of resistance 552,554, and then changes the resistance value of variable resistance unit 55.Therefore, even if the resistance value of resistance 552,554 changes along with manufacture of semiconductor skew, still can pass through control switch 551,553, make the resistance value that the resistance value of variable resistance unit 55 reaches default.

It should be noted that, in fig. 8, variable resistance unit 55 is that the mode of connecting realizes, and in fig .9, variable resistance unit 55 realizes in parallel, but in other embodiments, variable resistance unit 55 also can realize in the mode of connection in series-parallel combination, and these implementations are known to a person of ordinary skill in the art, explanation will not be added herein.

In sum, the present embodiment is built in being in chip 60, can reduce production cost; And utilize the 4th PMOS 531 of switch element 53 to replace the diode 125,135 in Fig. 1, can voltage drop be eliminated; And when power end 7 is not supplied electric power, make base stage and output 61 equipotential of each PMOS in bias voltage generation unit 51, switch element 53 and variable resistance unit 55, coordinate the conducting/not on-state suitably setting each MOS in these unit 51,53,55 again, can leakage current be prevented; Moreover the resistance unit being built in chip in the variable resistance unit 55,55 ' in Fig. 8 and Fig. 9 also provides precisely can correct the ability of (calibration).Therefore, really object of the present invention can be reached.

The present invention also provides a kind of semiconductor chip (such as: the chip 30 in Fig. 3, or the chip 60 in Fig. 4), comprise a core circuit (such as: the core circuit 32 in Fig. 3, or the core circuit 62 in Fig. 4), a resistance unit (such as: the lifting resistance 21 in Fig. 3, or the variable resistance unit 55 in Fig. 4) and a unidirectional current unit (the bias voltage generation unit 51 such as: the diode 22 in Fig. 3, or in Fig. 4 and switch element 53).Core circuit, resistance unit and unidirectional current unit are arranged in same semiconductor base.

Above-described is only embodiments of the invention, can not limit scope of the invention process with this, as long as the simple equivalence namely done according to claim and invention description content changes and modifies, all still remains within the scope of the patent.

Claims (3)

1. a semiconductor chip, is applicable to be coupled to a power end, an output and an earth terminal, and comprises:
One core circuit, is coupled in this output;
One resistance unit, is coupled in this output; And
One unidirectional current unit, be coupled between this resistance unit and this power end, be used for when this power end is supplied electric power, allow electric current from this power end conducting to this output, and when this power end is not supplied electric power, prevent in fact electric current from this output conducting to this power end;
Wherein, this core circuit, this resistance unit and this unidirectional current unit are arranged in the middle of same semiconductor base;
Wherein, this unidirectional current unit comprises a switch element and a bias voltage generation unit,
This switch element comprises a P-type crystal pipe P1, and this P-type crystal pipe P1 comprises a first end, being coupled to this power end and is coupled to the second end of this resistance unit, a grid and a base stage;
This bias voltage generation unit exports the base stage of a bias voltage to this P-type crystal pipe P1, and when this power end is supplied electric power, make this bias voltage equal in fact the voltage of this power end, and when this power end is not supplied electric power, make this bias voltage equal in fact the voltage of this output;
This bias voltage generation unit comprises:
One P-type crystal pipe P2, comprises a first end, being coupled to this output and is coupled to the grid that second end, of node exporting this bias voltage is coupled to this power end, and the base stage that receives this bias voltage;
One P-type crystal pipe P3, comprises the second end, a grid that a first end, being coupled to this power end is coupled to the node exporting this bias voltage, and the base stage of this bias voltage of reception;
One P-type crystal pipe P4, comprises the grid that the second end, that a first end, being coupled to this output is coupled to the grid of this P-type crystal pipe P3 is coupled to this power end, and the base stage that receives this bias voltage; And
One N-type transistor N1, comprises the grid that the second end, that a first end, being coupled to this earth terminal is coupled to the grid of this P-type crystal pipe P3 is coupled to this power end, and the base stage that is coupled to this earth terminal.
2. semiconductor chip as claimed in claim 1, wherein, this core circuit more exports a switch-over control signal, this switch element is when this power end is supplied electric power, transmit the grid of this switch-over control signal to this P-type crystal pipe P1, and when this power end is not supplied electric power, transmit the grid of voltage to this P-type crystal pipe P1 of this output.
3. semiconductor chip as claimed in claim 2, wherein, this switch element more comprises:
One P-type crystal pipe P5, the first end, comprising this switch-over control signal of reception is coupled to the second end, a grid of the grid of this P-type crystal pipe P1, and the base stage of this bias voltage of reception;
One P-type crystal pipe P6, comprises the grid that the second end, that a first end, being coupled to this output is coupled to the grid of this P-type crystal pipe P1 is coupled to this power end, and the base stage that receives this bias voltage;
One P-type crystal pipe P7, comprises the grid that the second end, that a first end, being coupled to this output is coupled to the grid of this P-type crystal pipe P5 is coupled to this power end, and the base stage that receives this bias voltage;
One N-type transistor N2, the second end, that the first end, comprising this switch-over control signal of reception is coupled to the grid of this P-type crystal pipe P1 is coupled to the grid of this power end, and the base stage that is coupled to this earth terminal; And
One N-type transistor N3, comprises the grid that the second end, that a first end, being coupled to this earth terminal is coupled to the grid of this P-type crystal pipe P5 is coupled to this power end, and the base stage that is coupled to this earth terminal.
CN201110407965.9A 2008-04-17 2008-04-17 Semiconductor chip CN102545878B (en)

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Hitachi,Ltd.High-Definition Multimedia Interface Specification Version 1.3a.《High-Definition Multimedia Interface Specification Version 1.3a》.2006,第5of156页, 8of156页, 11of156页, 39of156页, CEC-7of97页. *

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