CN102543873A - Autocollimation P<+> shallow junction doping technological method - Google Patents

Abstract

The invention relates to an autocollimation P<+> shallow junction doping technological method. The technological method comprises the following steps: (1) photoetching N<+>/injecting N<+>: carrying out N-type impurity source electrode photoetching and injection on a P-type silicon substrate (P-SUB) on which P-type well (PW) and an N-type well (NW), a photoresist (PR) and a field oxide (FOX) are formed, and forming an N<+> source electrode and an N<+> drain electrode of the PW; (2) depositing low-pressure tetraethyl orthosilicate (LPTEOS): depositing a layer of LPTEOS on the surface of a silicon slice; (3) carrying out P+S/D photoetching/erosion: carrying out P-type impurity drain electrode photoetching and erosion, wherein after the step 3, the following steps are carried out; (4) carrying out N+S/D annealing (P+S/D adulteration): carrying out furnace tube annealing under BH3 atmosphere, thereby achieving P<+> region adulteration and N<+> doping activation; and (5) forming a P<+> source electrode and a P<+> drain electrode of an N-type well. According to the autocollimation P<+> shallow junction doping technological method provided by the invention, P<+> source/drain region shallow junction is realized, and the junction capacitance and the overlapping capacitance are reduced.

Description

Autoregistration P+ shallow junction doping process method

[technical field]

The present invention relates to the CMOS source-drain area and form process, relate in particular to a kind of process that adopts the solid-source doping method to form the CMOS source-drain area.

[background technology]

Along with dwindling of device feature size, junction depth requires more and more shallow, promptly requires shallow junction even ultra shallow junction.Shallow junction is in substrate, to form the shallow degree of depth, has high concentration and overactivity rate dopant, and has the knot of abrupt junction section in the horizontal and vertical directions.

Shallow junction is formed by ion implantation or solid phase diffusion method usually.In ion implantation, ion implantor is injected into foreign ion in the substrate with high accelerating voltage accelerated impurity ion then, forms shallow junction.In solid phase diffusion method, on substrate, form the solid-state diffusion source, then the diffuse dopants the solid-state diffusion source in and mix in the substrate formation shallow junction.

See also Fig. 1 to Fig. 3, traditional deep-submicron CMPS technology in the process that source-drain area forms all be adopt N+ photoetching/injections-＞P+ photoetching/injection-＞mode that source-drain area is annealed realizes the source-drain area of metal-oxide-semiconductor.Its diffusion rate is much larger than arsenic but the boron of the P+ source-drain area that this mode forms leaks in follow-up source in the annealing thermal process; Therefore the P+ junction depth in the CMOS technology is always greater than the N+ junction depth; Simultaneously because the horizontal proliferation that diffusion rate is accelerated to cause is serious, so the channel length of PMOS always is slightly larger than the NMOS channel length and prevents channel punchthrough.In addition, the horizontal proliferation of P+ source-drain area seriously also can make the overlapping size of source-drain area and grid increase, and causes the overlap capacitance increase of source-drain area and grid and the increase of junction capacitance, thereby reduces the switching speed of logical circuit and the transient response of RF circuit.

Therefore, a kind of process that forms shallow junction source-drain area CMPS need be provided.

[summary of the invention]

The object of the present invention is to provide a kind of autoregistration P+ shallow junction doping process method, it has realized P+ source-drain area shallow junction, reduces junction capacitance and overlap capacitance, has improved device performance.

For realizing above-mentioned purpose, the invention relates to a kind of autoregistration P+ shallow junction doping process method, it comprises step:

1) N+ photoetching/N+ injects: on the P type silicon substrate P-SUB that is formed with P type trap PW and N type trap NW, photoresist PR and field oxide FOX, carry out N n dopant source n aurora quarter and inject the N+ source electrode and the N+ drain electrode of formation P type trap;

2) low pressure silicon oxide deposition (LPTEOS) deposition: at silicon chip surface deposition one deck LPTEOS;

3) P+S/D photoetching/corrosion: see also Fig. 6, p type impurity drain electrode photoetching and corrosion, the LPTEOS that above-mentioned P+ is regional etches away;

4) N+S/D annealing (P+S/D doping): under BH3 atmosphere, carry out boiler tube annealing, thereby reach P+ region doping and N+ doping activation;

5) be formed with P+ source electrode and the P+ drain electrode of N type trap.

As further improvement of the present invention, in the said annealing steps, main thermal process is used for boron and spreads from BH3 atmosphere to silicon chip surface, and the atom that High temperature diffusion is mixed is activated.

The invention has the beneficial effects as follows: through autoregistration P+ shallow junction doping process method, realized P+ source-drain area shallow junction, reduced junction capacitance and overlap capacitance.

[description of drawings]

Fig. 1 is the process schematic representation of N+ photoetching/injection in the cmos process flow in the prior art;

Fig. 2 is the process schematic representation of P+ photoetching/injection in the cmos process flow in the prior art;

Fig. 3 is S/D annealing and form the process schematic representation of resulting devices CMOS in the cmos process flow in the prior art;

Fig. 4 is the sketch map of N+ photoetching/N+ injection technology in the autoregistration P+ shallow junction doping process method of the present invention;

Fig. 5 is the sketch map of LPTEOS depositing operation in the autoregistration P+ shallow junction doping process method of the present invention;

Fig. 6 is the sketch map of P+S/D photoetching/etching process in the autoregistration P+ shallow junction doping process method of the present invention;

Fig. 7 is the sketch map of N+S/D annealing (P+S/D doping) technology in the autoregistration P+ shallow junction doping process method of the present invention;

Fig. 8 is the pattern sketch map of the final device CMOS that forms of autoregistration P+ shallow junction doping process method of the present invention.

[embodiment]

Autoregistration P+ shallow junction doping process method of the present invention may further comprise the steps:

N+ photoetching/N+ injects: see also Fig. 4, on the P type silicon substrate P-SUB that is formed with P type trap PW and N type trap NW, photoresist PR and field oxide FOX, carry out N n dopant source n aurora quarter and inject the N+ source electrode and the N+ drain electrode of formation P type trap;

Low pressure silicon oxide deposition (LPTEOS) deposition: see also Fig. 5, at silicon chip surface deposition one deck LPTEOS;

P+S/D photoetching/corrosion: see also Fig. 6, p type impurity drain electrode photoetching and corrosion, the LPTEOS that above-mentioned P+ is regional etches away;

N+S/D anneals (P+S/D doping): see also Fig. 7, under BH3 atmosphere, carry out boiler tube annealing, thereby reach P+ region doping and N+ doping activation.In the annealing process, main thermal process is used for boron and spread from BH3 atmosphere to silicon chip surface, and the atom that High temperature diffusion is mixed is activated, and need not the subsequent thermal process and activates, so realized P+ shallow junction purpose.The As in N+ zone so not disturbed by boron element, does not have the risk of doped chemical outdiffusion because the LPTEOS protection is arranged yet simultaneously.

The resulting devices shape appearance figure is as shown in Figure 8, therefore is formed with the P+ source electrode and the P+ drain electrode of N type trap.

Special needs to be pointed out is that only with this autoregistration P+ shallow junction doping process method as an example, the autoregistration P+ shallow junction doping process method of any kind all is suitable for the principle that the present invention discloses in practical application in the specific embodiment of the invention.For the person of ordinary skill of the art, that under instruction of the present invention, is done changes to equivalence of the present invention, must be included in the scope that claim of the present invention advocates.

Claims (2)

1. autoregistration P+ shallow junction doping process method, it comprises step:

1) N+ photoetching/N+ injects: on the P type silicon substrate P-SUB that is formed with P type trap PW and N type trap NW, photoresist PR and field oxide FOX, carry out N n dopant source n aurora quarter and inject the N+ source electrode and the N+ drain electrode of formation P type trap;

2) low pressure silicon oxide deposition (LPTEOS) deposition: at silicon chip surface deposition one deck LPTEOS;

3) P+S/D photoetching/corrosion: p type impurity drain electrode photoetching and corrosion, the LPTEOS that above-mentioned P+ is regional etches away;

4) N+S/D annealing (P+S/D doping): under BH3 atmosphere, carry out boiler tube annealing, thereby reach P+ region doping and N+ doping activation;

5) be formed with P+ source electrode and the P+ drain electrode of N type trap.

2. autoregistration P+ shallow junction doping process method as claimed in claim 1 is characterized in that, in the said annealing steps, main thermal process is used for boron and spreads from BH3 atmosphere to silicon chip surface, and the atom that High temperature diffusion is mixed is activated.

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