CN102509537B - Shift register of display device - Google Patents
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- CN102509537B CN102509537B CN 201110322397 CN201110322397A CN102509537B CN 102509537 B CN102509537 B CN 102509537B CN 201110322397 CN201110322397 CN 201110322397 CN 201110322397 A CN201110322397 A CN 201110322397A CN 102509537 B CN102509537 B CN 102509537B
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Abstract
The invention discloses a shift register of a display device. The shift register comprises shift registering units in plural level tandem connection, and each level of shift registering unit comprises an input circuit, a boosting circuit and a pull-down circuit. The shift registering unit receives an input voltage at an input end, and provides an output voltage at an output end. The input circuit is used for controlling a signal conduction path between a first clock signal and a first node according to the input voltage. The boosting circuit is used for controlling the signal conduction path between a second clock signal and the output end according to a potential of the first node. The pull-down circuit comprises a pull-down unit and a control unit. The pull-down unit is used for maintaining the potential of the first node or the output end according to the potential of the second node. The control unit is used for maintaining the potential of the second node according to a first bias and the potential of the first node. In the liquid crystal display device in the invention, the pull-down circuit can perform the pull-down with less elements; and not only the circuit layout is simplified, but also the potential of the output end OUT is effectively maintained.
Description
The application is that application number is 2009101591900, the applying date is on July 22nd, 2009, denomination of invention is divided an application for the patented claim of " shift register of display device ".
Technical field
The present invention is relevant to a kind of shift register, refers to a kind of shift register of LCD especially.
Background technology
LCD (liquid crystal display, LCD) have low radiation, volume is little and advantage such as low power consuming, replace traditional cathode-ray tube display (cathode ray tube display gradually, CRT), thereby be widely used in pen this note computer, personal digital assistant (personal digital assistant, PDA), flat-surface television, or on the information product such as mobile phone.The mode of conventional liquid crystal is to utilize the external drive chip to drive pixel on the panel with show image, but in order to reduce component number and to reduce manufacturing cost, the structure that develops into gradually in recent years driving circuit directly is made on the display panel, for example use gate driver circuit (gate driver) is integrated in liquid crystal panel (gate on array, technology GOA).
Please refer to Fig. 1, Fig. 1 is the simplification module diagram of a liquid crystal indicator 100 in the prior art.Fig. 1 has only shown the part-structure of liquid crystal indicator 100, comprises a plurality of gate lines G L (1)～GL (N), a shift register (shift register) 110, one clock (clock) generator 120 and a power supply unit 130.Clock generator 120 can provide shift register 110 runnings required initial pulse signal VST and two clock signal C K and XCK, and power supply unit 130 can provide shift register 110 runnings required operating voltage VSS.Clock signal C K and XCK be with predetermined period switch polarity between high electronegative potential, and have opposite polarity at one time.Shift register 110 includes shifting deposit unit SR (the 1)～SR (N) of plural number level serial connection, each grade shifting deposit unit is coupled to the first input end IN1 of corresponding gate line, next stage shifting deposit unit, and the second input end IN2 of previous stage shifting deposit unit.According to clock signal C K, XCK and initial pulse signal VST, shift register 110 can be exported gate drive signal GS (1)～GS (N) to corresponding gate lines G L (1)～GL (N) by shifting deposit unit SR (1)～SR (N) respectively in regular turn.
Please refer to Fig. 2, Fig. 2 be a n level shifting deposit unit SR (n) in the liquid crystal indicator 100 of prior art synoptic diagram (n between 1 and N between integer).Shifting deposit unit SR (n) comprises a first input end IN1, one second input end IN2, an output terminal OUT, a node Q (n), an input circuit 10, lifting circuit (pull-up circuit) 20, one pull-down circuit (pull-down circuit) 30, and one keeps circuit 40.The first input end IN1 of shifting deposit unit SR (n) is coupled to the output terminal OUT of previous stage shifting deposit unit SR (n-1), the second input end IN2 is coupled to the output terminal OUT of next stage shifting deposit unit SR (n+1), and output terminal OUT (n) is coupled to first input end IN1 and the gate lines G L (n) of next stage shifting deposit unit SR (n+1).In the liquid crystal indicator 100 of prior art, the transistor switch T1 of input circuit 10 keeps the current potential of node Q (n) according to previous stage gate drive signal GS (n-1), the transistor switch T2 and the T3 that promote circuit 20 export gate drive signal GS (n) according to current potential and the next stage gate drive signal GS (n+1) of node Q (n) respectively, the transistor switch T4 of pull-down circuit 30 keeps the current potential of node Q (n) according to next stage gate drive signal GS (n+1), and the transistor switch T5 of holding circuit 40 controls signal guided path between node Q (n) and the output terminal OUT according to clock signal C K.The liquid crystal indicator 100 of prior art needs to keep according to next stage gate drive signal GS (n+1) current potential of node Q (n), the circuit layout complexity, and the while also can't be kept the current potential of output terminal OUT effectively.
Please refer to Fig. 3, Fig. 3 is the simplification module diagram of a liquid crystal indicator 200 in the prior art.Fig. 2 has only shown the part-structure of liquid crystal indicator 200, comprises a plurality of gate lines G L (1)～GL (N), a shift register 210, a clock generator 220 and a power supply unit 230.Clock generator 220 can provide shift register 210 runnings required initial pulse signal VST and two clock signal C K and XCK, and power supply unit 230 can provide shift register 210 runnings required operating voltage VDD and VSS.Clock signal C K and XCK be with predetermined period switch polarity between high electronegative potential, and have opposite polarity at one time.Shift register 210 includes shifting deposit unit SR (the 1)～SR (N) of plural number level serial connection, and the output terminal of each grade shifting deposit unit is coupled to corresponding gate line and next stage shifting deposit unit.According to clock signal C K, XCK and initial pulse signal VST, shift register 210 can be exported gate drive signal GS (1)～GS (N) to corresponding gate lines G L (1)～GL (N) by shifting deposit unit SR (1)～SR (N) respectively in regular turn.
Please refer to Fig. 4, Fig. 4 be a n level shifting deposit unit SR (n) in the liquid crystal indicator 200 of prior art synoptic diagram (n between 1 and N between integer).Shifting deposit unit SR (n) comprises an input end IN (n), an output terminal OUT (n), an input circuit 10, promotes circuit 20, and a pull-down circuit 30.The input end IN (n) of shifting deposit unit SR (n) is coupled to previous stage shifting deposit unit SR (n-1), and output terminal OUT (n) is coupled to next stage shifting deposit unit SR (n+1) and gate lines G L (n).In the liquid crystal indicator 200 of prior art, the transistor switch T1 of input circuit 10 keeps the current potential of node Q1 (n) according to previous stage gate drive signal GS (n-1), the transistor switch T2 and the T3 that promote circuit 20 export gate drive signal GS (n) according to the current potential of node Q1 (n) and Q2 (n) respectively, and the transistor switch T4～T6 of pull-down circuit 30 then is used for keeping the current potential of node Q1 (n) and Q2 (n).The liquid crystal indicator 200 of prior art need not use next stage gate drive signal GS (n+1) to come as feedback signal, but still has the shortcoming of circuit layout complexity.
Summary of the invention
The invention provides a kind of shift register, it comprises the shifting deposit unit of plural number level serial connection, wherein each grade shifting deposit unit comprises an input end, an output terminal, a first node, a Section Point, an input circuit, a lifting circuit, and a pull-down circuit.This grade shifting deposit unit receives an input voltage in input end, and provides an output voltage in output terminal.Input circuit is controlled signal guided path between one first clock signal and this first node according to the current potential of this input voltage.Promote circuit and control signal guided path between a second clock signal and this output terminal so that this output voltage to be provided according to the current potential of this first node, wherein this first and second clock signal is with predetermined period switch polarity between a noble potential and an electronegative potential, and the polarity of this first and second clock signal is opposite in one-period.Pull-down circuit comprises a drop-down unit and a control module.The current potential of this first node or this output terminal is kept according to the current potential of this Section Point in this drop-down unit, and this control module is according to the current potential of keeping this Section Point according to the current potential of a bias voltage and this first node.
In liquid crystal indicator of the present invention, pull-down circuit can carry out drop-down running with less element, not only can simplify circuit layout, also can keep the current potential of output terminal OUT simultaneously effectively.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the simplification module diagram of a liquid crystal indicator in the prior art;
Fig. 2 is the synoptic diagram of a n level shifting deposit unit in the liquid crystal indicator of Fig. 1;
Fig. 3 is the simplification module diagram of another liquid crystal indicator in the prior art;
Fig. 4 is the synoptic diagram of a n level shifting deposit unit in the liquid crystal indicator of Fig. 3;
Fig. 5 is the simplification module diagram of a liquid crystal indicator among the present invention;
Fig. 6 is the synoptic diagram of a n level shifting deposit unit in the first embodiment of the invention;
Fig. 7 is the synoptic diagram of a n level shifting deposit unit in the second embodiment of the invention;
Fig. 8 is the simplification module diagram of another liquid crystal indicator among the present invention;
Fig. 9 is the synoptic diagram of a n level shifting deposit unit in the third embodiment of the invention;
Figure 10 is the synoptic diagram of a n level shifting deposit unit in the fourth embodiment of the invention.
Drawing reference numeral
10～14 input circuit VST initial pulse signals
20～24 promote circuit CK, XCK clock signal
30～34 pull-down circuit Q (n), P (n) node
41～44 drop-down unit T1～T8 transistor switches
51～54 control module VDD, VSS voltage
40 holding circuit OUT, OUT (n) output terminal
100,200,300,400 liquid crystal indicators
110,210,310,410 shift registers
120,220,320,420 clock generators
130,230,330,430 power supply units
IN1, IN2, IN (n) input end
GL (1)～GL (N), GL (n) gate line
GS (1)～GS (N), GS (n) gate drive signal
SR(1)～SR(N)、SR(n-1)、
SR (n), SR (n+1) shifting deposit unit
Embodiment
Please refer to Fig. 5, Fig. 5 is the simplification module diagram of a liquid crystal indicator 300 among the present invention.Fig. 5 has only shown the part-structure of liquid crystal indicator 300, comprises a plurality of gate lines G L (1)～GL (N), a shift register 310, a clock generator 320 and a power supply unit 330.Clock generator 320 can provide shift register 310 runnings required initial pulse signal VST and two clock signal C K and XCK, and power supply unit 330 can provide shift register 310 runnings required operating voltage VSS.Clock signal C K and XCK be with predetermined period switch polarity between high electronegative potential, and have opposite polarity at one time.Shift register 310 includes shifting deposit unit SR (the 1)～SR (N) of plural number level serial connection, and the output terminal of each grade shifting deposit unit is coupled to the input end of corresponding gate line and next stage shifting deposit unit.According to clock signal C K, XCK and initial pulse signal VST, shift register 310 can be exported gate drive signal GS (1)～GS (N) to corresponding gate lines G L (1)～GL (N) by shifting deposit unit SR (1)～SR (N) respectively in regular turn.
Please refer to Fig. 6, Fig. 6 be a n level shifting deposit unit SR (n) in the liquid crystal indicator 300 of first embodiment of the invention synoptic diagram (n between 1 and N between integer).Shifting deposit unit SR (n) comprises an input end IN (n), an output terminal OUT (n), node Q (n) and P (n), an input circuit 11, promotes circuit 21, and a pull-down circuit 31.The input end IN (n) of shifting deposit unit SR (N) is coupled to previous stage shifting deposit unit SR (n-1), and the output terminal OUT (n) of shifting deposit unit SR (n) is coupled to next stage shifting deposit unit SR (n+1) and gate lines G L (n).
Input circuit 11 comprises a transistor switch T1, its grid is coupled to the input end IN (n) of shifting deposit unit SR (n) to receive gate drive signal GS (n-1), its drain electrode is coupled to clock generator 320 with receive clock signal XCK, therefore and its source electrode is coupled to node Q (n), can control signal guided path between clock signal XCK and the node Q (n) according to gate drive signal GS (n-1).Promote circuit 21 and comprise a transistor switch T2, its grid is coupled to node Q (n), drain electrode is coupled to clock generator 320 with receive clock signal CK, therefore and the output terminal OUT (n) that source electrode is coupled to can control signal guided path between clock signal C K and the output terminal OUT (n) according to the current potential of node Q (n).
Pull-down circuit 31 comprises a drop-down unit 41 and a control module 51, drop-down unit 41 can be kept the current potential of node Q (n) or output terminal OUT (n) according to the current potential of node P (n), and control module 51 can be kept the current potential of node P (n) according to the current potential of clock signal C K, clock signal XCK and node Q (n).In the pull-down circuit 31 of first embodiment of the invention, drop-down unit 41 comprises transistor switch T3 and T4: the grid of transistor switch T3 is coupled to node P (n), drain electrode is coupled to output terminal OUT (n), and source electrode is coupled to power supply unit 330 to receive operating voltage VSS, therefore can keep the current potential of output terminal OUT (n) according to the current potential of node P (n); The grid of transistor switch T4 is coupled to node P (n), and drain electrode is coupled to node Q (n), and source electrode is coupled to power supply unit 330 to receive operating voltage VSS, therefore can keep the current potential of node Q (n) according to the current potential of node P (n).On the other hand, control module 51 comprises transistor switch T5～T7: the grid of transistor switch T5 and drain electrode all are coupled to clock generator 320 with receive clock signal CK, and source electrode is coupled to node P (n), therefore can keep the current potential of node P (n) according to clock signal C K; The grid of transistor switch T6 and drain electrode all are coupled to clock generator 320 with receive clock signal XCK, and source electrode is coupled to node P (n), therefore can keep the current potential of node P (n) according to clock signal XCK; The grid of transistor switch T7 is coupled to node Q (n), and drain electrode is coupled to node P (n), and source electrode is coupled to power supply unit 330 to receive operating voltage VSS, therefore can keep the current potential of node P (n) according to the current potential of node Q (n).
Outside the n level output cycle At All Other Times in, the gate drive signal GS (n) of shifting deposit unit SR (n) output device electronegative potential, therefore node Q (n) need maintain electronegative potential to guarantee transistor switch T2 for closing, and so the current potential of gate drive signal GS (n) just can not influenced by clock signal C K.The responsibility cycle (duty cycle) of supposing clock signal C K and XCK is all 1/2, respectively control 50% drop-down running by transistor switch T5 and T6 in the control module 51 this moment: when clock signal CK tool noble potential, transistor switch T5 is that conducting and transistor switch T6 are for closing, node P (n) can be pulled to the noble potential of clock signal C K by the transistor switch T5 of conducting, and then turn-on transistor switch T3 and T4 are to be pulled to electronegative potential bias voltage VSS with output terminal OUT (n) and node Q (n) respectively; When clock signal XCK tool noble potential, transistor switch T6 is that conducting and transistor switch T5 are for closing, node P (n) can be pulled to the noble potential of clock signal XCK by the transistor switch T6 of conducting, and then turn-on transistor switch T3 and T4 are to be pulled to electronegative potential bias voltage VSS with output terminal OUT (n) and node Q (n) respectively.
In the output cycle, node Q (n) need maintain noble potential with turn-on transistor switch T2 in the n level, and then the gate drive signal GS (n) of output device noble potential.Before the output cycle that enters shifting deposit unit SR (n), the transistor switch T1 of input circuit 11 can be exported the noble potential gate drive signal GS (n-1) in cycle by previous stage and open, and then node Q (n) is pulled to the noble potential of clock signal XCK.This moment, the transistor switch T7 of control module 51 also can be switched on, so node P (n) can be pulled to electronegative potential bias voltage VSS, and then closed transistor switch T3 and T4 to stop drop-down running.
Please refer to Fig. 7, Fig. 7 be a n level shifting deposit unit SR (n) in the liquid crystal indicator 300 of second embodiment of the invention synoptic diagram (n between 1 and N between integer).Shifting deposit unit SR (n) comprises an input end IN (n), an output terminal OUT (n), node Q (n) and P (n), an input circuit 12, promotes circuit 22, and a pull-down circuit 32.The input circuit 12 of second embodiment of the invention is identical with the structure that promotes circuit 21 with the input circuit 11 that promotes circuit 22 and first embodiment, and difference is the structure of pull-down circuit 32 in the second embodiment of the invention.The pull-down circuit 32 of second embodiment of the invention comprises a drop-down unit 42 and a control module 52.Drop-down unit 42 comprises transistor switch T3 and T4, can keep the current potential of node Q (n) or output terminal OUT (n) according to the current potential of node P (n).Control module 52 comprises transistor switch T5～T8, and transistor switch T5 and T6 can keep the current potential of node P (n) according to clock signal C K and XCK, and the current potential that transistor switch T7 in parallel and T8 can keep node P (n) according to the current potential of node Q (n).Transistor switch T7 and T8 driving force in parallel are stronger, so the liquid crystal indicator 300 of second embodiment of the invention can provide better drop-down running when keeping the current potential of node P (n).
Please refer to Fig. 8, Fig. 8 is the module diagram of a liquid crystal indicator 400 among the present invention.Fig. 8 has only shown the part-structure of liquid crystal indicator 400, comprises a plurality of gate lines G L (1)～GL (N), a shift register 410, a clock generator 420 and a power supply unit 430.Clock generator 420 can provide shift register 410 runnings required initial pulse signal VST and two clock signal C K and XCK, and power supply unit 430 can provide shift register 410 runnings required operating voltage VDD and VSS.Clock signal C K and XCK be with predetermined period switch polarity between high electronegative potential, and have opposite polarity at one time.Shift register 410 includes shifting deposit unit SR (the 1)～SR (N) of plural number level serial connection, and the output terminal of each grade shifting deposit unit is coupled to the input end of corresponding gate line and next stage shifting deposit unit.According to clock signal C K, XCK and initial pulse signal VST, shift register 410 can be exported gate drive signal GS (1)～GS (N) to corresponding gate lines G L (1)～GL (N) by shifting deposit unit SR (1)～SR (N) respectively in regular turn.
Please refer to Fig. 9, Fig. 9 be a n level shifting deposit unit SR (n) in the liquid crystal indicator 400 of third embodiment of the invention synoptic diagram (n between 1 and N between integer).Shifting deposit unit SR (n) comprises an input end IN (n), an output terminal OUT (n), node Q (n) and P (n), an input circuit 13, promotes circuit 23, and a pull-down circuit 33.The input end IN (n) of shifting deposit unit SR (N) is coupled to previous stage shifting deposit unit SR (n-1), and the output terminal OUT (n) of shifting deposit unit SR (n) is coupled to next stage shifting deposit unit SR (n+1) and gate lines G L (n).
Pull-down circuit 33 comprises a drop-down unit 43 and a control module 53, drop-down unit 43 can be kept the current potential of node Q (n) or output terminal OUT (n) according to the current potential of node P (n), and control module 53 can be kept the current potential of node P (n) according to the current potential of clock signal C K, clock signal XCK and node Q (n).In the pull-down circuit 33 of third embodiment of the invention, drop-down unit 43 comprises transistor switch T3 and T4: the grid of transistor switch T3 is coupled to node P (n), drain electrode is coupled to output terminal OUT (n), and source electrode is coupled to power supply unit 430 to receive operating voltage VSS, therefore can keep the current potential of output terminal OUT (n) according to the current potential of node P (n); The grid of transistor switch T4 is coupled to node P (n), and drain electrode is coupled to node Q (n), and source electrode is coupled to power supply unit 430 to receive operating voltage VSS, therefore can keep the current potential of node Q (n) according to the current potential of node P (n).On the other hand, control module 53 comprises transistor switch T5 and T6: the grid of transistor switch T5 and drain electrode all are coupled to power supply unit 430 to receive operating voltage VDD, and source electrode is coupled to node P (n), therefore can keep the current potential of node P (n) according to operating voltage VDD; The grid of transistor switch T6 is coupled to node Q (n), and drain electrode is coupled to node P (n), and source electrode is coupled to power supply unit 430 to receive operating voltage VSS, therefore can keep the current potential of node P (n) according to the current potential of node Q (n).
Outside the n level output cycle At All Other Times in, the gate drive signal GS (n) of shifting deposit unit SR (n) output device electronegative potential, therefore node Q (n) need maintain electronegative potential to guarantee that transistor switch T2 is for closing, so the current potential of gate drive signal GS (n) just can not influenced by clock signal C K, this moment, the transistor switch T5 by control module 53 controlled drop-down running, node P (n) was pulled to the noble potential of operating voltage VDD by the transistor switch T5 of conducting.In the output cycle, node Q (n) need maintain noble potential with turn-on transistor switch T2 in the n level, and then the gate drive signal GS (n) of output device noble potential.Before the output cycle that enters shifting deposit unit SR (n), the transistor switch T1 of input circuit 13 can be exported the noble potential gate drive signal GS (n-1) in cycle by previous stage and open, and then node Q (n) is pulled to the noble potential of clock signal XCK.This moment, the transistor switch T6 of drop-down unit 43 also can be switched on, so node P (n) can be pulled to electronegative potential bias voltage VSS, and then closed transistor switch T3 and T4 to stop drop-down running.
Please refer to Figure 10, Figure 10 be a n level shifting deposit unit SR (n) in the liquid crystal indicator 300 of fourth embodiment of the invention synoptic diagram (n between 1 and N between integer).Shifting deposit unit SR (n) comprises an input end IN (n), an output terminal OUT (n), node Q (n) and P (n), an input circuit 14, promotes circuit 24, and a pull-down circuit 34.The input circuit 14 of fourth embodiment of the invention is identical with the structure that promotes circuit 23 with the input circuit 13 that promotes circuit 24 and the 3rd embodiment, and difference is the structure of pull-down circuit 34 in the fourth embodiment of the invention.The pull-down circuit 34 of fourth embodiment of the invention comprises a drop-down unit 44 and a control module 54.Drop-down unit 44 comprises transistor switch T3 and T4, can keep the current potential of node Q (n) or output terminal OUT (n) according to the current potential of node P (n).Control module 54 comprises transistor switch T5, T7, T8, the grid of transistor switch T5 and drain electrode all are coupled to power supply unit 430 to receive operating voltage VDD, and source electrode is coupled to node P (n), therefore can keep the current potential of node P (n) according to operating voltage VDD, and the current potential that transistor switch T7 in parallel and T8 can keep node P (n) according to the current potential of node Q (n).Transistor switch T7 and T8 driving force in parallel are stronger, so the liquid crystal indicator 300 of fourth embodiment of the invention can provide better drop-down running when keeping the current potential of node P (n).
In the aforementioned embodiment, transistor switch T1～T8 can be thin film transistor (TFT) (thin film transistor, TFT) switch, or the element of other tool similar functions.In liquid crystal indicator of the present invention, pull-down circuit can carry out drop-down running with less element, not only can simplify circuit layout, also can keep the current potential of output terminal OUT simultaneously effectively.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (11)
1. a shift register is characterized in that, described shift register comprises the shifting deposit unit of plural number level serial connection, and wherein each grade shifting deposit unit comprises:
One input end is used for receiving an input voltage;
One output terminal is used to provide an output voltage;
One first node;
One Section Point;
One input circuit is used for current potential according to described input voltage to control signal guided path between one first clock signal and the described first node;
One promotes circuit, being used for current potential according to described first node controls signal guided path between a second clock signal and the described output terminal so that described output voltage to be provided, wherein said first and second clock signals are with predetermined period switch polarity between a noble potential and an electronegative potential, and the polarity of described first and second clock signals is opposite in one-period; And
One pull-down circuit comprises:
One drop-down unit is used for current potential according to described Section Point to keep the current potential of described first node or described output terminal; And
One control module is used for keeping according to the current potential of one first bias voltage and described first node the current potential of described Section Point.
2. shift register as claimed in claim 1 is characterized in that, described input circuit comprises:
One first switch comprises:
One first end is used for receiving described first clock signal;
One second end is coupled to described first node; And
One control end is coupled to the input end of this grade shifting deposit unit.
3. shift register as claimed in claim 1 is characterized in that, described lifting circuit comprises:
One second switch comprises:
One first end is used for receiving described second clock signal;
One second end is coupled to described output terminal; And
One control end is coupled to described first node.
4. shift register as claimed in claim 1 is characterized in that, described drop-down unit comprises:
One the 3rd switch comprises:
One first end is coupled to described output terminal;
One second end is used for receiving one second bias voltage; And
One control end is coupled to described Section Point.
5. shift register as claimed in claim 1 is characterized in that, described drop-down unit comprises:
One the 4th switch comprises:
One first end is coupled to described first node;
One second end is used for receiving one second bias voltage; And
One control end is coupled to described Section Point.
6. shift register as claimed in claim 1 is characterized in that, described control module comprises:
One the 5th switch comprises:
One first end is used for receiving described first bias voltage;
One second end is coupled to described Section Point; And
One control end is coupled to first end of described the 5th switch; And
One the 6th switch comprises:
One first end is coupled to described Section Point;
One second end is used for receiving one second bias voltage; And
One control end is coupled to described first node.
7. shift register as claimed in claim 1 is characterized in that, described control module comprises in addition:
One minion is closed, and comprises:
One first end is coupled to described Section Point;
One second end is used for receiving described second bias voltage; And
One control end is coupled to the control end of described the 6th switch.
8. shift register as claimed in claim 1 is characterized in that, described input circuit comprises:
One first switch comprises:
One first end is used for receiving described first clock signal;
One second end is coupled to described first node; And
One control end is coupled to the input end of this grade shifting deposit unit;
Described lifting circuit comprises:
One second switch comprises:
One first end is used for receiving described second clock signal;
One second end is coupled to described output terminal; And
One control end is coupled to described first node;
Described drop-down unit comprises:
One the 3rd switch comprises:
One first end is coupled to described output terminal;
One second end is used for receiving one second bias voltage; And
One control end is coupled to described Section Point;
One the 4th switch comprises:
One first end is coupled to described first node;
One second end is used for receiving described second bias voltage; And
One control end is coupled to described Section Point; And
Described control module comprises:
One the 5th switch comprises:
One first end is used for receiving described first bias voltage;
One second end is coupled to described Section Point; And
One control end is coupled to first end of described the 5th switch; And
One the 6th switch comprises:
One first end is coupled to described Section Point;
One second end is used for receiving described second bias voltage; And
One control end is coupled to described first node.
9. shift register as claimed in claim 8 is characterized in that, described control module comprises in addition:
One minion is closed, and comprises:
One first end is coupled to described Section Point;
One second end is used for receiving described second bias voltage; And
One control end is coupled to the control end of described the 6th switch.
10. shift register as claimed in claim 8 is characterized in that, the current potential of described first bias voltage is higher than the current potential of described second bias voltage.
11. shift register as claimed in claim 1 is characterized in that, the input end of described shift register is coupled to the output terminal of a prime shift register to receive described input signal.
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| CN 201110322397 CN102509537B (en) | 2009-07-22 | 2009-07-22 | Shift register of display device |
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| CN2009101591900A Division CN101609719B (en) | 2009-07-22 | 2009-07-22 | Shift register of display device |
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| TWI497473B (en) * | 2013-07-18 | 2015-08-21 | Au Optronics Corp | Shift register circuit |
| CN104517575B (en) | 2014-12-15 | 2017-04-12 | 深圳市华星光电技术有限公司 | Shifting register and level-transmission gate drive circuit |
| CN105469759B (en) * | 2015-12-15 | 2018-10-19 | 深圳市华星光电技术有限公司 | A kind of shift register |
| CN105702192B (en) * | 2016-03-07 | 2019-01-11 | 北京大学深圳研究生院 | Shift register cell, shift register, gate driving circuit and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100353460C (en) * | 2004-08-16 | 2007-12-05 | 友达光电股份有限公司 | Shift register and display panel using said shift register |
| KR101300038B1 (en) * | 2006-08-08 | 2013-08-29 | 삼성디스플레이 주식회사 | Gate driving circuit and display apparatus having the same |
| CN101465165B (en) * | 2007-12-20 | 2011-05-25 | 胜华科技股份有限公司 | Shift register |
| CN101369460B (en) * | 2008-10-15 | 2012-08-22 | 友达光电股份有限公司 | Shift buffer |
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