CN102479765A - Packaging structure with semiconductor component - Google Patents

Packaging structure with semiconductor component Download PDF

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Publication number
CN102479765A
CN102479765A CN 201010571504 CN201010571504A CN102479765A CN 102479765 A CN102479765 A CN 102479765A CN 201010571504 CN201010571504 CN 201010571504 CN 201010571504 A CN201010571504 A CN 201010571504A CN 102479765 A CN102479765 A CN 102479765A
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China
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sidewall
conductive
reference
insulating material
located
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CN 201010571504
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Chinese (zh)
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CN102479765B (en
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蔡莉雯
陈国华
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日月光半导体制造股份有限公司
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Abstract

The invention discloses a packaging structure with a semiconductor component. The semiconductor component comprises a substrate body, a plurality of conductive columns and a plurality of metal gaskets. The conductive columns are arranged in through holes of the substrate body. The metal gaskets are electrically connected to the conductive columns, and at least one of the metal gaskets is provided with at least one arc-shaped side wall and at least one reference side wall, wherein the curvature of the arc-shaped side wall is different from that of the reference side wall. Therefore, the metal gaskets can be closer to ensure that the conductive columns can also be closer, and thus, more electrifying columns can be arranged in a limited space.

Description

具有半导体组件的封装结构 Semiconductor device having a package structure

技术领域 FIELD

[0001] 本发明关于一种半导体组件及具有半导体组件的封装结构,详言之,关于一种具有导通柱的半导体组件及具有该半导体组件的封装结构。 [0001] The present invention relates to a semiconductor device and a semiconductor device having a package structure, detail, relates to a package having a semiconductor device having a conductive via and the semiconductor element.

背景技术 Background technique

[0002] 已知半导体组件(例如芯片或中介板(Interposer))具有数个导通柱(Via)及数个金属垫(Metal Pad),这些金属垫位于这些导通柱上方,且电性连接这些导通柱。 [0002] Known semiconductor device (e.g. a chip or interposer (Interposer)) having a plurality of conductive via (Via) and a plurality of metal pads (Metal Pad), which is located in the conductive metal pads square column, and is electrically connected these conductive via. 以俯视观之,每一金属垫的面积会大于每一导通柱面积,而且这些金属垫的外围侧壁为圆形。 In plan view, the area of ​​each metal pad may be greater than the area of ​​each conductive pillar, and a peripheral side wall of the metal pad is circular. 因此,这些金属垫并无法靠的太近,导致这些导通柱的间距并无法有效地缩小。 Thus, the metal pad and not too close, resulting in the spacing of the conductive posts and can not be effectively reduced.

发明内容 SUMMARY

[0003] 本发明提供一种具有半导体组件的封装结构。 [0003] The present invention provides a package structure having a semiconductor device. 该封装结构包括一半导体组件、一芯片及一底胶。 The package structure includes a semiconductor device, a chip, and a primer. 该半导体组件包括一基材本体、数个导通柱(Conductive Vias)、一绝缘材料、一第二保护层及数个金属垫(Metal Pad)。 The semiconductor device includes a substrate main body, a plurality of conductive via (Conductive Vias), an insulating material, a second protective layer, and a plurality of metal pads (Metal Pad). 该基材本体具有一第一表面、一第二表面及至少一贯孔。 The substrate body having a first surface, a second surface and at least one through hole. 这些导通柱位于该至少一贯孔内。 The conductive posts located in the at least one through hole. 该绝缘材料位于这些导通柱及该至少一贯孔的侧壁之间。 The insulating material is disposed between the conductive via sidewall and said at least one through hole. 该第二保护层位于该第二表面,且具有至少一开口,以显露这些导通柱。 The second protective layer is located on the second surface, and having at least one opening to expose the conductive posts. 这些金属垫位于该至少一开口内且电性连接至这些导通柱。 The metal pad is located within the at least one opening and electrically connected to the conductive via. 这些金属垫包括至少一第一金属垫,该第一金属垫具有至少一第一弧状侧壁及至少一第一参考侧壁,其中该第一弧状侧壁的曲率与该第一参考侧壁的曲率不同。 These metal pad comprises at least a first metal pad, the first pad having at least one first arcuate side wall, and at least a first reference side wall, wherein the first arcuately shaped side wall curvature of the first sidewall of the reference different curvatures.

[0004] 该芯片位于该半导体组件上,该芯片具有数个导体组件,以电性连接这些金属垫。 [0004] The semiconductor chip is located on the assembly, the die assembly having a plurality of conductors, electrically connected to the metal pads. 该底胶位于该芯片及该半导体组件之间,以包覆这些导体组件。 This primer is located between the chip and the semiconductor element, to cover the conductor assembly.

[0005] 藉此,这些金属垫可以更靠近,使得这些导通柱亦可以更靠近,因而,在有限空间内,可以排列较多的导通柱。 [0005] Accordingly, the pad may be closer to the metal, such that the conductive via can also be closer, and thus, in a limited space, can be arranged more conductive via.

附图说明 BRIEF DESCRIPTION

[0006] 图1至图7显示本发明第一实施例的半导体组件的工艺的示意图; [0006] Figures 1 to 7 shows a schematic process of the semiconductor assembly according to a first embodiment of the present invention;

[0007] 图8显示本发明第二实施例的半导体组件的剖视示意图; [0007] FIG. 8 shows a second cross-sectional view of the semiconductor components of an embodiment of the present invention;

[0008] 图9显示本发明第三实施例的半导体组件的剖视示意图; [0008] Figure 9 shows a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention;

[0009] 图10显示本发明第四实施例的半导体组件的剖视示意图; [0009] Figure 10 shows a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention;

[0010] 图11显示本发明第四实施例的半导体组件的俯视示意图; [0010] FIG. 11 shows a schematic top view of a semiconductor device according to a fourth embodiment of the present invention;

[0011] 图12显示本发明第五实施例的半导体组件的剖视示意图; [0011] FIG. 12 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention;

[0012] 图13显示本发明第五实施例的半导体组件的俯视示意图; [0012] Figure 13 shows a top view of a semiconductor assembly according to a fifth embodiment of the present invention;

[0013] 图14显示本发明第六实施例的半导体组件的剖视示意图; [0013] Figure 14 shows a schematic cross-sectional view of the semiconductor device of the sixth embodiment of the present invention;

[0014] 图15显示本发明第六实施例的半导体组件的俯视示意图; [0014] Figure 15 shows a top view of a semiconductor component according to a sixth embodiment of the present invention;

[0015] 图16显示本发明第七实施例的半导体组件的剖视示意图; [0015] Figure 16 shows a schematic cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention;

[0016] 图17显示本发明第七实施例的半导体组件的俯视示意图;[0017] 图18显示本发明第八实施例的半导体组件的剖视示意图; [0016] Figure 17 shows a schematic top view of a seventh embodiment of the semiconductor device of the present invention; schematic cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention [0017] Figure 18 shows;

[0018] 图19显示本发明第八实施例的半导体组件的俯视示意图; [0018] Figure 19 shows a schematic top view of a semiconductor device according to the eighth embodiment of the present invention;

[0019] 图20显示本发明第九实施例的半导体组件的剖视示意图; [0019] Figure 20 shows a schematic cross-sectional view of a ninth embodiment of the semiconductor device of the embodiment of the present invention;

[0020] 图21显示本发明第九实施例的半导体组件的俯视示意图; [0020] FIG. 21 shows a schematic top view of a semiconductor device of a ninth embodiment of the present invention;

[0021] 图22显示本发明第十实施例的半导体组件的剖视示意图; [0021] FIG. 22 shows a schematic cross-sectional view of a semiconductor device according to a tenth embodiment of the present invention;

[0022] 图23显示本发明第十实施例的半导体组件的俯视示意图;及 [0022] Figure 23 shows a schematic top view of a semiconductor device of a tenth embodiment of the present invention; and

[0023] 图M显示本发明第十一实施例的具有半导体组件的封装结构的剖面示意图。 [0023] FIG M shows a schematic cross-sectional structure of a package having a semiconductor device of the eleventh embodiment of the present invention.

具体实施方式 Detailed ways

[0024] 参考图1至图7,显示本发明第一实施例的半导体组件的工艺的示意图。 [0024] Referring to FIG. 1 to FIG. 7, a schematic view of a display process of a semiconductor module according to the first embodiment of the present invention. 参考图1, 提供一基材本体10。 Referring to FIG 1, a substrate main body 10. 该基材本体10包括一第一表面101、一第二表面102及数个孔洞103。 The substrate body 10 includes a first surface 101, a second surface 102 and a plurality of holes 103. 在本实施例中,该基材本体10为一硅基材,这些孔洞103为盲孔,且开口于该第一表面101。 In the present embodiment, the substrate is a silicon substrate main body 10, the holes 103 of the blind bore and the opening to the first surface 101.

[0025] 参考图2,形成一绝缘材料11 (例如:聚亚酰胺(Polyimide,PI)、环氧树脂(Epoxy)、苯环丁烯(Benzocyclobutene,BCB)等非导电性高分子)于这些孔洞103的侧壁上,且定出数个中心槽。 [0025] Referring to FIG 2, an insulating material 11 is formed (e.g.: polyimide (Polyimide, PI), an epoxy resin (Epoxy), BCB (Benzocyclobutene, BCB) and other non-conductive polymer) in the holes on the side wall 103, and fix a plurality of central channels. 之后再填满一导电材料12 (例如铜金属)于这些中心槽内。 After then filled with a conductive material 12 (e.g. copper) in the center of these grooves. 之后, 翻转180度。 Thereafter, rotated 180 degrees.

[0026] 参考图3,以研磨及/或蚀刻方式移除部份该第二表面102以薄化该基材本体10, 使得这些孔洞103变成数个贯孔104,且这些导电材料12变成数个导通柱13。 [0026] Referring to FIG. 3, grinding and / or etching to remove portions of the second surface of the substrate 102 to thin the main body 10, so that the number of the holes 103 into the through hole 104, and the conductive material 12 becomes into a plurality of conductive via 13.

[0027] 参考图4,形成一第二保护层(Passivation Layer) 14于该第二表面102。 [0027] Referring to FIG 4, a second protective layer is formed (Passivation Layer) 14 to the second surface 102. 该第二保护层14为非导电性高分子材料,例如:聚亚酰胺(Polyimide,PI)、环氧树脂(Epoxy)、苯环丁烯(Benzocyclobutene,BCB)等。 The second protective layer 14 is non-conductive polymer material, for example: polyimide (Polyimide, PI), an epoxy resin (Epoxy), BCB (Benzocyclobutene, BCB) and the like. 在本实施例中,该第二保护层14为一感旋光性高分子材料,例如是苯环丁烯(Benzocyclobutene,BCB),且利用旋转涂布(SpinCoating)或喷雾涂布(Spray Coating)方式形成该第二保护层14。 In the present embodiment, the second protective layer 14 is a photosensitive polymer material, for example, benzocyclobutene (Benzocyclobutene, BCB), and spin coating (SpinCoating) or spray coating (Spray Coating) mode the second protective layer 14 is formed.

[0028] 参考图5,进行微影工艺,以形成至少一开口141,而显露这些导通柱13。 [0028] Referring to FIG 5, a lithography process to form at least one opening 141, which expose the conductive posts 13. 该开口141的尺寸及位置可由微影工艺中所使用的光罩所定义。 The size and position of the opening mask 141 may be used in the lithography process defined.

[0029] 参考图6,形成一金属层于该第二保护层14上及该开口141内,以接触这些导通柱13。 [0029] Referring to FIG 6, a metal layer 14 and 13 on the opening 141 to contact the conductive via such that the second protective layer is formed. 之后,进行蚀刻工艺,以形成数个金属垫(Metal Pad) 19,而制得本发明第一实施例的半导体组件1。 Thereafter, an etching process, to form a plurality of metal pads (Metal Pad) 19, and the semiconductor module 1 according to the first embodiment of the present invention was prepared. 这些金属垫19彼此互不连接,且这些金属垫19的尺寸及位置可由蚀刻工艺中所使用的光罩所定义。 The metal pads 19 are not connected to each other mutually, and the metal mask pad size and position 19 may be used in the etching process are defined. 较佳地,以俯视观之,每一金属垫19的面积会大于每一导通柱13的面积。 Preferably, in plan view, the area of ​​each metal pad 19 may be greater than the area of ​​each conductive post 13.

[0030] 参考图7,显示本发明第一实施例的半导体组件的俯视示意图。 [0030] Referring to Figure 7, it shows a schematic top view of a semiconductor device according to a first embodiment of the present invention. 这些金属垫19包括一第一金属垫16及数个原始金属垫15。 The metal pad 19 includes a first metal pad 16 and a plurality of metal pads 15 of the original. 这些原始金属垫15的外围为一圆柱状侧壁151。 The periphery of the original metal pads 15 is a cylindrical sidewall 151. 该第一金属垫16具有一第一弧状侧壁161及一第一参考侧壁162,其中该第一弧状侧壁161的曲率与该第一参考侧壁162的曲率不同。 The first pad 16 has a first arcuately shaped sidewall 161 and a sidewall 162 of the first reference, wherein the first arcuately shaped sidewall curvature different from the curvature of the first reference 161 sidewall 162.

[0031] 参考图6及7,分别显示本发明第一实施例的半导体组件的剖视及俯视示意图。 [0031] Referring to FIG. 6 and 7 respectively show a cross-sectional view of a semiconductor device according to a first embodiment and a schematic plan view of the present invention. 该半导体组件1包括一基材本体10、数个导通柱13、一绝缘材料11、一第二保护层14及数个金属垫19。 The assembly 1 comprises a semiconductor substrate main body 10, a plurality of conductive via 13, an insulating material 11, a second protective layer 14 and a plurality of metal pads 19.

[0032] 该基材本体10具有一第一表面101、一第二表面102及至少一贯孔104。 [0032] The base body 10 has a first surface 101, a second surface 102, and always at least 104 holes. 在本实施例中,该基材本体10为一硅基材,且该至少一贯孔104贯穿该基材本体10。 In the present embodiment, the substrate main body 10 is a silicon substrate, and the through hole 104 is always at least 10 of the substrate main body. 这些导通柱13位于该至少一贯孔104。 The conductive posts 13 located at least one through hole 104. 在本实施例中,这些导通柱13为实心柱状。 In the present embodiment, the conductive via 13 is a columnar solid.

[0033] 该绝缘材料11位于这些导通柱13及该至少一贯孔104的侧壁之间。 [0033] positioned between the insulating material 11 and the side wall of the through hole 104 at least these conductive posts 13. 该第二保护层14位于该第二表面102,且具有至少一开口141,以显露这些导通柱13。 The second protective layer 14 is located on the second surface 102, and having at least one opening 141 to expose the conductive posts 13. 这些金属垫19 位于该至少一开口141内,且接触及电性连接至这些导通柱13。 The metal pad 19 is located within the at least one opening 141, and contacts and is electrically connected to the conductive via 13.

[0034] 在本实施例中,该基材本体10具有数个贯孔104,每一导通柱13位于每一贯孔104内。 [0034] In the present embodiment, the substrate main body 10 having a plurality of through holes 104, each conductive post 13 is located in each through hole 104. 该第二保护层14具有数个开口141,每一开口141显露每一导通柱13。 The second protective layer 14 having a plurality of openings 141, each opening 141 of each conductive post 13 exposed. 每一金属垫19位于每一开口141内且电性连接至每一导通柱13。 Each metal pad 19 is located within each of the openings 141 and electrically connected to each of the conductive via 13. 这些金属垫19延伸至该第二保护层14上。 These metal pads 19 extend onto the second protective layer 14.

[0035] 这些金属垫19包括一第一金属垫16及数个原始金属垫15。 [0035] These metal pads 19 includes a first metal pad 16 and a plurality of metal pads 15 of the original. 这些原始金属垫15 的外围为一圆柱状侧壁151。 The periphery of the original metal pads 15 is a cylindrical sidewall 151. 该第一金属垫16具有至少一第一弧状侧壁161及至少一第一参考侧壁162,其中该第一弧状侧壁161的曲率与该第一参考侧壁162的曲率不同。 The first pad 16 having at least a first arcuately shaped sidewall 161, and sidewall 162 at least a first reference, wherein the first arcuately shaped sidewall curvature different from the curvature of the first reference 161 sidewall 162. 因此, 这些原始金属垫15以俯视观之为一个完整的圆形,该第一金属垫16以俯视观的并非一个完整的圆形。 Thus, the metal pads 15 to the original concept of a plan view of a complete circle, the first pad 16 is not a complete circle in plan View. 较佳地,该第一参考侧壁162的曲率小于该第一弧状侧壁161的曲率。 Preferably, the curvature of the first sidewall 162 is smaller than the reference curvature of the first arcuate side wall 161. 在本实施例中,该第一参考侧壁162为一平直面,其曲率为0。 In the present embodiment, the first sidewall 162 as a reference flat surface, the curvature is zero. 或者,该第一参考侧壁162也可以是弧状,但是其曲率小于该第一弧状侧壁161的曲率。 Alternatively, with reference to the first sidewall 162 may be arcuate, but arc of curvature less than the curvature of the first sidewall 161.

[0036] 该第一金属垫16具有一第一延伸部163及一第二延伸部164,该第一延伸部163 延伸至该第一弧状侧壁161,该第二延伸部164延伸至该第一参考侧壁162,该第二延伸部164的长度小于该第一延伸部163的长度。 [0036] The first pad 16 has a first extending portion 163 and a second extension portion 164, the first extension portion 163 extending to the first arcuately shaped sidewall 161, the second extending portion 164 extending to the first a reference side wall 162, extending the length of the second portion 164 is smaller than the length of the first extending portion 163.

[0037] 该第一金属垫16下的导通柱13具有一中心轴17a,该原始金属垫15下的导通柱13具有一中心轴17b,该中心轴17a与该中心轴17b间的距离为一第一间距P1,该二个中心轴17b间的距离为一第二间距P2。 [0037] The first pad 16 is a conductive post 13 having a central axis 17a, the pads 15 of the original metal conductive post 13 having a central axis 17b, the distance between the center axis 17a of the center axis 17b of the It is a first pitch P1, the distance between the two central axis 17b of a second pitch P2. 由于该第一金属垫16具有该第一参考侧壁162,且该第一参考侧壁162的曲率小于该第一弧状侧壁161的曲率,因此该第一间距P1可以小于第二间距P2。 Since the metal pad 16 having the first reference a first sidewall 162, and sidewall of the first reference 162 is smaller than the curvature of the curvature of the first arc-shaped side wall 161, so that the first pitch P1 may be smaller than the second pitch P2. 因此,这些导通柱13可以更靠近。 Therefore, these conductive posts 13 may be closer.

[0038] 参考图8,显示本发明第二实施例的半导体组件的剖视示意图。 [0038] Referring to Figure 8, a schematic cross-sectional view of a second embodiment of the semiconductor device of the present invention. 本实施例的半导体组件2与第一实施例的半导体组件1 (图6)大致相同,其中相同的组件赋予相同的编号。 The semiconductor assembly according to the present embodiment and the semiconductor assembly 2 (FIG. 6) is substantially the same as the first embodiment, wherein like components are given the same numbers. 本实施例与第一实施例的不同处在于,本实施例的半导体组件2更包括一第一保护层观。 Different from the embodiment of the present embodiment from the first embodiment in that the semiconductor device of Example 2 of the present embodiment further includes a first protective layer concept. 该第一保护层观与该第二保护层14相同。 The same concept of the first protective layer 14 and the second protective layer. 该第一保护层观位于该第一表面101,且具有至少一开口观1,以显露这些导通柱13。 The concept of a first protective layer positioned on the first surface 101, and a concept of having at least one opening to expose the conductive posts 13. 在本实施例中,部份这些金属垫19(例如金属垫四) 更位于该第一保护层28的开口281内且电性连接至这些导通柱13。 In the present embodiment, part of the metal pad 19 (e.g., four metal pad) is located closer to and electrically connected to the conductive post 13 within the opening 281 of the first protective layer 28. 位于该第一表面101 的这些金属垫四的结构与位于该第二表面102的这些金属垫19的结构对称且相等。 Located on the first surface 101 of the metal pad structure and four at the second surface 102 of the metal pad structure 19 is symmetrical and equal.

[0039] 参考图9,显示本发明第三实施例的半导体组件的剖视示意图。 [0039] Referring to Figure 9, a schematic cross-sectional view of a third embodiment of the semiconductor device of the present invention. 本实施例的半导体组件3与第一实施例的半导体组件1 (图6)大致相同,其中相同的组件赋予相同的编号。 The semiconductor component 3 of this embodiment is substantially the same as the semiconductor device 1 of the first embodiment (FIG. 6), wherein the same components are given the same numbers. 本实施例与第一实施例的不同处在于,本实施例的半导体组件3更包括一电路层38及数个导接组件39。 Different from the embodiment of the present embodiment from the first embodiment in that the semiconductor device of Example 3 of the present embodiment further includes a circuit layer 38 and a plurality of conductive contact assembly 39. 该电路层38位于该第一表面101,且电性连接至这些导通柱13。 The circuit layer 38 is located on the first surface 101, and electrically connected to the conductive via 13. 这些导接组件39位于该电路层38上。 The guide assembly 39 is then positioned on the circuit layer 38. 在本实施例中,每一导接组件39包括一焊垫391及一凸块392。 In the present embodiment, each of the guide assembly 39 includes a contact pad 391 and a bump 392. 要注意的是,该电路层38可以具有一重布层(Redistribution Layer,RDL),而可以重新分配这些导接组件39的位置。 It is noted that the circuit layer 38 may have a redistribution layer (Redistribution Layer, RDL), and can reassign the position of these guide components 39 are connected.

[0040] 参考图10及11,分别显示本发明第四实施例的半导体组件的剖视及俯视示意图。 [0040] with reference to FIGS. 10 and 11, a cross-sectional view and a plan view of a semiconductor assembly according to a fourth embodiment of the present invention are shown. 本实施例的半导体组件4与第一实施例的半导体组件1(图6)大致相同,其中相同的组件赋予相同的编号。 The semiconductor assembly according to the present embodiment is substantially the same as the semiconductor components 4 of the first embodiment 1 (FIG. 6), wherein the same components are given the same numbers. 本实施例与第一实施例的不同处在于,这些导通柱43为中空环柱状,且该半导体组件4更包括一内绝缘材料48。 Different from the first embodiment in that the embodiment of the present embodiment, the conductive via 43 is a hollow cylindrical ring, and the semiconductor device 4 further includes an insulating material 48. 该内绝缘材料48位于这些导通柱43内。 The insulating material 48 is located within the column 43 through the guide.

[0041] 参考图12及13,分别显示本发明第五实施例的半导体组件的剖视及俯视示意图。 [0041] with reference to FIGS. 12 and 13, a cross-sectional view and a plan view of a semiconductor assembly according to a fifth embodiment of the present invention are shown. 该半导体组件5包括一基材本体10、数个导通柱13、一绝缘材料11、一第二保护层14及数个金属垫19。 The assembly 5 comprises a semiconductor substrate main body 10, a plurality of conductive via 13, an insulating material 11, a second protective layer 14 and a plurality of metal pads 19.

[0042] 该基材本体10具有一第一贯孔10½及一第二贯孔104b。 [0042] The base body 10 has a first through hole and a second through hole 10½ 104b. 这些导通柱13包括一第一导通柱13a及一第二导通柱13b。 The conductive via 13 comprises a first conductive post 13a, and a second conductive via 13b. 该第一导通柱13a位于该第一贯孔10½内,该第二导通柱1¾位于该第二贯孔104b内。 The first conductive post 13a located first through bore 10½, the second conductive via 1¾ located within the second through hole 104b. 该绝缘材料11包括一第一绝缘材料Ila及一第二绝缘材料lib。 The insulating material 11 comprises a first insulating material and a second insulating material Ila lib. 该第一绝缘材料Ila位于该第一导通柱13a及该第一贯孔10½的侧壁之间, 该第二绝缘材料lib位于该第二导通柱1¾及该第二贯孔104b的侧壁之间。 Ila the first insulating material disposed between the first conductive post 13a and the first through hole 10½ sidewall, the second insulating material of the second side lib located 1¾ conductive pillar and the second through hole 104b of wall between. 该第二保护层14具有一第一开口141a及一第二开口141b,该第一开口141a显露该第一导通柱13a, 该第二开口141b显露该第二导通柱13b。 The second protective layer 14 having a first opening 141a and a second opening 141b, the first opening 141a exposes the first conductive post 13a, the second opening 141b exposes the second conductive column 13b.

[0043] 这些金属垫19包括一第一金属垫16及一第二金属垫16b。 [0043] These metal pads 19 includes a first metal pad 16 and a second metallic pad 16b. 该第一金属垫16位于该第一开口141a内且电性连接至该第一导通柱13a,该第一金属垫16具有至少一第一弧状侧壁161及至少一第一参考侧壁162,该第一弧状侧壁161的曲率与该第一参考侧壁162 的曲率不同。 The first pad 16 is positioned and electrically connected to the first conductive post 13a within the first opening 141a, the first pad 16 having at least a first arcuately shaped sidewall 161, and sidewall 162 at least a first reference the first sidewall 161 arc curvature the curvature of the first sidewall 162 different reference. 该第二金属垫16b位于该第二开口141b内且电性连接至该第二导通柱13b, 该第二金属垫16b具有至少一第二弧状侧壁161b及至少一第二参考侧壁162b,该第二弧状侧壁161b的曲率与该第二参考侧壁162b的曲率不同,且该第一参考侧壁162面对该第二参考侧壁162b。 The second metal pad 16b positioned within the second opening 141b and is electrically connected to the second conductive post 13b, 16b of the second metal pad having at least one second sidewall 161b and at least one arc second reference sidewall 162b the curvature of the second arcuate side wall 161b with the curvature of the second side wall 162b of different reference, the first reference and the second reference sidewall 162 facing sidewall 162b.

[0044] 该第一导通柱13a具有一第一中心轴18a,该第二导通柱1¾具有一第二中心轴18b,该第一中心轴18a及该第二中心轴18b的距离定义为一第三间距P3,该第三间距P3小于该第一间距P1 (图6),同时亦小于该第二间距P2 (图6),因此该第一导通柱13a及该第二导通柱13b可以更靠近。 [0044] The first conductive post 13a having a first central axis 18a, the second conductive post 1¾ having a second central axis 18b, the distance defining a first central axis and second central axis 18a to 18b a third pitch P3, the third pitch P3 smaller than the first pitch P1 (FIG. 6), but also smaller than the second pitch P2 (FIG. 6), so that the first conductive post 13a and the second conductive via 13b may be closer.

[0045] 在本实施例中,该第一弧状侧壁161定义出一第一半径T1,该第二弧状侧壁161b 定义出一第二半径r2,该第三间距P3小于该第一半径巧及该第二半径r2之和。 [0045] In the present embodiment, the first arcuate side wall 161 defines a first radius Tl, the second arcuate sidewall 161b define a second radius r2, the third pitch P3 smaller than the first radius Qiao and the sum of the second radius r2. 亦即: that is:

[0046] P3 < r!+r2 [0046] P3 <r! + R2

[0047] 参考图14及15,分别显示本发明第六实施例的半导体组件的剖视及俯视示意图。 [0047] with reference to FIGS. 14 and 15, a cross-sectional view and a plan view of a semiconductor component according to a sixth embodiment of the present invention are shown. 本实施例的半导体组件6与第五实施例的半导体组件5 (图12及1¾大致相同,其中相同的组件赋予相同的编号。本实施例与第五实施例的不同处在于,该第一贯孔104a、该第二贯孔104b、该第一绝缘材料Ila及该第二绝缘材料lib的结构。在本实施例中,该第一贯孔10½及该第二贯孔104b并非圆柱状,而是具有一弧状侧壁及一参考侧壁。因此,该第一绝缘材料Ila具有至少一第一弧状侧壁Illa及至少一第一参考侧壁112a,该第一绝缘材料Ila的第一参考侧壁11¾对应该第一金属垫16的第一参考侧壁162。该第二绝缘材料lib具有至少一第二弧状侧壁Illb及至少一第二参考侧壁112b,该第二绝缘材料lib的第二参考侧壁112b对应该第二金属垫16b的第二参考侧壁162b。 Different from the semiconductor device according to the present embodiment the semiconductor device 5 and 6 of the fifth embodiment (FIGS. 12 and 1¾ substantially the same, wherein the same components are given the same numbers. Example of the fifth embodiment is characterized in the present embodiment, the first through structure holes 104a, 104b of the second through hole, the first insulating material and said second insulating material Ila lib in the present embodiment, the first through hole 10½ and the second through hole 104b is not a cylindrical shape, and arcuate sidewall having a sidewall and a reference. Thus, the first insulating material having at least a first arc Ila Illa sidewall and at least one reference first sidewall 112a, a first reference side of the first insulating material Ila 11¾ metal wall corresponding to the first pad 162. the first side wall 16 with reference to the second insulating material having at least one second arc lib Illb sidewall and at least one second reference sidewall 112b, a first of the second insulating material lib second reference sidewall 112b corresponding to the second metal pad to a second reference side wall 162b 16b.

[0048] 该第一中心轴18a及该第二中心轴18b的距离定义为一第四间距P4,该第四间距P4小于该第三间距&(图13),因此该第一导通柱13a及该第二导通柱1¾可以更靠近。 [0048] 18a of the first central axis and the second distance is defined as a center axis 18b of the fourth pitch P4, the fourth pitch P4 is smaller than the third spacing & (FIG. 13), so that the first conductive post 13a and the second conductive post 1¾ may be closer.

[0049] 参考图16及17,分别显示本发明第七实施例的半导体组件的剖视及俯视示意图。 [0049] with reference to FIGS. 16 and 17, cross-sectional view and a plan view of a semiconductor component according to a seventh embodiment of the present invention are shown. 本实施例的半导体组件7与第五实施例的半导体组件5 (图12及1¾大致相同,其中相同的组件赋予相同的编号。本实施例与第五实施例的不同处在于,该第一导通柱13a及该第二导通柱13b位于同一贯孔704内。 The semiconductor assembly 7 of the present embodiment and the semiconductor assembly 5 of the fifth embodiment (FIGS. 12 and 1¾ substantially the same, wherein the same components are given the same numbers. Example of the fifth embodiment is different from that of the present embodiment, the first guide pillars 13a and 13b of the second conductive via 704 are in the same through hole.

[0050] 参考图18及19,分别显示本发明第八实施例的半导体组件的剖视及俯视示意图。 [0050] with reference to FIGS. 18 and 19, cross-sectional view and a plan view of a semiconductor assembly according to an eighth embodiment of the present invention are shown. 本实施例的半导体组件8与第七实施例的半导体组件7 (图16及17)大致相同,其中相同的组件赋予相同的编号。 The semiconductor assembly according to the present embodiment and the seventh embodiment of the semiconductor device 8 of Example 7 (FIGS. 16 and 17) is substantially the same, wherein the same components are given the same numbers. 本实施例与第七实施例的不同处在于,在第七实施例中,该第二保护层14的每一开口141a,141b显露每一导通柱13a,13b。 Example differences from the seventh embodiment in that the present embodiment, in the seventh embodiment, the second protective layer 14 of each of the openings 141a, 141b expose each conductive post 13a, 13b. 然而,在本实施例中,该第二保护层14的开口141c的面积大于该至少二个导通柱13a,13b的截面积之和,以显露该至少二个导通柱13a,13b。 However, in the present embodiment, the area of ​​the opening 141c of the second protective layer 14 is greater than the at least two conductive posts 13a, 13b and the cross-sectional area, to reveal the at least two conductive posts 13a, 13b. 较佳地,该开口141c的面积略小于该贯孔704的面积。 Preferably, the area of ​​the opening 141c is slightly smaller than the area of ​​the through hole 704. 因此,这些导通柱13a,13b之间不会有该第二保护层14。 Therefore, these conductive posts 13a, will not have the protective layer 14 between the second 13b.

[0051] 参考图20及21,分别显示本发明第九实施例的半导体组件的剖视及俯视示意图。 [0051] with reference to FIGS. 20 and 21, cross-sectional view and a plan view of a semiconductor component according to a ninth embodiment of the present invention are shown. 本实施例的半导体组件9与第一实施例的半导体组件1(图6)大致相同,其中相同的组件赋予相同的编号。 The semiconductor assembly according to the present embodiment of the semiconductor assembly 9 of the first embodiment 1 (FIG. 6) is substantially the same, wherein the same components are given the same numbers. 本实施例与第一实施例的不同处在于,在本实施例中,部分这些金属垫19 (即这些金属垫96)具有数个第一弧状侧壁961及数个第一参考侧壁962。 Different from the embodiment of the present embodiment from the first embodiment in that, in the present embodiment, the portion of the metal pad 19 (i.e., the metal pad 96) having a first plurality of arc-shaped side wall 961 and a plurality of side wall 962 of the first reference. 因此这些导通柱13可以更靠近。 Thus these conductive posts 13 may be closer. 藉此,在有限空间内,可以排列较多的导通柱13。 Whereby, in a limited space, it can be arranged more conductive via 13.

[0052] 参考图22及23,分别显示本发明第十实施例的半导体组件的剖视及俯视示意图。 [0052] with reference to FIGS. 22 and 23, a cross-sectional view and a plan view of a semiconductor assembly according to a tenth embodiment of the present invention are shown. 本实施例的半导体组件9a与第九实施例的半导体组件9(图21)大致相同,其中相同的组件赋予相同的编号。 The semiconductor assembly according to the present embodiment and the ninth embodiment of the semiconductor device 9a in Example 9 (FIG. 21) is substantially the same, wherein the same components are given the same numbers. 本实施例与第九实施例的不同处在于,在本实施例中,这些导通柱13 位于同一贯孔904内,且该第二保护层14的开口141d的面积大于这些个导通柱13的截面积之和,以显露这些导通柱13。 Different from the embodiment of the present embodiment and the ninth embodiment in that, in the present embodiment, the conductive posts 13 through holes 904 located within the same, and the area of ​​the opening 141d of the second protective layer 14 is greater than those of guide pillars 13 the cross-sectional area and to expose the conductive posts 13. 因此,部分这些金属垫19 (即这些金属垫96)位于这些导通柱13及该绝缘材料11上,且未接触该第二保护层14。 Thus, part of the metal pad 19 (i.e., the metal pads 96) located on the conductive post 13 and the insulating material 11, and not in contact with the second protective layer 14.

[0053] 参考图24,显示本发明第十一实施例的具有半导体组件的封装结构的剖面示意图。 [0053] Referring to Figure 24, a cross-sectional schematic view showing a semiconductor device having a package structure eleventh embodiment of the present invention. 该封装结构9b包括一半导体组件1、一芯片90及一底胶(Underfill) 92。 The package 1 comprises 9b, a chip 90 and a primer a semiconductor element (Underfill) 92. 在本实施例中,该半导体组件1为本发明第一实施例的半导体组件1 (图6)。 In the present embodiment, the semiconductor element 1 of the present embodiment of the semiconductor device 1 of the first embodiment (FIG. 6) the invention. 然而,在其它实施例中,该半导体组件1可置换成本发明第二至十实施例的半导体组件。 However, in other embodiments, the semiconductor element 1 may be replaced with a semiconductor assembly cost ten second embodiment of the invention embodiment. 该芯片90位于该半导体组件1上。 The chip 90 is positioned on the semiconductor element 1. 该芯片90具有数个导体组件91 (例如焊球),以接触且电性连接这些金属垫19。 The chip 90 has a plurality of conductor assembly 91 (e.g., solder balls), and is electrically connected to the contact pads 19 of these metals. 该底胶91位于该芯片90及该半导体组件1之间,以包覆且保护这些导体组件91。 The primer 91 is located in the chip 90 and between the semiconductor element 1, to cover and protect the conductor assemblies 91.

[0054] 惟上述实施例仅为说明本发明的原理及其功效,而非用以限制本发明。 [0054] However the above-described embodiments are illustrative only of the principles and effect of the present invention, not to limit the present invention. 因此,习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。 Accordingly, those conventional in this art to the embodiments described above modifications and variations still off the spirit of the present invention. 本发明的权利范围应如权利要求书所列。 Scope of the present invention shall be set forth in claim book.

Claims (16)

1. 一种具有半导体组件的封装结构,包括: 一半导体组件,包括:一基材本体,具有一第一表面、一第二表面及至少一贯孔; 数个导通柱,位于该至少一贯孔内; 一绝缘材料,位于这些导通柱及该至少一贯孔的侧壁之间; 一第二保护层,位于该第二表面,且具有至少一开口,以显露这些导通柱;及数个金属垫,位于该至少一开口内且电性连接至这些导通柱,这些金属垫包括至少一第一金属垫,该第一金属垫具有至少一第一弧状侧壁及至少一第一参考侧壁,其中该第一弧状侧壁的曲率与该第一参考侧壁的曲率不同;一芯片,位于该半导体组件上,该芯片具有数个导体组件,以电性连接这些金属垫;及一底胶,位于该芯片及该半导体组件之间,以包覆这些导体组件。 A package structure having a semiconductor device, comprising: a semiconductor element, comprising: a substrate body having a first surface, a second surface and at least one through aperture; a plurality of conducting posts, at least one through hole located inside; between an insulating material, which conductive via is located at least one through aperture and said side walls; a second protective layer disposed on the second surface, and having at least one opening to expose the conductive posts; and a plurality of a metal pad, is located within the at least one opening and electrically connected to the conductive via, the metal pad comprises at least a first metal pad, the first pad having a first arcuate side wall and at least a first reference side of at least one wall, wherein the first curvature of the arcuate curvature of the first sidewall with the sidewall of a different reference; a chip on the semiconductor element, the chip has a plurality of conductor assembly electrically connected to the metal pads; and a bottom glue, located between the chip and the semiconductor element, to cover the conductor assembly.
2.如权利要求1的封装结构,其中该基材本体为一硅基材。 2. The package structure as claimed in claim 1, wherein the substrate body is a silicon substrate.
3.如权利要求1的封装结构,其中这些导通柱为实心柱状。 3. The packaging structure as claimed in claim 1, wherein the column is a solid cylindrical conductive.
4.如权利要求1的封装结构,其中该基材本体具有一第一贯孔及一第二贯孔,这些导通柱包括一第一导通柱及一第二导通柱,该第一导通柱位于该第一贯孔内,该第二导通柱位于该第二贯孔内,该绝缘材料包括一第一绝缘材料及一第二绝缘材料,该第一绝缘材料位于该第一导通柱及该第一贯孔的侧壁之间,该第二绝缘材料位于该第二导通柱及该第二贯孔的侧壁之间,该第二保护层具有一第一开口及一第二开口,该第一开口显露该第一导通柱,该第二开口显露该第二导通柱,这些金属垫更包括至少一第二金属垫,该第一金属垫位于该第一开口内且电性连接至该第一导通柱,该第二金属垫位于该第二开口内且电性连接至该第二导通柱,该第二金属垫具有至少一第二弧状侧壁及至少一第二参考侧壁,该第二弧状侧壁的曲率与该第二参考侧壁的曲率不同,且 The package structure as claimed in claim 1, the first, wherein the substrate body has a first through hole and a second through hole, the conductive via comprising a first conductive via and a second conductive via, conducting the first through hole positioned column, the second conductive via the second through hole is located, the insulating material comprising a first insulating material and a second insulating material, the first insulating material located between the first between the sidewall of the via post and the first through hole of the second insulating material located between the sidewall of the second conductive via and the second through hole of the second protective layer having a first opening and a second opening, the first opening exposes the first conductive pillars, the second opening exposes the second conductive via, the metal pads further comprises at least one second metal pad, the first pad is located in the first within the opening and electrically connected to the first conductive pillars, the second metal pad is located and electrically connected to the second conductive pillar within the second opening, the second metal pad having at least one second arcuate sidewall and at least one second reference sidewall, the arcuate curvature of the second curvature of the second side wall and the side walls different from the reference, and 第一参考侧壁面对该第二参考侧壁。 Referring first sidewall facing the second sidewall reference.
5 如权利要求4的封装结构,其中该第一导通柱的中心轴及该第二导通柱的中心轴间的距离定义为一间距,该第一弧状侧壁定义出一第一半径,该第二弧状侧壁定义出一第二半径,该间距小于该第一半径及该第二半径之和。 5 The package structure as claimed in claim 4, wherein the distance between the central axes of the first conductive pillar and the second conductive pillar is defined as a distance, the first sidewall defines a first arc radius, the second sidewall defines a second arc radius, the pitch is smaller than the first radius and the second radius and.
6.如权利要求4的封装结构,其中该第一绝缘材料具有至少一第一弧状侧壁及至少一第一参考侧壁,该第一绝缘材料的第一参考侧壁对应该第一金属垫的第一参考侧壁,该第二绝缘材料具有至少一第二弧状侧壁及至少一第二参考侧壁,该第二绝缘材料的第二参考侧壁对应该第二金属垫的第二参考侧壁。 6. The package structure as claimed in claim 4, wherein the first insulating material having at least a first arcuately shaped side wall and at least one sidewall of the first reference, with reference to the first sidewall of the first insulating material corresponding to the first metal pad Referring first sidewall, the second insulating material having at least one side wall and at least a second arc second reference sidewall, a second sidewall of the second reference for the second insulating material of the second metal pad reference should sidewall.
7.如权利要求1的封装结构,其中该基材本体具有数个贯孔,每一导通柱位于每一贯孔内,该第二保护层具有数个开口,每一开口显露每一导通柱,每一金属垫位于每一开口内且电性连接至每一导通柱。 7. The package structure as claimed in claim 1, wherein the substrate body has a plurality of through holes, each located on each conductive via hole consistent, the second protective layer having a plurality of openings, each opening of each exposed conductive column, each metal pad is located and electrically connected to each conductive via in each opening.
8.如权利要求1的封装结构,其中这些金属垫延伸至该第二保护层上。 8. The packaging structure as claimed in claim 1, wherein the metal pad extends onto the second protective layer.
9.如权利要求1的封装结构,其中至少二个导通柱位于一个贯孔内。 9. The packaging structure as claimed in claim 1, wherein the at least two conducting posts in a holding space.
10.如权利要求9的封装结构,其中该第二保护层具有数个开口,且每一开口显露每一导通柱。 10. The package of claim 9, wherein the second protective layer having a plurality of openings, each opening and each exposed conductive via.
11.如权利要求9的封装结构,其中该第二保护层的开口的面积大于该至少二个导通柱的截面积之和,以显露该至少二个导通柱。 11. The package of claim 9, wherein the area of ​​the opening of the second protective layer is greater than the cross-sectional area of ​​the at least two conductive column, and to expose the at least two conductive posts.
12.如权利要求11的封装结构,其中部分这些金属垫位于该绝缘材料上,且未接触该第二保护层。 12. The package of claim 11, wherein the metal part of the pad is positioned on the insulating material, and not in contact with the second protective layer.
13.如权利要求1的封装结构,其中部分这些金属垫具有数个该第一弧状侧壁及数个该第一参考侧壁。 13. The package of claim 1, wherein the metal part of the first pad has a plurality of arc-shaped side wall and a plurality of the first reference sidewall.
14.如权利要求1的封装结构,其中该半导体组件更包括: 一电路层,位于该第一表面,且电性连接至这些导通柱;及数个导接组件,位于该电路层上。 14. The package of claim 1, wherein the semiconductor device further comprising: a circuit layer, located on the first surface, and electrically connected to the conductive via; and a plurality of conductive connection assembly disposed on the circuit layer.
15.如权利要求1的封装结构,其中该第一参考侧壁为一平直面。 15. The package of claim 1, wherein the first sidewall is a reference flat surface.
16.如权利要求1的封装结构,其中该半导体组件更包括一内绝缘材料,这些导通柱为中空环柱状,该内绝缘材料位于这些导通柱内。 16. The package of claim 1, wherein the semiconductor device further comprises an insulating material, the conductive via has a hollow cylindrical ring, the inner insulating material positioned within the conductive via.
CN201010571504.0A 2010-11-24 2010-11-24 Semiconductor device having a package structure CN102479765B (en)

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