CN102468835A - Differential sensing and silicon crystal perforating hole time sequence control structure of three-dimensional chip - Google Patents
Differential sensing and silicon crystal perforating hole time sequence control structure of three-dimensional chip Download PDFInfo
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- CN102468835A CN102468835A CN2010105366976A CN201010536697A CN102468835A CN 102468835 A CN102468835 A CN 102468835A CN 2010105366976 A CN2010105366976 A CN 2010105366976A CN 201010536697 A CN201010536697 A CN 201010536697A CN 102468835 A CN102468835 A CN 102468835A
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Abstract
The invention relates a differential sensing and silicon crystal perforating hole time sequence control structure of a three-dimensional chip, comprising a first chip layer of a stack component , wherein the first chip layer includes a detection circuit and a relative high-capacity driver which is horizontally coupled to the detection circuit, a sensing circuit which is coupled to the detection circuit via a horizontal lead, a first differential signal driver which is horizontally coupled to the sensing circuit in a first chip layer, and an Nth chip layer of the stack component , wherein the Nth chip layer includes an Nth relative high-capacity driver and an Nth differential signal driver formed on the Nth chip layer, wherein the Nth relative high-capacity driver penetrates a vertical relative low-load silicon crystal perforating hole and (N-2) relative high-load silicon crystal perforating holes as virtual loads to be vertically coupled to a first relative high-capacity driver, and the Nth differential signal driver penetrates a pair of relative low-load silicon crystal perforating holes and (N-2) pairs of relative high-load silicon crystal perforating holes to be vertically coupled to the first differential signal driver.
Description
[technical field]
The present invention system is about a kind of three-dimensional stack chip assembly, and special system is relevant for a kind of differential sensing and silicon wafer perforation SECO structure of three-dimensional chip.
[background technology]
Recently portable electronic device, for example mobile phone and non-volatility semiconductor memory media (for example integrated circuit memory card), minification designs or makes, and the minimizing of newly-increased demand desire is used for the number of parts of equipment and medium and dwindles its size.Therefore, in semi-conductor industry, the encapsulation technology of integrated circuit has advanced to and has met miniaturization and the demand of following reliability.For example, the demand of miniaturization and cause the accelerated development of encapsulation technology makes it have the similar size with the semiconductor chip.Moreover then the importance of reliability on encapsulation technology is to promote the then efficient of processing procedure, and after then processing procedure is accomplished, improves machinery and electrical reliability.Therefore, existing considerable work is to develop packaged semiconductor efficiently.The encapsulation that meets the demand comprises: have the rough chip size packages (CSP) that equals the package size of semiconductor chip; Have multiple semiconductor chip to include heavy Chip Packaging more than the single encapsulation in, and multiple packaging body storehouse and the storehouse that is incorporated into a monolithic structure dress encapsulate.
Along with the development of technology, the increase of the relative required storage volume of response memory, and the semiconductor subassembly (multiple chip assembly) of proposition storehouse kenel, it has the semiconductor integrated circuit chip storehouse together.In other words; It is the storehouse kenel semiconductor subassembly that provides at least two semiconductor integrated circuit assembly storehouses to be formed; Each has specification and comprises the semiconductor IC chip; Wherein each semiconductor integrated circuit assembly comprises that a conductor passes wherein, and the semiconductor integrated circuit assembly electrically connects by conductor, and above-mentioned specification value comprises that the size of the superiors or orlop semiconductor integrated circuit assembly is maximum or minimum.Therefore, storehouse kenel semiconductor subassembly has a plurality of chip stacks in a vertical direction.In storehouse kenel semiconductor subassembly, chip system is electrically connected through for example passing the connector (plugs) of chip.Therefore, selecting the storehouse memory chip of a suitable same structure is a important work.If a storehouse kenel semiconductor subassembly is accomplished make, chip can make only normal chip can be selected and storehouse individually by operational testing.
A kind ofly provide technology connected vertically to be called silicon wafer perforation (TSV), it has become a promising solution of three-dimensional storehouse assembly.In the above-mentioned technology, vertically connect linear system and pass wafer and form, be able between the stack chip link up and make.Relevant paper can be " utilizing the three-dimensional DDR3 DRAM of 8 kilomegabits of silicon wafer puncturing technique " (VOL.45, NO.1, JANUARY 2010 for IEEE, JOURNAL OF SOLID-STATECIRCUITS) with reference to title.In this piece paper, the proposition system with silicon wafer perforation Three-Dimensional Dynamic random access memory is in order to overcome the restriction of traditional modular approach.It also discloses how to design this structure and data path.It also discloses silicon wafer perforation connectivity inspection and the restorative procedure that comprises 3-D technology, and power noise reduction method.The silicon wafer perforation can see through simple mode and after dispatching from the factory, form, and therefore need not during normal processing procedure, to add in addition special processing procedure and integrates.Chip identification system normally distributes.
In the data communication system, typically be to utilize one in the transmission assembly of operation under the first frequency and the independent receiving unit of an operation under second frequency.Usually, transmission assembly and receiving unit have a frequency speed difference.The data that this frequency speed difference causes the recipient to see coming in than expection sooner or slower, be called " timing off-set " here.For the packet basis communication system, if package during possible timing off-set maximum less than a symbol during, then the frequency speed difference can be left in the basket.The U.S. the 7th, 003,056 patent discloses a kind of symbol sequential and follows the trail of and method, and it is the timing off-set that utilizes sequential to follow the trail of to come owing to the difference on the frequency of transmission frequency and receive frequency with calibration.Follow the trail of by sequential, the correlation of three continuous samplings can utilize the reception signal to calculate with replying symbol, calculates its summation then.In addition, the static random stored memory is widely used in the application that speed has importance, and for example high-speed cache typically is to place processor or the central processing unit that is bordering on personal computer most.Yet the sequential of its internal circuit possibly seriously influence the speed and the efficient of static random stored memory.For example, comprise appreciable read/write cycles during the bit lines charged, and sensing amplifier uses the overall power consumption contribution for the static random stored memory showing.In the static random stored memory design in early days, read/write cycles system is based on an outside pulse signal that produces.Another known techniques is exposed in the U.S.'s the 7th, 003,056 patent, and it comprises that self-timing circuit is to reduce the write cycle of semiconductor internal memory.One virtual memory structure cell has identical sequential demand with as the function structure cell, and the relevant preferred circuit that writes logic add to memory subassembly.The virtual structure cell that writes receives identical controlling signal in order to writing the function structure cell of data to this internal memory, and sends one after finishing and accomplish signal when writing access, causes terminate write cycle.This circuit and method allow time write cycle to be reduced to the smallest effective value, are independent of the read cycle time.This potential integrated operation speed that has increased memory subassembly.
The present invention provides a kind of differential sensing of three-dimensional storehouse assembly and silicon wafer to bore a hole SECO to improve loading problem, shown in figure one.Time delay by loading problem caused is even worse in more chip layer.Therefore, the present invention one novel three-dimensional chip sensing and sequential control are provided method to address this problem.
[summary of the invention]
One of the present invention viewpoint is to provide a kind of differential sensing of three dimensional integrated circuits and the method and the structure of silicon wafer perforation SECO.
The differential sensing of three dimensional integrated circuits and silicon wafer perforation SECO structure comprise a relative ability driver (buffer), and a dummy load couples relative ability driver (buffer) and dodges the control signal to transmit a sequential, and a testing circuit couples dummy load.One differential signal produces structure and couples a relative capabilities driver (buffer) to produce a differential signal.One sensing circuit couples differential signal and produces structure.When an active signal reached to a trigger point, testing circuit started sensing circuit.
Differential signal produces structure and comprises that a pair of high capacity structure couples a relative capabilities driver, and a reverser is disposed at this between one of relative high capacity structure and the relative capabilities driver.Should comprise a pair of silicon wafer perforation to relative high capacity structure.Dummy load comprises silicon wafer perforation.
The transmission speed of ability driver is greater than the transmission speed of relative capabilities driver relatively.In one embodiment, the transmission speed of ability driver is the transmission speed of the doubly relative capabilities driver of x relatively.Sensing circuit comprises a sensing amplifier, a comparator or an operational amplifier.
Under the framework of above-mentioned three-dimensional viewpoint; A kind of differential sensing and silicon wafer perforation SECO structure with storehouse assembly of plural layer; Comprise: first chip layer of a pile stack component comprises that a testing circuit and a relative ability driver level couple testing circuit.One sensing circuit couples testing circuit by a horizontal wire.One first differential signal driver, level couples sensing circuit in first chip layer.The N chip layer of a pile stack component; Comprise that a relative ability driver of a N and a N differential signal driver are formed on the N chip layer; N is the natural number greater than 1; Wherein the relative ability driver of N system see through a vertically opposite low load silicon wafer perforation and (N-2) relatively the high capacity silicon wafer bore a hole as dummy load and the vertical first relative ability driver that couples; Low relatively load silicon wafer perforation with (N-2) relatively high capacity silicon wafer perforation system pass the storehouse assembly from N chip layer to the first chip layer; Wherein low relatively load silicon wafer perforation with (N-2) relatively the perforation of high capacity silicon wafer be formed at one and share in the structure; Wherein N differential signal driver system bores a hole and the vertical first differential signal driver that couples to relative high capacity silicon wafer with (N-2) through a pair of low relatively load silicon wafer perforation; Should to low relatively load silicon wafer perforation with should (N-2) relatively high capacity silicon wafer perforation system pass the storehouse assembly from N layer to ground floor, each low relatively load silicon wafer perforation system is formed between first and second chip layer, each relative high capacity silicon wafer perforation system is formed between arbitrary adjacent two chip layer of storehouse assembly; When an active signal reached to a trigger point, testing circuit started sensing circuit by this.
[description of drawings]
Said modules, and further feature of the present invention and advantage, by read hold within the execution mode and graphic after, will be more obvious:
Fig. 1 demonstration is asked figure according to the load of known techniques.
Fig. 2 shows the differential sensing of the three-dimensional chip according to the present invention and the functional block diagram of silicon wafer perforation SECO structure.
Fig. 3 shows the differential sensing of the three-dimensional chip according to the present invention and the functional block diagram of silicon wafer perforation SECO structure.
Fig. 4 shows that the differential sensing of the three-dimensional chip according to the present invention and the graphics of silicon wafer perforation SECO structure indicate intention.
Among the figure:
100,300 drivers or buffer
101 first high capacity structures
200,400 reversers
The 210a second high capacity structure (silicon wafer perforation)
210b the 3rd high capacity structure (silicon wafer perforation)
220,420 sensing circuits
310 virtual silicon wafer perforation (dummy load)
315 testing circuits
405a, the relative low level driver of 405b (buffer)
410a, the perforation of 410b silicon wafer
The relative ability driver of 300L1
The C1 lead
The relative ability driver of 300LN N
The 422L1 first differential signal driver
422LN N differential signal driver
[embodiment]
The present invention will cooperate its preferred embodiment and the diagram of enclosing to be specified in down.Should the person of understanding be the usefulness that the preferred embodiment of all is merely illustration among the present invention, be not in order to restriction.Therefore the preferred embodiment in literary composition, the present invention also can be widely used among other embodiment.And the present invention is not limited to any embodiment, should be with the claim of enclosing and equivalent fields thereof and decide.
Present invention is directed to the differential sensing and the silicon wafer perforation SECO structure of three-dimensional chip, it can be introduced in embedded volatility or non-voltile memory.In a preferred embodiment, as shown in Figure 2, the present invention discloses a differential sensing structure, and it comprises a driver or buffer 100, couples one first high capacity structure 101.The input of one signal couples the other end of driver or buffer 100, and a signal output electric property connects the first high capacity structure, and it can see through silicon wafer perforation 101 and form.This structure more comprises one second high capacity structure (silicon wafer perforation) 210a and the 3rd high capacity structure (silicon wafer perforation) 210b, and the two considers above-mentioned second silicon wafer perforation 210a and the 3rd silicon wafer perforation 210b to be the configured in parallel structure according to design.Can also utilize other structural arrangements.The signal input couples second silicon wafer perforation 210a, and a reverser 200 is disposed between signal input and the 3rd silicon wafer perforation 210b.Next, a sensing circuit 220 couples second silicon wafer perforation 210a and the 3rd silicon wafer perforation 210b respectively.Signal output couples the other end of sensing circuit 220.Also show the VDD sequential chart in the differential sensing structure of Fig. 2 respectively.For first silicon wafer perforation 101, its trigger point (trigger point) is the half the of VDD, if the trigger point horizontal-extending, then is time shaft and crosspoint from A point vertical extent line readout time to reach the A point of VDD sequential chart.Similarly, for second silicon wafer perforation 210a and the 3rd silicon wafer perforation 210b, its sensing boundary is higher than the trigger point, that is is higher than 1/2nd VDD.Therefore, read on VDD sequential line, it will be between RCA and VDD sequential line.
With reference to figure 3, it shows one of the present invention preferred embodiment.It shows the silicon wafer perforation SECO of different sensings, and this structure comprises that a relative high levels driver or buffer 300 couple one and have virtual silicon wafer perforation (dummy load) 310 of high capacity.One sequential is dodged the other end that control signal (timing strobe signal) couples driver or buffer 300, and a testing circuit 315 electrically connects virtual silicon wafer perforation (dummy load) 310.This differential signal structure comprises a pair of high capacity structure; In an example; This can be formed by a pair of silicon wafer perforation 410a and silicon wafer perforation 410b the high capacity structure, and this sees through relative low level driver (buffer) 405a and 405b respectively and couple the signal input silicon wafer perforation 410a and silicon wafer perforation 410b.It should be noted that a reverser 400 is disposed between signal input and relative low level driver (buffer) 405b.Next, a sensing circuit 420 couple respectively this to the high capacity structure the two.Signal output couples the other end of sensing circuit 420.Aforementioned testing circuit 315 couples sensing circuit 420.Preferably, sequential sudden strain of a muscle control signal is almost identical with the signal input.In a preferred embodiment, high levels driver (buffer) 300 has several times of efficiency in relative low level driver (buffer) 405a or 405b relatively.
Please refer to Fig. 3, it then illustrates the SECO of silicon wafer perforation differential sensing.Initial step is that input timing dodges the control signal to relative high levels driver (buffer).True signal inputs to relative low level driver (buffer) 405a and 405b.Signal through reverser 400 will also postpone from the initial input signal is reverse, and the reverse signal waveform can be found out from the upper right portion of Fig. 3.Therefore, the signal of arrival high capacity structure 410b will be reversed via reverser 400.On the contrary, the signal that does not arrive another high capacity structure 410a through reverser 400 is still kept identical.This moment, sensing circuit 420 was normally to cut out.Because load is heavy, therefore by the differential signal transmission.When the difference of differential signal greater than 100mV (0.1 volt), next open sensing circuit 420, therefore determine that digital state is 1 or 0.
The difference system of 100mV (0.1 volt) is by the circuit decision, and it has dummy load 310 and couples testing circuit 315.The VDD sequential chart can with reference to second with the diagram of Fig. 3.This diagram is meaning signal and is passing dummy load 310.This is shown in the right of Fig. 2 and Fig. 3 to high capacity structure 410a and the output of 410b in the VDD sequential chart.One virtual signal is duplicated to transmit a well-known active signal by 310 of dummy load, and the driver 300 of number (x) times ability is introduced to dummy load 310.Suppose that VDD is 1.8 volts, then the trigger point is the half the of VDD, promptly 0.9 volt.As a result, when the difference of differential signal greater than 100mV (0.1 volt), the signal of dummy load reaches to the trigger point, so the value of x is 9.Its transmission speed that is meaning dummy load 310 is bigger to the differential signal structure than this.Similarly, if VDD is 1 volt, then the x value is 5.
When the active signal, in the step 2 of figure three, reach to the trigger point, testing circuit 315 should be opened sensing circuit 420 as early as possible.In a preferred embodiment, testing circuit 315 is to form by at least one reverser, produces surging to detect, in the step 3 of figure three.One of most important person is that reverser need accord with should this sensing sequential.Sensing circuit 420 can be a sensing amplifier or a comparator or an operational amplifier.At last, signal is exported from sensing circuit, in the step 4 of figure three.Loading problem can be easily overcome by silicon wafer perforation SECO and differential sensing structure.
Fig. 4 shows the present invention's three-dimensional structure, and three-dimensional storehouse assembly comprises a plurality of stack chip layers, and it comprises that an individual chip (not icon) is positioned at each chip layer.First chip layer (ground floor) of three-dimensional storehouse assembly comprises that a testing circuit 315 is positioned within the presumptive area, a relative ability driver 300L1 coupled in parallel testing circuit 315.One sensing circuit 420 is disposed at one of first chip layer presumptive area, and couples testing circuit 315 by a horizontal wire C1.One differential signal driver 422L1 level couples sensing circuit 420.The structure of other chip layer of storehouse assembly is except not having testing circuit 315 and sensing circuit 420, similar with first chip layer.The N chip layer (N layer) of three-dimensional storehouse assembly comprises that also the relative ability driver of N 300LN is positioned on the appointed area of N layer chip layer, and a N differential signal driver 422LN also is disposed on the N chip layer; N is the natural number greater than 1.The relative ability driver of N 300LN system sees through the relative high capacity silicon wafer perforation with (N-2) of a vertically opposite low load silicon wafer perforation and the vertical first relative ability driver 300L1 that couples; Shown in its TSVx (N-2) by Fig. 4; All low relatively load silicon wafer perforation with (N-2) relatively high capacity silicon wafer perforation system pass the storehouse assembly from last the end of to, wherein low relatively load silicon wafer perforation with (N-2) relatively the perforation of high capacity silicon wafer be formed at one and share in the structure.Similarly; N differential signal driver 422LN system bores a hole through a pair of low relatively load silicon wafer and with (N-2) relative high capacity silicon wafer is bored a hole and the vertical first differential signal driver 422L1 that couples, and it is to pass the storehouse assembly from n layer to ground floor that all low relatively load silicon wafers are bored a hole with (N-2) relative high capacity silicon wafer being bored a hole.It should be noted that each low relatively load silicon wafer perforation is to be formed between first and second chip layer.(N-2) relatively high capacity silicon wafer perforation system is formed at, between first and second chip layer, between arbitrary adjacent two chip layer of storehouse assembly.Its mechanism with method of operation be illustrated in the 3rd with Fig. 4 in.Therefore, omit its unnecessary narration.
One embodiment system is one of the present invention instance or example.Be described in it " embodiment " in the specification, " some embodiment " or " other embodiment " mean describe and one of be linked among this embodiment among the involved minimum embodiment of specific characteristic, structure or characteristic, but be not all embodiment are all essential.The narration of difference such as " embodiment " or " some embodiment " means and nonessential this some embodiment that mention.It should be noted that in preamble narration specific embodiment different characteristic can be gathered sometimes in a single embodiment, graphic or narration to be in order to simplified illustration and to help the understanding to one or more different aspect of the present invention about the present invention.Yet this exposure method should not be used to the invention category that reflection is asked, thereby the characteristic in the said example is added in each claim.Otherwise, can be less than all characteristics among the above-mentioned single embodiment that discloses in following the present invention's that claim reflects viewpoint.Therefore, said embodiment is contained in claim system, and each claim itself all can be considered the independent embodiment of one of the present invention.
Claims (10)
1. the differential sensing of the storehouse assembly with plural layer and silicon wafer perforation SECO structure is characterized in that comprising:
First chip layer of one this storehouse assembly comprises that a time sequence detecting circuit and a relative ability driver couple this time sequence detecting circuit in identical chips layer level;
One sensing circuit couples this time sequence detecting circuit by a horizontal wire in this first chip layer;
One first differential signal driver, level couples this sensing circuit in this first chip layer; And
The N chip layer of one this storehouse assembly; Comprise that a relative ability driver of a N and a N differential signal driver are formed on this N chip layer; This N is the natural number greater than 1; Wherein the relative ability driver of this N system see through a vertically opposite low load silicon wafer perforation and (N-2) relatively the high capacity silicon wafer bore a hole as dummy load and vertical this first relative ability driver that couples; It is pass this storehouse assembly from this N chip layer to this first chip layer that this low relatively load silicon wafer is bored a hole with being somebody's turn to do (N-2) relative high capacity silicon wafer perforation; Wherein this low relatively load silicon wafer is bored a hole and should (N-2) relative high capacity silicon wafer perforation be formed in the shared structure; Wherein this N differential signal driver system bores a hole and vertical this first differential signal driver that couples to relative high capacity silicon wafer with (N-2) through a pair of low relatively load silicon wafer perforation; Should to low relatively load silicon wafer perforation with should (N-2) relatively high capacity silicon wafer perforation system pass this storehouse assembly from N layer to ground floor, each this low relatively load silicon wafer perforation system is formed between this first and second chip layer, each should relative high capacity silicon wafer perforation be to be formed between arbitrary adjacent two chip layer of this storehouse assembly; When an active signal reached to a trigger point, this testing circuit started this sensing circuit by this.
2. the differential sensing and the silicon wafer perforation SECO structure that have the storehouse assembly of plural layer according to claim 1; It is characterized in that more comprising a relative capabilities driver and a reverser; This reverser is disposed at this N between one of the relative high capacity silicon wafer perforation relative capabilities driver with this; The transmission speed of this relative ability driver is greater than the transmission speed of this relative capabilities driver; The transmission speed of this relative ability driver is the doubly relatively transmission speed of capabilities driver of x, and this x looks closely sensing boundary and the x of this sensing circuit greater than one.
3. have the differential sensing and the silicon wafer perforation SECO structure of the storehouse assembly of plural layer according to claim 1, it is characterized in that this time sequence detecting circuit comprises at least one reverser.
4. have the differential sensing and the silicon wafer perforation SECO structure of the storehouse assembly of plural layer according to claim 1, it is characterized in that this sensing circuit comprises a sensing amplifier, a comparator or an operational amplifier.
5. the differential sensing and the silicon wafer perforation SECO structure that have the storehouse assembly of plural layer according to claim 1; It is characterized in that the relative high capacity silicon wafer perforation of one of this low relatively load silicon wafer perforation and this (N-2) couples a sequential and dodges the control signal, this is bored a hole to low relatively load silicon wafer and should (N-2) couple an input signal to relative high capacity silicon wafer perforation.
6. the differential sensing of the storehouse assembly with plural layer and silicon wafer perforation SECO structure is characterized in that comprising:
First chip layer of one this storehouse assembly comprises that a time sequence detecting circuit and a relative ability buffer level couple this testing circuit;
One sensing circuit couples this testing circuit by a horizontal wire in this first chip layer;
One first differential signal buffer, level couples this sensing circuit; And
The N chip layer of one this storehouse assembly; Comprise that a relative ability buffer of a N and a N differential signal buffer are formed on this N chip layer; This N is the natural number greater than 1; Wherein the relative ability buffer of this N system see through a low relatively load silicon wafer perforation and (N-2) relatively the high capacity silicon wafer bore a hole as dummy load and vertical this first relative ability buffer that couples; It is pass this storehouse assembly from this N chip layer to this first chip layer that this low relatively load silicon wafer is bored a hole with being somebody's turn to do (N-2) relative high capacity silicon wafer perforation; Wherein this low relatively load silicon wafer is bored a hole and should (N-2) relative high capacity silicon wafer perforation be formed in the shared structure; Wherein this N differential signal buffer system bores a hole and vertical this first differential signal buffer that couples to relative high capacity silicon wafer with (N-2) through a pair of low relatively load silicon wafer perforation; Should to low relatively load silicon wafer perforation with should (N-2) relatively high capacity silicon wafer perforation system pass this storehouse assembly from N layer to this ground floor, each this low relatively load silicon wafer perforation system is formed between this first and second chip layer, each should relative high capacity silicon wafer perforation be to be formed between arbitrary adjacent two chip layer of this storehouse assembly; When an active signal reached to a trigger point, this testing circuit started this sensing circuit by this.
7. like the differential sensing of the said storehouse assembly of claim 6 and silicon wafer perforation SECO structure with plural layer; It is characterized in that more comprising a relative capabilities buffer and a reverser; This reverser is disposed at this N between one of the relative high capacity silicon wafer perforation relative capabilities buffer with this; The transmission speed of this relative ability buffer is greater than the transmission speed of this relative capabilities buffer, and the transmission speed of this relative ability buffer is the doubly transmission speed of this relative capabilities buffer of x.
8. like the differential sensing and the silicon wafer perforation SECO structure of the said storehouse assembly of claim 6, it is characterized in that this testing circuit comprises at least one reverser with plural layer.
9. like the differential sensing and the silicon wafer perforation SECO structure of the said storehouse assembly of claim 6, it is characterized in that this sensing circuit comprises a sensing amplifier, a comparator or an operational amplifier with plural layer.
10. like the differential sensing of the said storehouse assembly of claim 6 and silicon wafer perforation SECO structure with plural layer; It is characterized in that the relative high capacity silicon wafer perforation of one of this low relatively load silicon wafer perforation and this (N-2) couples a sequential and dodges the control signal, this is bored a hole to low relatively load silicon wafer and should (N-2) couple an input signal to relative high capacity silicon wafer perforation.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5767699A (en) * | 1996-05-28 | 1998-06-16 | Sun Microsystems, Inc. | Fully complementary differential output driver for high speed digital communications |
| CN1637938A (en) * | 2003-12-29 | 2005-07-13 | 海力士半导体有限公司 | Semiconductor memory device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5767699A (en) * | 1996-05-28 | 1998-06-16 | Sun Microsystems, Inc. | Fully complementary differential output driver for high speed digital communications |
| CN1637938A (en) * | 2003-12-29 | 2005-07-13 | 海力士半导体有限公司 | Semiconductor memory device |
Non-Patent Citations (1)
| Title |
|---|
| UKSONG KANG ET AL: "《8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology》", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
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