CN102456413B - Fuse circuit and the memory device including fuse circuit - Google Patents
Fuse circuit and the memory device including fuse circuit Download PDFInfo
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- CN102456413B CN102456413B CN201110118041.7A CN201110118041A CN102456413B CN 102456413 B CN102456413 B CN 102456413B CN 201110118041 A CN201110118041 A CN 201110118041A CN 102456413 B CN102456413 B CN 102456413B
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- 230000000875 corresponding Effects 0.000 claims description 24
- 230000004044 response Effects 0.000 claims description 20
- 238000001514 detection method Methods 0.000 claims description 14
- 230000003213 activating Effects 0.000 claims description 2
- 230000003321 amplification Effects 0.000 claims 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 16
- 230000004913 activation Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 206010010254 Concussion Diseases 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006011 modification reaction Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N oxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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Abstract
The invention discloses a kind of fuse circuit and a kind of memory device.Described fuse circuit includes: multiple fuse cells, amplifying unit and multiple depositor.Amplifying unit is configured to sequentially the data being stored in fuse cell be amplified.Depositor is configured to sequentially store the data amplified by amplifying unit.
Description
Cross-Reference to Related Applications
This application claims the korean patent application No.10-2010-0100751 submitted on October 15th, 2010
Priority, entire contents is incorporated in herein by quoting.
Technical field
The exemplary embodiment of the present invention relates to semiconductor device, more particularly to one for half
Conductor device stores the fuse circuit of data (such as restoration information).
Background technology
Generally, whether the data of fuse are cut off by laser instrument according to fuse and are classified.Usually,
Before wafer is installed in packaging body, in wafer state, fuse is programmed.
Antifuse (antifuse) is used to overcome above such restriction.Antifuse uses transistor to store up
Deposit data.The data of antifuse are classified according to the resistance between grid and drain/source.
Fig. 1 illustrates and includes that the antifuse of transistor and antifuse are as resistance or the operation of electric capacity.
Seeing Fig. 1, antifuse includes that transistor T, described transistor T have and is applied in supply voltage
Grid G, and it is applied in the drain/source terminal D/S of ground voltage.
When applying, to grid G, the normal supply voltage that transistor T allows, antifuse such as electric capacity C
Equally operate.Therefore, electric current is not had to flow between grid G and drain/source terminal D/S.So
And, when applying, to grid G, the high power supply voltage that transistor T is impermissible for, the grid oxygen of transistor T
Compound is destroyed, in order to make grid G and drain/source terminal D/S short circuit, thus antifuse such as resistance
R equally works.Therefore, electric current flows between grid G and drain/source terminal D/S.
Based on this fact, detected instead by the resistance value between grid G and drain/source terminal D/S
The data of fuse.In one approach, sensing can need not by increasing the size of transistor T
The data of antifuse are directly detected in the case of operation.In another approach, transistor T it is increased without
Size, the electric current of transistor T can be flowed through by sensing by means of amplifier and detect antifuse
Data.But, because the transistor T of antifuse is designed to have big size or must include pin
Amplifier to each fuse, therefore above two method Shortcomings for area.
Summary of the invention
The exemplary embodiment of the present invention is intended to reduce the area of the fuse circuit including multiple fuse.
According to one exemplary embodiment of the present invention, a kind of fuse circuit includes: multiple fuse cells;
Amplifying unit, described amplifying unit is configured to sequentially the data being stored in fuse cell be amplified;
And multiple depositor, the plurality of depositor is configured to sequentially store the number amplified by amplifying unit
According to.
Fuse cell can be anti-fuse cell, and can include at the beginning of the system of described fuse circuit
The storage operation of the amplifieroperation of the order of amplifying unit and the order of depositor is performed in beginning to operate.
According to another exemplary embodiment of the present invention, a kind of fuse circuit includes: multiple fuse cells,
The plurality of fuse cell is configured to respond to the selection corresponding thereto among multiple selection signal
Signal and be enabled;Counter unit, described counter unit is configured to count the wave of oscillation also
Produce address;Translator unit, described translator unit is configured to decode address and produce choosing
Select signal;Amplifying unit, described amplifying unit is configured to the fuse being enabled among by fuse cell
The data of unit are amplified;And multiple depositor, the plurality of depositor is configured to respond to select letter
Selection signal corresponding thereto among number and be enabled, and store the data amplified by amplifying unit.
According to another exemplary embodiment of the present invention, a kind of memory device includes: multiple fuse cells,
The plurality of fuse cell is configured to respond to the selection corresponding thereto among multiple selection signal
Signal and be enabled;Counter unit, described counter unit is configured to count the wave of oscillation also
Produce address;Translator unit, described translator unit is configured to decode address and produce choosing
Select signal;Amplifying unit, described amplifying unit is configured to the fuse being enabled among by fuse cell
The data of unit are amplified;Memory bank district, described memory bank district includes multiple memory element and multiple depositor,
Each choosing corresponding thereto being configured to respond among described selection signal in described depositor
Select signal and be enabled, and store the data amplified by amplifying unit;And multiple address wire, described many
Individual address wire is configured to be sent to address memory bank district.
Accompanying drawing explanation
Fig. 1 is that explanation includes that the antifuse of transistor and antifuse are as resistance or the operation of electric capacity
Figure.
Fig. 2 is the block diagram of the fuse circuit according to one exemplary embodiment of the present invention.
Fig. 3 is the block diagram of the fuse circuit of the Fig. 2 according to one exemplary embodiment of the present invention.
Fig. 4 is the block diagram of the circuit of the enable signal RD_EN producing Fig. 3.
Fig. 5 is the sequential chart of the operation of the circuit of explanatory diagram 4.
Fig. 6 is the block diagram of the fuse circuit of Fig. 2 of another exemplary embodiment according to the present invention.
Fig. 7 is the block diagram of the circuit enabling signal producing Fig. 6.
Fig. 8 is the sequential chart of the operation of the circuit of explanatory diagram 7.
Fig. 9 is the memorizer of the fuse circuit including Fig. 3 according to one exemplary embodiment of the present invention
The block diagram of part.
Figure 10 is an address wire of the transfer address in a time division manner in the address wire of Fig. 9 and data
Sequential chart.
Detailed description of the invention
It is described more fully the exemplary embodiment of the present invention below with reference to accompanying drawings.But, the present invention
Can implement by different modes, and should not be construed as limited to embodiments set forth herein.
Exactly, it is provided that these embodiments are to make this specification understand and completely, and will be to ability
Field technique personnel pass on the scope of the present invention completely.In this manual, identical reference is at this
Each bright drawings and Examples represent identical parts.
Fig. 2 is the block diagram of the fuse circuit according to one exemplary embodiment of the present invention.
See Fig. 2, include multiple fuse list according to the fuse circuit of one exemplary embodiment of the present invention
Unit (fuse cell) 210_0 to 210_N, amplifying unit 220 and multiple depositor 230_0 to 230_N.
Amplifying unit 220 is configured to sequentially the data being stored in fuse cell 210_0 to 210_N be put
Greatly.Depositor 230_0 to 230_N is configured to sequentially store the data amplified by amplifying unit 220.
Each in fuse cell 210_0 to 210_N stores data according to programmed result.Fuse cell
210_0 to 210_N can be the anti-fuse cell (antifuse needing the amplifieroperation for sensing data
cell).But, owing to common fuse (such as, laser cutting type fuse) also may require that amplifieroperation,
Therefore fuse cell 210_0 to 210_N can also be the fuse type in addition to antifuse.
The data being stored in fuse cell 210_0 to 210_N are sequentially amplified by amplifying unit 220.
Word " sequentially " refers to the data of fuse cell 210_0 to 210_N with predetermined order one by one
Be exaggerated, and be not necessarily meant to refer to the data of fuse cell 210_0 to 210_N with from the 0th fuse list
The order of unit 210_0 to N fuse cell 210_N is exaggerated.That is, amplifying unit 220 is to fuse
The order that the data of unit 210_0 to 210_N are amplified can change according to different embodiments.
In one exemplary embodiment of the present invention, the amplifieroperation of amplifying unit 220 execution sequence.Therefore,
The each offer amplifying unit 220 being not necessary in fuse cell 210_0 to 210_N.Therefore, may be used
Think that fuse cell 210_0 to 210_N provides an amplifying unit 220.For example, it is possible to be every 100
Individual fuse cell provides an amplifying unit.200 fuse cells altogether can also be provided, and can be
These 200 fuse cells provide two amplifying units, sequentially the data of corresponding fuse cell to be put
Greatly.
Depositor 230_0 to 230_N sequentially stores the data amplified by amplifying unit 220.Depositor
230_0 to 230_N and fuse cell 210_0 to 210_N one_to_one corresponding, and depositor 230_0 is extremely
The data of each storage corresponding fuse cell 210_0 to 210_N in 230_N.Such as, the 0th melts
The data of silk unit 210_0 are amplified by amplifying unit 220 and the data of gained are stored into the 0th and deposit
In device 230_0, and the data of the 4th fuse cell 210_4 are amplified by amplifying unit 220 and gained
Data are stored in the 4th depositor 230_4.Depositor 230_0 to 230_N can include latch.
Depositor 230_0 to 230_N has high data input/output speed.Therefore, described fuse is used
The system (the most various semiconductor chips, such as memory device) of circuit can access rapidly and be stored in
Data in depositor 230_0 to 230_N, with thinking that system obtains desired information.
The data being stored in fuse cell 210_0 to 210_N are sequentially put by the fuse circuit of the present invention
Greatly, the data of gained are stored in depositor 230_0 to 230_N, and depositor 230_0 will be stored in
Data to 230_N provide to the system using described fuse circuit.Amplifying unit 220 execution sequence
Amplifieroperation.Therefore, there is no need to amplify for each offer in fuse cell 210_0 to 210_N
Device, such as amplifying unit 220, thus can be greatly reduced the gross area of fuse circuit.
It is stored in the data in fuse cell 210_0 to 210_N and must be stored into depositor 230_0
It was exaggerated before 230_N, in order to use the system of described fuse circuit to use and be stored in fuse list
Data in unit 210_0 to 210_N.Therefore, it can system initial using described fuse circuit
Operation performs the amplifieroperation of amplifying unit 220 and the data amplified by amplifying unit 220 are stored
Operation in depositor 230_0 to 230_N.
Fig. 3 is the block diagram of the fuse circuit of the Fig. 2 according to one exemplary embodiment of the present invention.
Fig. 3 illustrates following exemplary cases: the fuse circuit of the present invention is applied to memory device,
And a part for the structure of fuse circuit shares the original structure of described memory device.
See Fig. 3, include multiple fuse list according to the fuse circuit of one exemplary embodiment of the present invention
Unit 210_0 to 210_N, counter unit 310, translator unit 320, amplifying unit 220 and many
Individual depositor 230_0 to 230_N.
Counter unit 310 is configured to count automatic refresh signal REF, and produces address
A<0:M>.Automatically refresh operation is to perform in the initial mode of operation of memory device.To this end,
In the initial mode of operation of memory device, periodically apply automatic refresh command periodically to activate certainly
Dynamic refresh signal REF.Automatic refresh signal REF is counted by counter unit 310, and often
When automatic refresh signal REF is activated increase address A<0:M>value.
When automatic refresh signal REF is activated, perform the automatic refresh operation of memory device, with
Sequentially activate the wordline of different address.Therefore, memory device includes being configured to automatic refresh signal
REF carries out counting and increase address A<0:M>counter unit.Thus, it is arranged in memory device
, the counter unit 310 being used as the present invention for the counter unit of automatic refresh operation.
Translator unit 320 is configured to address A<0:M>decode, and produce multiple selection letter
Number SEL<0:N>.Select signal SEL<0:N>in one according to translator unit 320 to address
A<0:M>decoding result and be activated.Due to address A<0:M>value connected by counter unit 310
Increase, the selection signal SEL < 0:N therefore activated by translator unit 320 change continuously continuously.
Such as, according to the decoding result of translator unit 320, select signal SEL<0>first it is activated, so
Rear selection signal SEL<1>, SEL<2>..., SEL<N>be sequentially activated.Signal will be enabled
RD_EN is input in translator unit 320, to be enabled by translator unit 320.When enabling signal
When RD_EN is activated, translator unit 320 performs normal decoded operation;And when enabling signal
When RD_EN is deactivated, translator unit 320 is by all of selection signal SEL<0:N>deexcitation.
Fuse cell 210_0 to 210_N be configured to respond to select signal SEL<0:N>among with
Its corresponding selection signal and be enabled.Such as, fuse cell 210_0 can be in response to selecting signal
SEL<0>and be enabled, and fuse cell 210_4 can be in response to selecting signal SEL<4>and be enabled.
When select signal SEL<0:N>in one be activated time, among fuse cell 210_0 to 210_N
Its stored data are exported to amplifying unit 220 by corresponding fuse cell.Such as, when selecting signal
SEL<1>when being activated, the data of fuse cell 210_1 are transferred into amplifying unit 220;And when selecting
Signal SEL<N>when being activated, the data of fuse cell 210_N are transferred into amplifying unit 220.As
Upper described, fuse cell 210_0 to 210_N can be that needs are for sensing the anti-of the amplifieroperation of data
Fuse cell.
It is molten that amplifying unit 220 is configured to being enabled among fuse cell 210_0 to 210_N
The data of silk unit output are amplified.As it has been described above, fuse cell 210_0 to 210_N is according to selecting signal
SEL<0:N>and be the most sequentially enabled, and amplifying unit 220 is molten by be enabled
The data of silk unit are amplified.
Depositor 230_0 to 230_N be configured to respond to select signal SEL<0:N>among and its
Corresponding selection signal and be enabled.Such as, depositor 230_0 can be in response to selecting signal
SEL<0>and be enabled, and depositor 230_4 can be in response to selecting signal SEL<4>and be enabled.
When select signal SEL<0:N>in one be activated time, the phase among depositor 230_0 to 230_N
The depositor answered stores the data amplified by amplifying unit 220.Such as, when selecting signal SEL<1>quilt
During activation, amplifying unit 220 data amplified are stored in depositor 230_1, and when selecting letter
Number SEL<N>when being activated, amplifying unit 220 data amplified are stored in depositor 230_N.
Therefore, in the initial refresh operation time period automatically of semiconductor device, fuse circuit sequentially will
The data that are stored in fuse cell 210_0 to 210_N are amplified, and the data of gained are stored into and deposit
In device 230_0 to 230_N.Hereafter, memory device is enabled by fuse circuit, is stored in direct use
Data (such as, restoration information) in depositor 230_0 to 230_N.
Fig. 4 is the block diagram of the circuit of the enable signal RD_EN for producing Fig. 3.
Fuse circuit will be stored in during the initial operation of memory device in fuse cell 210_0 to 210_N
All data be stored in depositor 230_0 to 230_N.But, by fuse cell 210_0 extremely
After data stored by 210_N are stored in depositor 230_0 to 230_N, it is not necessary to again transmit
Data.Therefore, signal RD_EN is enabled only in order to the data by fuse cell 210_0 to 210_N
It is sent in the time period of depositor 230_0 to 230_N be activated, is therefore prevented from fuse cell 210_0
Data to 210_N are repeatedly transmitted by after being sent to depositor 230_0 to 230_N.
The circuit producing enable signal RD_EN includes address detection unit 410 and S/R latch 420.
Address detection unit 410 is configured at address A<0:M>reach to output it signal during particular value
RST_P activates.Here, the quantity of described particular value and fuse cell 210_0 to 210_N and posting
The quantity of storage 230_0 to 230_N is corresponding.Such as, if fuse circuit includes 100 (100)
Individual fuse cell 210_0 to 210_N and 100 (100) individual depositor 230_0 to 230_N, then
Described particular value is 100 (100);And if fuse circuit includes 200 (200) individual fuse cell 210_0
To the individual depositor 230_0 to 230_N of 210_N and 200 (200), the most described particular value is 200
(200)。
S/R latch 420 is configured to respond to power up (power-up) pulse signal PWRUP_P
And signal RD_EN will be enabled and activate, and in response to output signal RST_P of address detection unit 410
And signal RD_EN deexcitation will be enabled.Here, adding electric impulse signal PWRUP_P is at memorizer
Part powers up and is activated afterwards.
Fig. 5 is the sequential chart of the operation of the circuit of explanatory diagram 4.
Seeing Fig. 5, when memory device completes power-up operations, power up signal PWRUP is from logic low electricity
The flat logic high that becomes, and add electric impulse signal PWRUP_P and be activated as logic low.Ring
Ying Yu adds the activation of electric impulse signal PWRUP_P, and S/R latch 420 will enable signal RD_EN
Activate as logic high.
On the other hand, if address A<0:M>value be gradually increased by counter unit 310, and address
A<0:M>value reach particular value (such as, 100), then address detection unit 410 is by output signal
RST_P activates as logic low.In response to being activated as output signal RST_P of logic low,
Enable signal RD_EN to be deactivated as logic low.
During enabling the activationary time section of signal RD_EN, it is stored in fuse cell 210_0 extremely
Data in 210_N are sequentially amplified by amplifying unit 220, and are transferred into depositor 230_0 extremely
230_N.But, once enable signal RD_EN and be deactivated preferably at fuse cell 210_0
Gone after being all sent to depositor 230_0 to 230_N to all of data stored by 210_N
Activate and the most do not perform to amplify and data transfer operation.
Fig. 6 is the block diagram of the fuse circuit of Fig. 2 of another exemplary embodiment according to the present invention.
Fig. 3 illustrates after the powering up of memory device data in automatic refresh operation time period from fuse
The fuse cell 210_0 to 210_N of circuit is sent to the depositor 230_0 to 230_N of fuse circuit
An exemplary cases.Do not perform automatically to refresh behaviour during initialization time section however, it is possible to exist
The memory device made.Therefore, Fig. 6 illustrates following exemplary cases: memory device operation it
After, data in the waiting period started by the reset signal being activated for the first time from fuse cell
210_0 to 210_N is sent to depositor 230_0 to 230_N.
See Fig. 6, include multiple fuse according to the fuse circuit of another exemplary embodiment of the present invention
Unit 210_0 to 210_N, wave of oscillation generating unit 610, counter unit 620, translator unit
630, amplifying unit 220 and multiple depositor 230_0 to 230_N.
Wave of oscillation generating unit 610 can include ring oscillator 611 and output unit 612.Annular is shaken
Swing device 611 to be configured to produce primary Sasser OSC_PRE.Output unit 612 is configured to output
Primary Sasser OSC_PRE or automatically refresh signal as wave of oscillation OSC as wave of oscillation OSC.
As shown in Figure 6, output unit 612 can be configured with or door (OR gate).Ring oscillator 611 exists
Primary Sasser OSC_PRE is periodically activated during enabling the activationary time section of signal RD_EN,
And during enabling the deexcitation time period of signal RD_EN, primary Sasser OSC_PRE is fixed as
Logic low.When primary Sasser OSC_PRE triggers, output unit 612 exports primary concussion
Ripple OSC_PRE is as wave of oscillation OSC;And when automatic refresh signal REF triggers, output unit
612 export automatic refresh signal REF as wave of oscillation OSC.Exemplary embodiment according to Fig. 6
Fuse circuit is in non-automatic refresh time section (when i.e., not periodically activating automatic refresh signal REF
Time period) in utilize ring oscillator 611 and by the data transmission of fuse cell 210_0 to 210_N
To depositor 230_0 to 230_N.
Counter unit 620 is configured to count wave of oscillation OSC, and produces address A<0:M>.
When wave of oscillation OSC is activated, address A<0:M>value by means of the operation of counter unit 620
And increase.As the exemplary embodiment of Fig. 3, arranging for automatic refresh operation in memory device
Enumerator be used as the counter unit 620 of the present invention.
Translator unit 630 is configured to address A<0:M>decode, and produce multiple selection letter
Number SEL<0:N>.Select signal SEL<0:N>in one according to translator unit 630 to address
A<0:M>decoding result and be activated.Due to address A<0:M>value connected by counter unit 620
Increase, the selection signal SEL < 0:N therefore activated by translator unit 630 change the most continuously continuously.
Such as, according to the decoding result of translator unit 630, select signal SEL<0>first it is activated, so
Rear selection signal SEL<1>, SEL<2>..., SEL<N>be sequentially activated.Enable signal RD_EN
It is imported into translator unit 630, to be enabled by translator unit 630.When enabling signal RD_EN
When being activated, translator unit 630 performs normal decoded operation;And when enabling signal RD_EN quilt
During deexcitation, translator unit 630 is by all of selection signal SEL<0:N>deexcitation.
Fuse cell 210_0 to 210_N be configured to respond to select signal SEL<0:N>among with
Its corresponding selection signal and be enabled.Such as, fuse cell 210_0 can be in response to selecting signal
SEL<0>and be enabled, and fuse cell 210_4 can be in response to selecting signal SEL<4>and be enabled.
When select signal SEL<0:N>in one be activated time, among fuse cell 210_0 to 210_N
The data that corresponding fuse cell is stored export to amplifying unit 220.Such as, when selecting signal
SEL<1>when being activated, the data of fuse cell 210_1 are transferred into amplifying unit 220;And when selecting
Signal SEL<N>when being activated, the data of fuse cell 210_N are transferred into amplifying unit 220.As
Upper described, fuse cell 210_0 to 210_N can be that needs are for sensing the anti-of the amplifieroperation of data
Fuse cell.
It is molten that amplifying unit 220 is configured to being enabled among fuse cell 210_0 to 210_N
The data of silk unit output are amplified.As it has been described above, fuse cell 210_0 to 210_N is according to selecting signal
SEL<0:N>and be the most sequentially enabled, and amplifying unit 220 is molten by be enabled
The data of silk unit are amplified.
Depositor 230_0 to 230_N be configured to respond to select signal SEL<0:N>among and its
Corresponding selection signal and be enabled.Such as, depositor 230_0 can be in response to selecting signal
SEL<0>and be enabled, and depositor 230_4 can be in response to selecting signal SEL<4>and be enabled.
When select signal SEL<0:N>in one be activated time, the phase among depositor 230_0 to 230_N
The depositor answered stores the data amplified by amplifying unit 220.Such as, when selecting signal SEL<1>quilt
During activation, amplifying unit 220 data amplified are stored in depositor 230_1, and when selecting letter
Number SEL<N>when being activated, amplifying unit 220 data amplified are stored in depositor 230_N.
Therefore, in the activationary time section enabling signal RD_EN, fuse circuit sequentially will be stored in
Data in fuse cell 210_0 to 210_N are amplified, and the data of gained are stored into depositor 230_0
To 230_N.Hereafter, memory device is enabled by fuse circuit, is stored in depositor with direct use
Data (such as, restoration information) in 230_0 to 230_N.
Fig. 7 is the block diagram of the circuit of the enable signal RD_EN producing Fig. 6.
After the operation of memory device, the fuse circuit of Fig. 6 is by the reset signal being activated for the first time
During the waiting period started, (usually, 500 μ s after resetting for the first time) will be stored in
All of data in fuse cell are sent to depositor.The circuit of Fig. 7 is configured in waiting period
Middle will enable signal activation.
The circuit producing enable signal RD_EN includes reset signal detector unit 710, address detected list
Unit 720 and S/R latch 730.
Reset signal detector unit 710 is configured to receive reset signal RESET, and only at the letter that resets
When number RESET is activated for the first time, reset detection signal F_RESET is activated.Such as, if
After the operation of memory device, reset signal RESET is activated three times, then reset detection signal
F_RESET is only just activated when reset signal RESET is activated for the first time.
Address detection unit 720 is configured at address A<0:M>reach to output it signal during particular value
RST_P activates.Here, the quantity of described particular value and fuse cell 210_0 to 210_N and posting
The quantity of storage 230_0 to 230_N is corresponding.Such as, if fuse circuit includes 100 (100)
Individual fuse cell 210_0 to 210_N and 100 (100) individual depositor 230_0 to 230_N, then institutes
Stating particular value is 100 (100);And if fuse circuit includes 200 (200) individual fuse cell 210_0
To the individual depositor 230_0 to 230_N of 210_N and 200 (200), the most described particular value is 200 (200).
When reset detection signal F_RESET is activated, S/R latch 730 will enable signal
RD_EN activates, and when output signal RST_P is activated, S/R latch 730 will enable signal
RD_EN deexcitation.
Therefore, when reset signal RESET is activated for the first time, enables signal RD_EN and be activated,
And when all of data of fuse cell 210_0 to 210_N are all sent to depositor 230_0 extremely
During 230_N, enable signal RD_EN and be deactivated.
Fig. 8 is the sequential chart of the operation of the circuit of explanatory diagram 7.
Seeing Fig. 8, when memory device completes power-up operations, power up signal PWRUP is activated as patrolling
Collecting high level, reset signal RESET is activated as logic high subsequently.When reset signal RESET
When being activated for the first time, reset detection signal F_RESET is activated and is by reset signal detector unit 710
Logic low.Lock in response to the reset detection signal F_RESET, SR being activated as logic low
Storage 730 will enable signal RD_EN and activate as logic high.
On the other hand, if address A<0:M>value be gradually increased by counter unit 620, and address
A<0:M>value reach particular value (such as, 100), then address detection unit 720 is by output signal
RST_P activates as logic low.In response to being activated as output signal RST_P of logic low,
Enable signal RD_EN deexcitation is logic low by S/R latch 730.
Fig. 9 is the memorizer of the fuse circuit including Fig. 3 according to one exemplary embodiment of the present invention
The block diagram of part.
See Fig. 9, include multiple fuse list according to the memory device of one exemplary embodiment of the present invention
Unit 210_0 to 210_N, counter unit 310, translator unit 320, amplifying unit 220, storage
Body (bank) district 900 and multiple address wire ADD_LINES.Fuse cell 210_0 to 210_N
Be configured to respond to multiple selection signal SEL<0:N>among selection signal corresponding thereto and quilt
Enable.Counter unit 310 is configured to count automatic refresh signal REF, and produces ground
Location A<0:M>.Translator unit 320 is configured to address A<0:M>decode, and produce choosing
Select signal SEL<0:N>.Amplifying unit 220 is configured among fuse cell 210_0 to 210_N
The fuse cell being enabled data amplify.Memory bank district 900 includes that multiple memory element 910 is with many
Individual depositor 230_0 to 230_N and store the data amplified by amplifying unit 220, the plurality of
Depositor 230_0 to 230_N be configured to respond to select signal SEL<0:N>among corresponding thereto
The selection signal answered and be enabled.Address wire ADD_LINES is configured to address A<0:M>transmit
To memory bank district 900.Here, at least one in described address wire ADD_LINES not only transmits ground
Location A<0:M>, but also transmit the data amplified by amplifying unit 220.
In automatic refresh operation, fuse circuit will be stored in fuse cell 210_0 to 210_N
Data are amplified, and the data of gained are sent to the depositor 230_0 included by memory bank district 900 extremely
230_N.And, in automatic refresh operation, counter unit 310 the address A<0:M produced>
Memory bank district 900 must be sent to from counter unit 310.Therefore, memory device includes address wire
ADD_LINES, in order to by address A<0:M>it is sent to memory bank district 900.The fuse circuit of the present invention
The data using at least one in address wire ADD_LINES and will be amplified by amplifying unit 220
DATA is sent to the depositor 230_0 to 230_N included by memory bank district 900.
That is, transmit by counter unit via at least one in address wire ADD_LINES simultaneously
The 310 address A<0:M produced>and data DATA amplified by amplifying unit 220.This can lead to
Crossing use time division scheme (time division scheme) to realize, this time division scheme is in first time period
Period via at least one in address wire ADD_LINES come transfer address (A<X>, wherein X is
Arbitrary integer from 0 to M), and during the second time period in address wire ADD_LINES extremely
Few upper transmission data DATA.
Driver 920 at the activationary time of the first signal STROBE_1 via address wire ADD_LINES
In one by address A<0:M>be sent to memory bank district 900, and in secondary signal STROBE_2
Data DATA are sent to memory bank district 900 via identical address wire by activationary time.Here, first
Signal STROBE_1 utilizes refresh signal REF to produce, and secondary signal STROBE_2 is
By postponing what the first signal STROBE_1 produced.
According to above-mentioned time division scheme, it is possible to use existing address wire will be as being stored in fuse cell
Data in 210_0 to 210_N are sent to the address wire of depositor 230_0 to 230_N
ADD_LINES, is therefore prevented from using the area of the memory device of the fuse circuit of the present invention to increase.
Although Fig. 9 illustrates memory device only includes a memory bank district, but the invention is not restricted to this.
In other exemplary embodiment, memory device can include 8 or 16 memory banks.Due to storage
There are the data in fuse cell and must be communicated to the corresponding depositor included by memory bank district, therefore
Above-mentioned time division scheme is prevented from the area of memory device and increases.
Figure 10 is the A<X of transfer address in a time division manner among the address wire of Fig. 9>and data DATA
The sequential chart of address wire ADD_LINE.
Seeing Figure 10, the first signal STROBE_1 is activated as logic high at automatic refresh signal REF
Logic high it is activated as the when of level.Then, driver 920 is by address A<X>it is loaded into ground
On the line ADD_LINE of location.Secondary signal STROBE_2 is at swashing from the first signal STROBE_1
It is activated after the special time that live time is lighted.Driver 920 is in response to secondary signal STROBE_2
And data DATA are loaded in address wire ADD_LINE.I.e., in a time division manner via address wire
ADD_LINE carrys out transfer address A<X>and data (DATA).
For reference, as address A<X>memory bank district it is transferred into via address wire ADD_LINE
When 900, it is arranged in memory bank region 900, for selecting the line decoder (not shown) of wordline
Latch address A<X>.At address A<X>latched by line decoder after, even if there being data DATA quilt
It is loaded in address wire ADD_LINE, does not also interfere with the operation of line decoder.
As it has been described above, according to the exemplary embodiment of the present invention, the data of fuse cell are suitable by amplifying unit
Sequence ground amplifies, and the data amplified sequentially are stored in depositor.Therefore, even if fuse is set
It is calculated as that there is small size, it is not required that provide amplifier for each fuse, thus can reduce fuse circuit
Area.
If additionally, use described fuse circuit in memory device, can existing with share storage device
Element, thus can reduce the area of memory device.
Although the present invention of having had been described with reference to specific embodiments, but for those skilled in the art
Speech is it is evident that in the premise of the spirit and scope of the present invention limited without departing from appended claims
Under, variations and modifications can be carried out.
Claims (12)
1. a fuse circuit, including:
Multiple fuse cells, the plurality of fuse cell be configured to respond among multiple selection signal with
Its corresponding selection signal and be enabled;
Counter unit, described counter unit is configured to count the wave of oscillation and produce address;
Translator unit, described translator unit is configured to decode and produce described choosing to described address
Select signal;
Amplifying unit, described amplifying unit is configured to the fuse list being enabled among by described fuse cell
The data of unit are amplified;And
Multiple depositors, the plurality of depositor be configured to respond among described selection signal with its phase
Corresponding selection signal and be enabled, and store the data amplified by described amplifying unit,
Wherein,
Described fuse circuit is used in memory device,
The described wave of oscillation is applied to the automatic refresh signal of described memory device, and
Described translator unit is in response to the enable signal being activated in the initial operation of described memory device
It is enabled.
2. fuse circuit as claimed in claim 1, wherein said fuse cell is anti-fuse cell.
3. fuse circuit as claimed in claim 1, the described address wherein produced by described counter unit
It is used in the automatic refresh operation of described memory device.
4. fuse circuit as claimed in claim 1, wherein said enable signal is quilt in response to power up signal
Activate, and be deactivated after all of described fuse cell is sequentially enabled.
5. fuse circuit as claimed in claim 1, wherein said enable signal is by address detection unit and SR
Latch produces, and described address detection unit is configured to detect the value of described address, described S/R latch quilt
It is configured to the output signal in response to described address detection unit and by described enable signal deexcitation.
6. a fuse circuit, including:
Multiple fuse cells, the plurality of fuse cell be configured to respond among multiple selection signal with
Its corresponding selection signal and be enabled;
Counter unit, described counter unit is configured to count the wave of oscillation and produce address;
Translator unit, described translator unit is configured to decode and produce described choosing to described address
Select signal;
Amplifying unit, described amplifying unit is configured to the fuse list being enabled among by described fuse cell
The data of unit are amplified;
Multiple depositors, the plurality of depositor be configured to respond among described selection signal with its phase
Corresponding selection signal and be enabled, and store the data amplified by described amplifying unit;And
Wave of oscillation generating unit, described wave of oscillation generating unit is configured to produce the described wave of oscillation,
Wherein,
Described wave of oscillation generating unit includes:
Ring oscillator, described ring oscillator is configured to produce primary Sasser;And
Output unit, described output unit is configured to export described primary Sasser or automatic refresh signal is made
For the described wave of oscillation.
7. fuse circuit as claimed in claim 6, wherein said fuse circuit is used in memory device, institute
Stating translator unit to be enabled in response to enabling signal, described enable signal is in the operation of described memory device
Afterwards, it is activated in being activated, by the first time of reset signal, the waiting period started.
8. fuse circuit as claimed in claim 6, wherein said fuse circuit is used in memory device, institute
State translator unit to be activated in response to enabling signal, and at all of described fuse cell all by order
Ground is deactivated after enabling, and described enable signal is after the operation of described memory device, reset signal quilt
It is activated when activating for the first time.
9. a memory device, including:
Multiple fuse cells, the plurality of fuse cell be configured to respond among multiple selection signal with
Its corresponding selection signal and be enabled;
Counter unit, described counter unit is configured to count the wave of oscillation and produce address;
Translator unit, described translator unit is configured to decode and produce described choosing to described address
Select signal;
Amplifying unit, described amplifying unit is configured to the fuse list being enabled among by described fuse cell
The data of unit are amplified;
Memory bank district, described memory bank district includes multiple memory element and multiple depositor, in described depositor
Each selection signal corresponding thereto being configured to respond among described selection signal and be enabled,
And store the data amplified by described amplifying unit;And
Multiple address wires, the plurality of address wire is configured to be sent to described address described memory bank district.
10. memory device as claimed in claim 9, at least one in wherein said address wire is when first
Between transmit described address during section, and during the second time period, transmit the data of described amplification.
11. memory devices as claimed in claim 9, at least one in wherein said address wire in response to by
Automatically refresh signal produces the first signal and transmit described address, and in response to by postponing described first letter
Number and the secondary signal that produces to transmit the data of described amplification.
12. memory devices as claimed in claim 9, also include driver, described driver be configured to by
Described address is loaded at least one in described address wire, and is loaded into identical by the data of described amplification
Address wire on.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100100751A KR101113790B1 (en) | 2010-10-15 | 2010-10-15 | Fuse circuit and memory device including the same |
KR10-2010-0100751 | 2010-10-15 |
Publications (2)
Publication Number | Publication Date |
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CN102456413A CN102456413A (en) | 2012-05-16 |
CN102456413B true CN102456413B (en) | 2016-12-14 |
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US5808944A (en) * | 1996-02-08 | 1998-09-15 | Hitachi, Ltd. | Semiconductor memory device having a defect relief arrangement |
CN1901093A (en) * | 2005-07-22 | 2007-01-24 | 三星电子株式会社 | Redundancy selector circuit for use in non-volatile memory device |
CN101228589A (en) * | 2005-07-25 | 2008-07-23 | 精工爱普生株式会社 | Semiconductor storage device |
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US5808944A (en) * | 1996-02-08 | 1998-09-15 | Hitachi, Ltd. | Semiconductor memory device having a defect relief arrangement |
CN1901093A (en) * | 2005-07-22 | 2007-01-24 | 三星电子株式会社 | Redundancy selector circuit for use in non-volatile memory device |
CN101228589A (en) * | 2005-07-25 | 2008-07-23 | 精工爱普生株式会社 | Semiconductor storage device |
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