CN102446951B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN102446951B CN102446951B CN 201010501685 CN201010501685A CN102446951B CN 102446951 B CN102446951 B CN 102446951B CN 201010501685 CN201010501685 CN 201010501685 CN 201010501685 A CN201010501685 A CN 201010501685A CN 102446951 B CN102446951 B CN 102446951B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 408
- 238000000034 method Methods 0.000 title claims abstract description 68
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- 239000000758 substrate Substances 0.000 claims abstract description 69
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- 229910052581 Si3N4 Inorganic materials 0.000 description 5
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- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
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Abstract
A semiconductor structure is formed on a first semiconductor layer and comprises a nanowire set and two semiconductor substrates; each semiconductor substrate comprises at least two second semiconductor layers, and each second semiconductor layer is formed on the insulating layer; among the semiconductor substrates, the second semiconductor layers and the insulating layers correspond to each other one by one; the nanowire group comprises at least two nanowires, each nanowire is discrete and comprises a third semiconductor layer, the materials of the second semiconductor layer are different from those of the first semiconductor layer and/or the third semiconductor layer, each nanowire is connected with each corresponding second semiconductor layer one by one, and the projections of the nanowires on the first semiconductor layer are overlapped. And, a method of forming a semiconductor structure. The integration level is increased.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically, relate to a kind of semiconductor structure and forming method thereof.
Background technology
Along with the critical dimension of semiconductor structure is more and more less, due to the particularity on structure and performance, the application prospect of nano wire aspect semiconductor structure manifested, and makes it become the study hotspot in current international forward position.Especially, in VLSI (very lagre scale integrated circuit (VLSIC)) field, because nano wire has characteristic and the short channel control characteristic that height ratio is dwindled, and paid much attention to.
But, at present, the described nano wire of each making is all directly to be formed on semiconductor base, make utilizing of described semiconductor base relatively limited, for applying nano line better is beneficial to scaled down characteristic, if the nano wire on being formed at semiconductor base, also has a kind of nano wire that is formed at the semiconductor base top, can reduce to carry the area of the required semiconductor base of similar number nano wire, be beneficial to thering is the more semiconductor structure of manufacture on the semiconductor base of same area, increase integrated level.
Summary of the invention
In order to address the above problem, the invention provides a kind of semiconductor structure and forming method thereof, be beneficial to the increase integrated level.
A kind of semiconductor structure provided by the invention, described semiconductor structure is formed on the first semiconductor layer, and described semiconductor structure comprises set of nanowires and two semiconductor substrates; Each described semiconductor substrate comprises at least two the second semiconductor layers, and each described second semiconductor layer is formed on insulating barrier; Between each described semiconductor substrate, each described second semiconductor layer and each described insulating barrier are corresponding one by one; Described set of nanowires comprises at least two nano wires, each described nano wire is discrete and comprise the 3rd semiconductor layer, described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material, described the second semiconductor layer that each described nano wire is corresponding with each joins one by one, and the projection of each described nano wire on described the first semiconductor layer overlaps.
A kind of semiconductor structure provided by the invention, described semiconductor structure is formed on the first semiconductor layer, and described semiconductor structure comprises two set of nanowires and two semiconductor substrates; Each described semiconductor substrate comprises at least two the second semiconductor layers, and each described second semiconductor layer is formed on insulating barrier, and between each described semiconductor substrate, each described second semiconductor layer and each described insulating barrier are corresponding one by one; Each described set of nanowires comprises at least two nano wires, each described nano wire is discrete and comprise the 3rd semiconductor layer, described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material, and between each described set of nanowires, each described nano wire is corresponding one by one; Described the second semiconductor layer described nano wire corresponding with each of each correspondence joins one by one; In same described set of nanowires, the projection of each described nano wire on described the first semiconductor layer overlaps.
The formation method of a kind of semiconductor structure provided by the invention comprises:
Determine nanowire region and form semiconductor substrate and the 3rd semiconductor layer on the first semiconductor layer, described the 3rd semiconductor layer covers described nanowire region and embeds in described semiconductor substrate; Described semiconductor substrate comprises at least three the second semiconductor layers, and each described second semiconductor layer is sandwiched between insulating barrier; Described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material, is formed with the first hard mask in being connected to described nanowire region on the described semiconductor substrate of one group of opposite flank;
Form the second hard mask, the described second hard mask is attached to sidewall and described the 3rd semiconductor layer of expose portion that is connected to described opposite flank in the described first hard mask;
Remove described the 3rd semiconductor layer of part exposed, to form groove;
Form the 3rd hard mask, the described the 3rd hard mask covers the sidewall of described groove, and the described first hard mask, the described second hard mask are different from described insulating layer material with the described the 3rd hard mask;
Removal is away from the described semiconductor substrate of the part of described nanowire region, be less than so that be connected to the width of described opposite sides in described semiconductor substrate the width that is connected to other places, side, to expose described the first semiconductor layer, each described insulating barrier and each described the second semiconductor layer;
Removal is connected in described semiconductor substrate the described insulating barrier that is connected to described opposite sides, and the surface of described the 3rd semiconductor layer of part of exposure carrying the described first hard mask, after removing the described first hard mask, the described second hard mask and the described the 3rd hard mask, on described normal to a surface direction, described the second semiconductor layer of take is mask, remove described the 3rd semiconductor layer, then remove described the second semiconductor layer as mask.
Compared with prior art, adopt technical scheme provided by the invention to there is following advantage:
By making described set of nanowires comprise at least two nano wires, each described nano wire is discrete, and the projection of each described nano wire on described the first semiconductor layer overlap (or, by making described device comprise two set of nanowires, each described set of nanowires comprises at least two nano wires, each described nano wire is discrete, and the projection of each described nano wire on described the first semiconductor layer overlaps, between each described set of nanowires, each described nano wire is corresponding one by one), can above described semiconductor base, form nano wire, in addition, because each described second semiconductor layer has formed stacked structure by each described insulating barrier, by described the second semiconductor layer that each described nano wire is corresponding with each is joined one by one, then, take each described nano wire as the basic channel region that forms device, described second semiconductor layer of each correspondence of take is that basis forms the source-drain area of device, be beneficial to and form the stacking of device, , be beneficial to the area that reduces to carry the required described semiconductor base of the described nano wire of similar number, and there is the more device of manufacture on the described semiconductor base of same area, increase integrated level.
By making described grid be connected to each described nano wire, that is, make each device share a described grid, be beneficial to further increase integrated level.
By making described side wall be positioned at described set of nanowires top, be beneficial to after forming described side wall, can expose each described nano wire, then, in subsequent step, take described side wall as mask, can carry out metalized to each described nano wire, be beneficial to the resistance that reduces device.
Join by the subregion that makes upper surface in described contact hole and each described the second semiconductor layer, can control respectively each described the second semiconductor layer, then control respectively the different components that comprises each described the second semiconductor layer, be beneficial to technological design.
By making described nano wire there is smooth surface, be beneficial in described nanowire surface and form uniform passivation layer (as hafnium base oxide layer or Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO), can provide uniform described gate dielectric layer utilizing described nano wire to form device and usining described passivation layer during as gate dielectric layer, be beneficial to optimized device performance.
The accompanying drawing explanation
The vertical view that Fig. 1 to Fig. 6 is semiconductor structure the first embodiment of the present invention and respectively along the cutaway view of AA ', BB ', CC ', DD ' and EE ' direction;
The vertical view that Fig. 7 to Figure 13 is semiconductor structure the second embodiment of the present invention and respectively along the cutaway view of AA ', BB ', CC ', DD ', EE ' and FF ' direction;
Figure 14 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the cutaway view formed after semiconductor substrate;
Figure 15 to Figure 17 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the vertical view that forms after the first hard mask and along the cutaway view of AA ', BB ' direction;
Figure 18 to Figure 20 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the vertical view that forms after the 3rd semiconductor layer and along the cutaway view of AA ', BB ' direction;
Figure 21 to Figure 23 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the vertical view that forms after the second hard mask and along the cutaway view of AA ', BB ' direction;
Figure 24 to Figure 26 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the vertical view that forms after groove and along the cutaway view of AA ', BB ' direction;
Figure 27 to Figure 29 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the vertical view that forms after the 3rd hard mask and along the cutaway view of AA ', BB ' direction;
Figure 30 to Figure 32 is respectively in the formation embodiment of the method for semiconductor structure of the present invention and removes in described semiconductor substrate away from the vertical view after the part of described nanowire region with along the cutaway view of AA ', BB ' direction;
Figure 33 to Figure 34 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the cutaway view formed behind heterogeneous district along AA ', BB ' direction;
Figure 35 to Figure 37 is respectively the vertical view of the device architecture formed in the formation embodiment of the method for semiconductor structure of the present invention and along the cutaway view of AA ', BB ' direction;
Figure 38 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the cutaway view of carrying out after annealing operation along AA ' direction;
Figure 39 to Figure 42 is respectively vertical view after the part upper surface that exposes each second semiconductor layer in the formation embodiment of the method for semiconductor structure of the present invention and along the cutaway view of BB ', CC ', DD ' direction;
Figure 43 to Figure 46 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the cutaway view formed after first grid along BB ', CC ', DD ', EE ' direction;
Figure 47 to Figure 50 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the cutaway view formed after the first interlayer dielectric layer along BB ', CC ', DD ', EE ' direction;
Figure 51 to Figure 54 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the cutaway view formed after side wall along BB ', CC ', DD ', EE ' direction;
Figure 55 to Figure 58 is respectively in the formation embodiment of the method for semiconductor structure of the present invention the cutaway view formed after contact hole along BB ', CC ', DD ', FF ' direction.
Embodiment
Disclosing hereinafter provides many different embodiment or example to be used for realizing technical scheme provided by the invention.Although hereinafter parts and the setting of specific examples are not described,, they are only example, and purpose lies in restriction the present invention.
In addition, the present invention can be in different embodiment repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself do not indicate discussed various embodiment and/or arrange between relation.
The invention provides the example of various special processes and/or material, still, other techniques that those of ordinary skills can recognize and/or the alternate application of other materials, obviously do not break away from the scope of protection of present invention.Need emphasize the extension that in presents, the border in described various zones comprises necessity of doing due to the needs of technique or processing procedure.
The invention provides a kind of semiconductor structure, as shown in Figures 1 to 6, described semiconductor structure is formed on the first semiconductor layer 100, and described semiconductor structure comprises set of nanowires 140 (as empty frame in Fig. 2 is indicated) and two semiconductor substrates 120 (as empty frame in Fig. 3 is indicated); Each described semiconductor substrate 120 comprises at least two the second semiconductor layers 122, and each described second semiconductor layer 122 is formed on insulating barrier 124; Between each described semiconductor substrate 120, each described second semiconductor layer 122 and each described insulating barrier 124 are corresponding one by one; Described set of nanowires 140 comprises at least two nano wires 142, each described nano wire 142 is discrete and comprise the 3rd semiconductor layer, described the second semiconductor layer 122 is different from described the first semiconductor layer 100 and/or described the 3rd semiconductor layer material, described the second semiconductor layer 122 that each described nano wire 142 is corresponding with each joins one by one, and the projection of each described nano wire 142 on described the first semiconductor layer 100 overlaps.
Wherein, described the first semiconductor layer 100 can be silicon substrate, and preferably, described the first semiconductor layer 100 is silicon epitaxy layer, and described the first semiconductor layer 100 also can be silicon-on-insulator (SOI); Now, described the 3rd semi-conducting material can be silicon or doped silicon, described doped silicon comprises that the silicon materials that completed ion doping through ion implantation technology (can be the silicon materials of N-type or P type, as, the silicon materials of doping B, P or As) and directly form through epitaxial growth technology (in as the reactant that is generating silicon, mixing the reactant that comprises the ion component that adulterate) silicon materials that adulterate (as for the PMOS device, described silicon materials can be Si
1-Xge
x, wherein, the span of X can be 0.1～0.7, as 0.2,0.3,0.4,0.5 or 0.6; For nmos device, described silicon materials can be Si:C, and wherein, the span of the atomicity percentage of C can be 0.2%～2%, as 0.5%, 1% or 1.5%).It should be noted that, described the first semiconductor layer 100 materials also can be doped silicon, and described doped silicon is identical with above-mentioned doped silicon, repeats no more.
When described the first semiconductor layer 100 materials or described the 3rd semiconductor layer material are silicon or doped silicon, described the second semiconductor layer 122 materials are doping or unadulterated polysilicon or amorphous silicon.Be preferably the polysilicon (doped chemical can be B, P or As etc.) of doping, both be beneficial to when graphical described the second semiconductor layer 122 and obtained the high-quality figure, also be beneficial to and take described the second semiconductor layer 122 optimized device performance when basis provides source-drain area.Described insulating barrier 124 can be silicon oxide layer.
In presents, " between each described semiconductor substrate 120, each described second semiconductor layer 122 and each described insulating barrier 124 are corresponding one by one " means: while comprising two described semiconductor substrates 120 (being designated as respectively the first semiconductor substrate and the second semiconductor substrate) in described device, described the first semiconductor substrate comprises that (direction along away from described the first semiconductor layer 100, be denoted as 1241 and 1243 to two described insulating barriers 124, it should be noted that, for taking into account the simple and clear and clear of attached number in the figure, each described second semiconductor layer, the differentiation of each described insulating barrier and follow-up each described nano wire only gives exemplary concrete label in Fig. 6, in other accompanying drawings, do not distinguish), and accompany altogether two described the second semiconductor layers 122 between each described insulating barrier 124 (along the direction away from described the first semiconductor layer 100, be denoted as 1221 and 1223) time, described the second semiconductor substrate also comprises that two described insulating barriers 124 are (along the direction away from described the first semiconductor layer 100, be denoted as 1242 and 1244) and each described insulating barrier 124 between also accompany altogether two described the second semiconductor layers 122 (along away from the direction of described the first semiconductor layer 100, be denoted as 1222 and 1224).The material of the described insulating barrier 124 in described the first semiconductor substrate and described insulating barrier 124 in described the second semiconductor substrate is identical with thickness, as 1241 and 1242,1243 and 1244; The material of the second semiconductor layer 122 in described the first semiconductor substrate and the second semiconductor layer 122 in described the second semiconductor substrate is identical with thickness, as 1221 and 1222,1223 and 1224.
" described second semiconductor layer 122 of each correspondence " means a combination that described the second semiconductor layer 122 forms in arbitrary described the second semiconductor layer 122 and described the second semiconductor substrate in described the first semiconductor substrate, the material of the two identical with thickness (as 1221 and 1222 and 1223 and 1224), each described second semiconductor layer 122 can only belong to a certain definite combination.
" described the second semiconductor layer 122 that each described nano wire 142 is corresponding with each joins one by one " means: each described nano wire 142 is connected to arbitrary described combination; For arbitrary described combination, only with unique described nano wire 142, join, as, when described set of nanowires comprises 2 described nano wires, (edge is away from the direction of described the first semiconductor layer 100, be denoted as 1421 and 1423), nano wire 1421 is connected to 1221 and 1222, and nano wire 1423 is connected to 1223 and 1224.
Described semiconductor structure also comprises grid 160, and described grid 160 can adopt first grid (gatefirst) or rear grid (gate last) technique to form; While adopting first grid technique, described grid 160 can be polysilicon gate or metal gates, and (described metal gate material can be a kind of or its combination in Ti, Co, Ni, Al, W, described metal gates is formed on workfunction layers, and described workfunction layers can be a kind of or its combination in TiN, TiAlN, TaN, TaAlN, TaC); While adopting rear grid technique, described grid 160 comprises workfunction layers and metal level, described metal level is formed at (all not shown in described workfunction layers and described metal level figure) on described workfunction layers, wherein, described workfunction layers can be a kind of or its combination in TiN, TiAlN, TaN, TaAlN, TaC; Described metal level can be a kind of or its combination in Ti, Co, Ni, Al, W.
In the present embodiment, described grid 160 is connected to each described nano wire 142 through gate dielectric layer 164.Described gate dielectric layer 164 can be high dielectric constant material HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO.Take each described nano wire 142, form the channel region of device, described second semiconductor layer 122 of each correspondence of take as basis be after source-drain area that basis forms device forms device stacking, make again described grid 160 be connected to each described nano wire 142,, can make each device share a described grid 160, be beneficial to further increase integrated level.
Described semiconductor structure also comprises side wall 162, and described side wall 162 is connected to relative both sides in described grid 160.Described side wall 162 can comprise a kind of or its combination in silicon nitride, silica, silicon oxynitride or carborundum.Described side wall 162 can have sandwich construction.In the present embodiment, described side wall 162 is positioned at described set of nanowires 140 tops; Be beneficial to after forming described side wall 162, expose each described nano wire 142, then, in subsequent technique, the described side wall 162 of take is mask, can carry out metalized to each described nano wire 142, is beneficial to the resistance that reduces device.Especially, each described nano wire 142 also comprises the metallized semi conductor layer, described metallized semi conductor layer is below folded zone between described side wall 162 and described the second semiconductor layer 122 and be connected to described the second semiconductor layer 122, is beneficial to the resistance that reduces device.
Described semiconductor structure also comprises that contact hole is (in illustrated embodiment, be formed with 2 contact holes on each described semiconductor substrate, be designated as respectively 182 and 184), in described contact hole and each described the second semiconductor layer 122, the subregion (through metal silicide layer 180) of upper surface joins, and each described subregion is positioned at the homonymy of described set of nanowires 140; Be beneficial to and control respectively each described the second semiconductor layer 122, then control respectively the different components that comprises each described the second semiconductor layer 122, be beneficial to technological design.
Described nano wire 142 can have smooth surface.In presents, described smooth surface means the cross section perpendicular to its length direction in described nano wire 142 does not have the wedge angle protruded.That is, described cross section can be the circle shown in Fig. 2, also can be ellipse, also can be rectangle or squarely carries out the figure that corners obtains.Described nano wire 142 has smooth surface, is beneficial on described nano wire 142 surfaces and forms uniform passivation layer (as hafnium base oxide layer or Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO), can, utilizing described nano wire 142 to form semiconductor structures and usining described passivation layer during as gate dielectric layer 164, provide uniform described gate dielectric layer 164, to optimize the performance of described semiconductor structure.
Wherein, in presents, each described nano wire 142, each described semiconductor substrate, described grid 160, described side wall 162 and described contact hole all are embedded in interlayer dielectric layer 190.
The present invention also provides a kind of semiconductor structure, and as shown in Fig. 7 to Figure 13, described semiconductor structure is formed on the first semiconductor layer 100, and described semiconductor structure comprises two set of nanowires 140 and two semiconductor substrates 120; Each described semiconductor substrate 120 comprises at least two the second semiconductor layers 122, each described second semiconductor layer 122 is formed on insulating barrier 124, between each described semiconductor substrate 120, each described second semiconductor layer 122 and each described insulating barrier 124 are corresponding one by one; Each described set of nanowires 140 comprises at least two nano wires 142, and each described nano wire 142 is discrete and comprise the 3rd semiconductor layer, and between each described set of nanowires 140, each described nano wire 142 is corresponding one by one; Described the second semiconductor layer 122 is different from described the first semiconductor layer 100 and/or described the 3rd semiconductor layer material, and described the second semiconductor layer 122 described nano wire 142 corresponding with each of each correspondence joins one by one; In same described set of nanowires 140, the projection of each described nano wire 142 on described the first semiconductor layer 100 overlaps.
In presents, " between each described set of nanowires 140; each described nano wire 142 is corresponding one by one " means: comprise two described set of nanowires 140 (being designated as respectively the first set of nanowires and the second set of nanowires) in described device, and described the first set of nanowires comprises that two described nano wires 142 are (along the direction away from described the first semiconductor layer 100, be denoted as 1421 and 1423) time, described the second set of nanowires also comprises two described nano wires 142 (direction along away from described the first semiconductor layer 100, be denoted as 1422 and 1424).
" the described nano wire 142 of each correspondence " means a combination that described nano wire 142 forms in the described nano wire 142 of in described the first set of nanowires one and described the second set of nanowires, the two is identical (as 1421 and 1422 with described the first semiconductor layer 100 distances, 1423 and 1424), each described nano wire 142 can only belong to a certain definite combination.
In the present embodiment, " described second semiconductor layer 122 of each correspondence " means 1221 and 1224,1222 and 1225 and 1223 and 1226 combinations that form.
" described the second semiconductor layer 122 described nano wire 142 corresponding with each of each correspondence joins one by one " means: each described nano wire 142 is connected to arbitrary described the second semiconductor layer 122 combinations; As nano wire 1421 and 1422 all can be connected to 1221 and 1224, nano wire 1423 is connected to 1222 and 1225, and nano wire 1424 is connected to 1223 and 1226.
Now, each described nano wire 142, each described semiconductor substrate, described grid 160, described side wall 162 and described contact hole, all with identical in previous embodiment, repeat no more.In above-described embodiment, only exemplarily provided the example that comprises two described nano wires 142 in each described set of nanowires 140, instruction according to above-described embodiment, those skilled in the art can know in each described set of nanowires 140 and comprise other execution modes more than two described nano wires 142, repeat no more.
The present invention also provides a kind of formation method of semiconductor structure, comprising:
At first, as shown in figure 14, on the first semiconductor layer 200, interval forms insulating barrier 202 and the second semiconductor layer 204 (to form semiconductor substrate), the number of described the second semiconductor layer 204 is at least three (in the present embodiment being three), each described second semiconductor layer 204 is sandwiched between insulating barrier 202, subsequently, on described semiconductor substrate, (on the described insulating barrier 202 away from described the first semiconductor layer 200) forms the first hard mask layer 206.
Described the first semiconductor layer 200 can be silicon substrate, and preferably, described the first semiconductor layer 200 is silicon epitaxy layer, and described the first semiconductor layer 200 also can be silicon-on-insulator (SOI).Described the second semiconductor layer 204 can be doping or unadulterated polysilicon or amorphous silicon.Be preferably the polysilicon (doped chemical can be B, P or As etc.) of doping, both be beneficial to when graphical described the second semiconductor layer 204 and obtained the high-quality figure, also be beneficial to and take described the second semiconductor layer 204 optimized device performance when basis provides source-drain area.Described insulating barrier 202 can be silicon oxide layer.Described the first hard mask layer 206 can be silicon nitride layer.
Can form described semiconductor substrate and described the first hard mask layer 206 by depositing operation.Can adopt chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or other applicable technique to carry out described electroless copper deposition operation.
Then, as shown in Figure 15 to 17, remove described first hard mask layer 206 (to form the first hard mask 208) of subregion, bar-shaped zone as shown, to expose the described insulating barrier 202 in described zone; Again predetermined in order to the zone (being nanowire region) that forms nano wire in, remove described semiconductor substrate, to expose described the first semiconductor layer 200.Can utilize anisotropic etch process (as RIE) carry out as described in removal operation.Now, only in being connected to described nanowire region, on the described semiconductor substrate of one group of opposite flank, be formed with the described first hard mask 208; And the described semiconductor substrate that is connected to another group opposite flank in described nanowire region only exposes described insulating barrier 202.
Again, as shown in Figure 18 to 20, form the 3rd semiconductor layer 220 on described the first semiconductor layer 200 exposed, can epitaxial growth technology form described the 3rd semiconductor layer 220, described the 3rd semiconductor layer 220 materials can be silicon or doped silicon; Subsequently, then remove described the 3rd semiconductor layer 220 of Partial Height, make the upper surface of the upper surface of described the 3rd semiconductor layer 220 lower than the described first hard mask 208, to expose the sidewall that is connected to described opposite flank in the described first hard mask 208; Can cmp (CMP) technique carry out described removal operation.
In the present embodiment, the upper surface of the described insulating barrier 202 that the upper surface of described the 3rd semiconductor layer 220 can expose with above-mentioned bar-shaped zone is concordant; In presents, term " upper surface " means to be parallel in the described semiconductor substrate of described the 3rd semiconductor layer 220 materials or exposure the side of described the first semiconductor layer 200; Term " concordant " means the difference in height of the two in the scope of fabrication error permission.
Again, as shown in Figure 21 to 23, form the second hard mask 218, the described second hard mask 218 is attached to sidewall and described the 3rd semiconductor layer 220 of expose portion that is connected to described opposite flank in the described first hard mask 208.Can depositing-etching technique form the described second hard mask 218; The described second hard mask 218 materials can be silicon nitride.
Subsequently, as shown in Figure 24 to 26, remove described the 3rd semiconductor layer 220 of part exposed, to form groove 240, described groove 240 exposes described the first semiconductor layer 200.Can RIE technique carry out described removal operation.
Then, as shown in Figure 27 to 29, form the 3rd hard mask 228, the described the 3rd hard mask 228 covers the sidewall of described groove 240.Can depositing-etching technique form the described the 3rd hard mask 228; The described the 3rd hard mask 228 materials can be silicon nitride.
Subsequently, as shown in Figure 30 to 32, remove in described semiconductor substrate the part away from described nanowire region, so that in described semiconductor substrate, the width at carrying the described first hard mask 208 places is less than the width that is connected to its elsewhere of described nanowire region, to expose described the first semiconductor layer 200, each described insulating barrier 202 and each described the second semiconductor layer 204.In presents, described width means shared wire space on the direction perpendicular to described nanowire region side, arbitrary zone.Can RIE technique carry out described removal operation.
Again, as shown in Figure 33 to 34, (the described insulating barrier 202 of this part is connected to described nanowire region one opposite flank to the described insulating barrier 202 in the described semiconductor substrate of removal carrying the described first hard mask 208; Now, each the described insulating barrier 202 that is connected to another opposite sides in described semiconductor substrate is also partly removed; For the described semiconductor substrate do not covered by the described first hard mask 208, the described insulating barrier 202 of its exposure also is removed, and then, make the described semiconductor substrate do not covered by the described first hard mask 208 expose described the second semiconductor layer 204), and the surface of described the 3rd semiconductor layer 220 of part of exposure carrying the described first hard mask 208; Then, carry out oxidation operation, on described the 3rd semiconductor layer 220 exposing, to form heterogeneous district 222 (now, described the second semiconductor layer 204 can prevent that described the 3rd semiconductor layer 220 of its covering is oxidized, that is, described the second semiconductor layer 204 can play the effect of mask), described heterogeneous district 222 materials are different with described the 3rd semiconductor layer 220 materials from described the second semiconductor layer 204 materials, in the present embodiment, described heterogeneous district 222 materials are silica; Now, described the second semiconductor layer 204 as mask also is oxidized to silica by part (top layer 2046 is oxidized); In addition, described the second semiconductor layer 204 exposed in described semiconductor substrate also is oxidized to heterogeneous district 222 (being silica).
Then, remove the described first hard mask 208, the described second hard mask 218 and the described the 3rd hard mask 228, described the second semiconductor layer 204 of take again is mask, remove described heterogeneous district 222, upper in described normal to a surface direction (as shown by arrows), described the 3rd semiconductor layer 220 is run through in described heterogeneous district 222; And then, remove described the second semiconductor layer 204 as mask, obtain the device architecture as shown in Figure 35 to 37.First make described the 3rd semiconductor layer 220 of part to be removed form described heterogeneous district 222, remove again described heterogeneous district 222 to remove described the 3rd semiconductor layer 220 of part and then graphical described the 3rd semiconductor layer 220, can make described heterogeneous district 222 mainly be formed at the zone that described mask exposes, and the zone that described mask is covered only produces less impact, be beneficial to after removing described heterogeneous district 222, the zone that described mask is covered only produces less lateral erosion, is beneficial to more accurately and shifts mask pattern on described the 3rd semiconductor layer 220.
It should be noted that, in other embodiments, after the surface of described the 3rd semiconductor layer 220 of part that exposes carrying the described first hard mask 208, described the second semiconductor layer 204 of take is mask, on described normal to a surface direction (as shown by arrows), adopt isotropic etching (as wet etching) technique remove as described in the 3rd semiconductor layer 220, (described the second semiconductor layer 204 just now exposed in described semiconductor substrate is not oxidized is heterogeneous district 222 also can to obtain the device architecture shown in similar Figure 35 to 37, in the device architecture formed, comprise three described the 3rd semiconductor layers 220), those skilled in the art can choose concrete technology according to actual needs flexibly.
Subsequently, as shown in figure 38, described device architecture is carried out to annealing operation.Particularly, can be at H
2or, under He atmosphere, carry out described annealing operation.Be beneficial to the part that makes to expose in described device architecture (as, in order to form the 3rd semiconductor layer 220 of nano wire) there is smooth surface, be beneficial in described nanowire surface and form uniform passivation layer (as hafnium base oxide layer or Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO), can provide uniform described gate dielectric layer utilizing described nano wire to form device and usining described passivation layer during as gate dielectric layer, be beneficial to optimized device performance.
Then, then form grid structure and contact hole on described device architecture, can form semiconductor structure.Wherein, the order that forms described grid structure and described contact hole can be selected according to flexible process design.
Particularly, the step that forms described grid structure comprises:
At first, as shown in Figure 39 to 42, remove described the second semiconductor layer 204 of part, to expose the part upper surface of each described the second semiconductor layer 204.
Wherein, the step of removing described the second semiconductor layer 204 of part comprises: first remove subregion on described the second semiconductor layer 204 of ground floor exposed, to expose the subregion of described the second semiconductor layer 204 of the second layer; Until remove subregion on described the second semiconductor layer 204 of N layer exposed, to expose the subregion of described the second semiconductor layer 204 of N+1 layer, N is more than or equal to 1 natural number.In the present embodiment, N equals 1.
Because described the 3rd semiconductor layer 220 is connected to described the second semiconductor layer 204, when removing corresponding described the second semiconductor layer 204, described the 3rd semiconductor layer 220 be sandwiched between corresponding described the second semiconductor layer 204 also will be removed, and described the 3rd semiconductor layer 220 will provide the channel region existed with the nano wire form in the semiconductor structure of follow-up formation, therefore, for as often as possible utilizing described the 3rd semiconductor layer 220, in removing each described second semiconductor layer 204 during subregion, the subregion that is connected to described the 3rd semiconductor layer 220 is tended to be retained.
; in the present embodiment; for removing the subregion in two-layer described the second semiconductor layer 204; each complete described second semiconductor layer 204 can be divided into 3 zones (being designated as respectively 2041,2042 and 2043); while making in the subregion of removing described the second semiconductor layer 204 of ground floor (remaining area 2041 and zone 2043); zone 2042 is removed; and expose the zone 2042 (insulating barrier between each layer of described the second semiconductor layer can, with corresponding technique removal, repeat no more) of described the second semiconductor layer 204 of the second layer.Can be by described the second semiconductor layer 204, forming resist layer, and adopt the mode of photoetching and the graphical described resist layer of etching technics, carry out described removal operation.
On each zone 2041,2042 and 2043 exposed, can form respectively contact hole, be beneficial to and control respectively each described the second semiconductor layer 204, then control respectively the different components that comprises each described the second semiconductor layer 204, be beneficial to technological design.Consider, each described second semiconductor layer 204 is used as source-drain electrode in the semiconductor structure of follow-up formation, and the upper surface of grid structure is usually above the upper surface of described source-drain electrode, the difference in height of the two is filled by interlayer dielectric layer, before forming described grid structure, process each described the second semiconductor layer 204 according to designing requirement in advance, be beneficial to when removing the subregion of each described the second semiconductor layer 204, reduce the impact of the height of described interlayer dielectric layer on exposure, lithographic accuracy.
What need emphasize is, for controlling respectively each described the second semiconductor layer 204, the arbitrary zone (2041 exposed, 2042 or 2043) on, need to form at least one contact hole, especially, for zone 2042, because it is connected with two described the 3rd semiconductor layers 220 (being nano wire), the semiconductor device that comprises these two described the 3rd semiconductor layers 220 will be by Synchronization Control, for controlling respectively each semiconductor device, can form at least two contact holes on zone 2042, and regional 2042 to obtain zone 2044 as described in cutting (as along BB ' cutting), 2045 o'clock, can form at least one contact hole and each zone on each zone (2044 or 2045) all is connected with corresponding described the second semiconductor layer 204.
Subsequently, as shown in Figure 43 to Figure 46, form first grid 260, described first grid 260 is connected to described the 3rd semiconductor layer 220 through gate dielectric layer 262.When adopting first grid technique to form described first grid 260, described first grid 260 materials can be the polysilicon of doping; When after employing, grid technique forms described first grid 260, described first grid 260 materials can be doping or unadulterated polysilicon or amorphous silicon.Described gate dielectric layer 262 materials can be hafnium base oxide layer or Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO.
Again, as shown in Figure 47 to Figure 50, form the first interlayer dielectric layer 264 of planarization, so that the first interlayer dielectric layer 264 of described planarization covers described the 3rd semiconductor layers 220 and exposes upper surface and the partial sidewall of described first grid 260, described partial sidewall is formed to downward-extension by described upper surface.
The step that forms the first interlayer dielectric layer 264 of described planarization can comprise: form the first interlayer dielectric layer, described the first interlayer dielectric layer covers described first grid; Described the first interlayer dielectric layer of planarization, to expose described first grid 260; Described the first interlayer dielectric layer of etching, with upper surface and the partial sidewall that exposes described first grid 260.Can CMP technique carry out described planarization operation, with RIE technique, carry out described etching operation.Now, the first interlayer dielectric layer 264 of described planarization covers each described second semiconductor layer 204 and each described the 3rd semiconductor layer 220.
Then, as shown in Figure 51 to Figure 54, form side wall 266, described side wall 266 is formed on the first interlayer dielectric layer 264 of described planarization and is attached on described partial sidewall.Can adopt depositing-etching technique to form described side wall 266.Described side wall 266 can comprise a kind of or its combination in silicon nitride, silica, silicon oxynitride or carborundum.Described side wall 266 can have sandwich construction.In the present embodiment, described side wall 266 is positioned at each described the 3rd semiconductor layer 220 (that is, set of nanowires) top; Be beneficial to after forming described side wall 266, can expose each described nano wire, then, in subsequent technique, the described side wall 266 of take is mask, can carry out metalized to each described nano wire, is beneficial to the resistance that reduces device.
Further, the described side wall 266 of take is mask, removes the first interlayer dielectric layer 264 of the described planarization of part, to expose described the 3rd semiconductor layer 220; Described the 3rd semiconductor layer 220 metallizes.Be beneficial to the resistance that reduces device.Wherein, the step of described the 3rd semiconductor layer 220 that metallizes can comprise: first form the first metal layer (as a kind of or its combination in Ti, Co, Cu, Ni), to cover described device architecture; Carry out again heat treatment operation, make described the 3rd semiconductor layer covered by described the first metal layer in described device architecture form metal silicide layer (now, the top layer of described first grid and each described the second semiconductor layer also all is formed with metal silicide layer); Remove unreacted described the first metal layer.
As shown in Figure 55 to Figure 58, after forming described grid structure, can continue to form contact hole 280, specifically comprise: at first, form the second interlayer dielectric layer 268, described the second interlayer dielectric layer 268 covers described the first interlayer dielectric layer (that is, covering each described second semiconductor layer 204 and each described the 3rd semiconductor layer 220); It should be noted that, while adopting rear grid technique, after forming described second medium layer 268, also comprise: substitute described first grid with second grid, described second grid material is metal material.Described second grid comprises workfunction layers and the second metal level, described the second metal level is formed at (all not shown in described workfunction layers and described the second metal level figure) on described workfunction layers, wherein, described workfunction layers can be a kind of or its combination in TiN, TiAlN, TaN, TaAlN, TaC; Described the second metal level can be a kind of or its combination in Ti, Co, Ni, Al, W; Subsequently, at the interior formation contact hole of described the second interlayer dielectric layer 268, described contact hole (through metal silicide 282) is connected to the subregion of each described the second semiconductor layer 204 upper surfaces.Wherein, the step that forms described contact hole 280 comprises: at the interior formation groove of described the second interlayer dielectric layer 268, described groove exposes the subregion of each described the second semiconductor layer 204 upper surfaces; Fill described groove with the 3rd metal level.Described the 3rd metal level comprises bed course (a kind of or its combination in Ta, TaN, Ti, TiN) and filling metal level (a kind of or its combination in W, Al, Cu, TiAl), and described filling metal level is formed on described bed course.It should be noted that, in the description of the various embodiments described above, the second semiconductor layer 204 is contained the second semiconductor layer 2041, the second semiconductor layer 2042 and/or the second semiconductor layer 2043.
In addition, in other embodiments, the step that forms described contact hole on described device architecture comprises: at first, remove described the second semiconductor layer of part, with the part upper surface (identical with step in previous embodiment, as to repeat no more) that exposes each described the second semiconductor layer; Then, form the 3rd interlayer dielectric layer, described the 3rd interlayer dielectric layer covers each described the second semiconductor layer; Again, in described the 3rd interlayer dielectric layer, form contact hole, described contact hole is connected to the subregion (identical with step in previous embodiment, as to repeat no more) of each described upper surface of exposure.Now, can any traditional technique form described grid structure.
In presents, can adopt and form each interlayer dielectric layer (as the first interlayer dielectric layer, the second interlayer dielectric layer and the 3rd interlayer dielectric layer) as CVD and/or other suitable technique, each described inter-level dielectric layer material can comprise a kind of or its combination in silica glass, fluorine silex glass, Pyrex, phosphorosilicate glass, boron-phosphorosilicate glass, carbon silex glass, low K dielectrics material (as black diamond, coral etc.).Each described interlayer dielectric layer can have sandwich construction.
Need emphasize, range of application of the present invention is not limited to technique, structure, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.According to disclosure of the present invention; those skilled in the art will easily understand; for the technique, mechanism, manufacture, material composition, means, method or the step that have existed or be about to develop at present later; they carry out the corresponding embodiment that describes with the present invention substantially identical function or obtain cardinal principle identical as a result the time; according to instruction of the present invention; can be applied them, and do not broken away from the present invention's scope required for protection.
Claims (14)
1. the formation method of a semiconductor structure, is characterized in that, comprising:
Determine nanowire region and form semiconductor substrate and the 3rd semiconductor layer on the first semiconductor layer, described the 3rd semiconductor layer covers described nanowire region and embeds in described semiconductor substrate; Described semiconductor substrate comprises at least three the second semiconductor layers, and each described second semiconductor layer is sandwiched between insulating barrier; Described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material, is formed with the first hard mask in being connected to described nanowire region on the described semiconductor substrate of one group of opposite flank;
Form the second hard mask, the described second hard mask is attached to sidewall and described the 3rd semiconductor layer of expose portion that is connected to described opposite flank in the described first hard mask;
Remove described the 3rd semiconductor layer of part exposed, to form groove;
Form the 3rd hard mask, the described the 3rd hard mask covers the sidewall of described groove, and the described first hard mask, the described second hard mask are different from described insulating layer material with the described the 3rd hard mask;
Removal is away from the described semiconductor substrate of the part of described nanowire region; be less than so that be connected to the width of described opposite sides in described semiconductor substrate the width that is connected to other places, side, to expose described the first semiconductor layer, each described insulating barrier and each described the second semiconductor layer;
Removal is connected in described semiconductor substrate the described insulating barrier that is connected to described opposite sides, and the surface of described the 3rd semiconductor layer of part of exposure carrying the described first hard mask, after removing the described first hard mask, the described second hard mask and the described the 3rd hard mask, on described normal to a surface direction, described the second semiconductor layer of take is mask, remove described the 3rd semiconductor layer, then remove described the second semiconductor layer as mask.
2. method according to claim 1, is characterized in that, also comprises:
Remove described the second semiconductor layer of part, described part the second semiconductor layer is positioned at the zone that is connected to described groove, to expose the part upper surface of each described the second semiconductor layer;
Form first grid, described first grid is connected to described the 3rd semiconductor layer through gate dielectric layer, and described first grid material is semi-conducting material and different from described the 3rd semiconductor layer material;
Form the first interlayer dielectric layer of planarization, so that the first interlayer dielectric layer of described planarization covers described the 3rd semiconductor layer and exposes upper surface and the partial sidewall of described first grid, described partial sidewall is formed to downward-extension by described upper surface;
Form side wall, described side wall is formed on the first interlayer dielectric layer of described planarization and is attached on described partial sidewall.
3. method according to claim 2, is characterized in that, also comprises:
Take described side wall as mask, remove the first interlayer dielectric layer of the described planarization of part, to expose described the 3rd semiconductor layer;
Described the 3rd semiconductor layer metallizes.
4. method according to claim 3, is characterized in that, also comprises:
Form the second interlayer dielectric layer, described the second interlayer dielectric layer covers each described second semiconductor layer and each described the 3rd semiconductor layer;
Form contact hole in described the second interlayer dielectric layer, described contact hole is connected to the subregion of each described the second semiconductor layer upper surface.
5. according to the described method of any one in claim 2 to 4, it is characterized in that, forming described side wall to exposing between described the 3rd semiconductor layer, also comprise: substitute described first grid with second grid, described second grid material is metal material.
6. method according to claim 1, is characterized in that, also comprises:
Remove described the second semiconductor layer of part, to expose the part upper surface of each described the second semiconductor layer;
Form the 3rd interlayer dielectric layer, described the 3rd interlayer dielectric layer covers each described the second semiconductor layer;
Form contact hole in described the 3rd interlayer dielectric layer, described contact hole is connected to the subregion of each described upper surface of exposure.
7. according to the described method of claim 2 or 6, it is characterized in that, the step of removing described the second semiconductor layer of part comprises:
Remove subregion on described the second semiconductor layer of ground floor exposed, to expose the subregion of described the second semiconductor layer of the second layer;
Until remove subregion on described the second semiconductor layer of N layer exposed, to expose the subregion of described the second semiconductor layer of N+1 layer, N is more than or equal to 1 natural number.
8. according to the described method of claim 2 or 6, it is characterized in that, also comprise: along being parallel to described the 3rd semiconductor layer and cutting described the first semiconductor layer perpendicular to the direction of described the first semiconductor layer, to obtain two semiconductor structures, in each described semiconductor structure, described contact hole is connected to the subregion of each described upper surface.
9. method according to claim 1, is characterized in that, determines nanowire region and form semiconductor substrate and the step of described the 3rd semiconductor layer comprises on the first semiconductor layer:
On the first semiconductor layer, order forms semiconductor substrate and the first hard mask layer; described semiconductor substrate comprises at least three the second semiconductor layers; each described second semiconductor layer is sandwiched between insulating barrier, and described the first hard mask layer is formed on described semiconductor substrate;
Determine nanowire region; and the described semiconductor substrate in removal described the first hard mask layer of part and described nanowire region; to form the first hard mask on the described semiconductor substrate of one group of opposite flank in being connected to described nanowire region, and expose described the first semiconductor layer;
Form the 3rd semiconductor layer on described the first semiconductor layer exposed, the upper surface of described the 3rd semiconductor layer is lower than the upper surface of the described first hard mask, to expose the sidewall that is connected to described opposite flank in the described first hard mask, described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material.
10. method according to claim 1, is characterized in that, the step of removing described the 3rd semiconductor layer of part comprises:
Form heterogeneous district on described the 3rd semiconductor layer exposed, described heterogeneous district material is different with described the 3rd semiconductor layer material from described the second semiconductor layer material;
Described the second semiconductor layer of take is mask, removes described heterogeneous district, and on described normal to a surface direction, described the second semiconductor layer is run through in described heterogeneous district.
11. method according to claim 10 is characterized in that: with oxidation technology, form described heterogeneous district.
12. method according to claim 1, is characterized in that, also comprises: carry out annealing operation.
13. method according to claim 12 is characterized in that: at H
2or, under He atmosphere, carry out described annealing operation.
14. method according to claim 1 is characterized in that: when described the first semiconductor layer material is silicon or doped silicon, described the second semiconductor layer is doping or unadulterated polysilicon or amorphous silicon, and described the 3rd semiconductor layer is silicon or doped silicon.
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| CN1893079A (en) * | 2005-06-28 | 2007-01-10 | 三星电子株式会社 | CMOS device, method of manufacturing the same, and memory including cmos device |
| CN101438415A (en) * | 2006-05-05 | 2009-05-20 | 梅尔斯科技公司 | Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods |
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| CN1893079A (en) * | 2005-06-28 | 2007-01-10 | 三星电子株式会社 | CMOS device, method of manufacturing the same, and memory including cmos device |
| CN101438415A (en) * | 2006-05-05 | 2009-05-20 | 梅尔斯科技公司 | Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods |
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