CN102446842A - Method for reducing interlayer capacitance of metal wiring layer in dual damascene technology - Google Patents
Method for reducing interlayer capacitance of metal wiring layer in dual damascene technology Download PDFInfo
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- CN102446842A CN102446842A CN2011103562806A CN201110356280A CN102446842A CN 102446842 A CN102446842 A CN 102446842A CN 2011103562806 A CN2011103562806 A CN 2011103562806A CN 201110356280 A CN201110356280 A CN 201110356280A CN 102446842 A CN102446842 A CN 102446842A
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- metal wiring
- wiring layer
- dual damascene
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Abstract
The invention discloses a method; according to the method, a dielectric constant of a dielectric layer is reduced, so that interlayer capacitance of a metal wiring layer in a dual damascene technology is reduced. The method comprises the following steps that: step one, a dielectric layer is deposed; step two, a groove is etched on the dielectric layer; step three, a metal wiring layer is deposed, wherein the metal wiring layer is used to seal the opening of the groove so as to form a cavity; step four, a dual damascene photoethcing and etching technology is employed to form a through hole and a metal wiring groove on the metal wiring layer, wherein the position of through hole is deviated from the position of the groove; and step five, a dual damascene copper electroplating and chemical-mechanical planarization technology is employed to complete filling and planarization of the through hole and the metal wiring groove. According to the invention, during the manufacturing process of a damascene structure, a cavity is manufactured in a dielectric layer so as to reduce a dielectric constant of the dielectric layer, so that interlayer capacitance of a metal wiring layer is reduced.
Description
Technical field
The present invention relates to a kind of method that reduces metal wiring layer layer capacitance in the dual damascene process, relate in particular to a kind of dielectric constant that reduces dielectric layer, thereby reduce the method for metal wiring layer layer capacitance in the dual damascene process.
Background technology
In field of microelectronic fabrication, along with the integrated development of integrated circuit, the live width and the thickness of plain conductor constantly reduce, and the thickness of dielectric layers between the interlayer lead is also more and more thinner simultaneously, and the time-delay between plain conductor at this moment becomes an adverse effect of can not ignore.And the effective ways that reduce to postpone between plain conductor reduce plain conductor resistivity and dielectric layer dielectric constant exactly.At present in 90nm and following processing procedure, generally adopt copper conductor substitution of Al lead to reduce resistivity.For dielectric layer, then adopt the material such as the BD1 of low-k, BD2 etc. substitute traditional oxide (oxide) dielectric layer, to reduce the dielectric layer dielectric constant.How under the situation that does not change the dielectric layer material, can reduce the dielectric constant of dielectric layer equally, reaching the effect that reduces to postpone between plain conductor is a difficult problem that faces at present.
Summary of the invention
To the problem of above-mentioned existence, the purpose of this invention is to provide a kind ofly under the situation that does not change the dielectric layer material, be same as the dielectric constant that can reduce dielectric layer, realize the method that reduces to postpone between plain conductor.
The objective of the invention is to realize through following technical proposals:
A kind of method that reduces metal wiring layer layer capacitance in the dual damascene process wherein, comprises the steps,
Step 1, dielectric layer deposited feeds a certain amount of growth gasses under high vacuum state, under the radio frequency power source effect, form plasma, gas-phase nucleation on the substrate that heats then, deposit goes out dielectric layer on required substrate;
Step 2, etching groove on dielectric layer;
Step 3, the depositing metal wiring layer wherein makes said metal wiring layer seal said groove opening, thereby forms the cavity;
Step 4, utilization dual damascene photoetching and etching technics form through hole and hardware cloth wire casing, the position of the said groove of position deviation of wherein said through hole at said metal wiring layer;
Step 5, utilization dual damascene copper is electroplated and chemical-mechanical planarization technology, accomplishes the filling and the planarization of through hole and hardware cloth wire casing.
The above-mentioned method that reduces metal wiring layer layer capacitance in the dual damascene process, wherein, the density of said groove is 5%-90%.
The method that reduces metal wiring layer layer capacitance in the dual damascene process of the above, wherein, the technology of said depositing metal wiring layer is pecvd process or SACVD technology.
The above-mentioned method that reduces metal wiring layer layer capacitance in the dual damascene process, wherein, the material of said dielectric layer be Oxide, PSG, FSG, BD1 or BD2 any one.
The above-mentioned method that reduces metal wiring layer layer capacitance in the dual damascene process, wherein, surface contact angle is 270
0
Compared with present technology; Beneficial effect of the present invention is: in making the damascene structure process; Under the situation that does not change the dielectric layer material,, reach the dielectric constant that reduces dielectric layer equally, thereby realize reducing metal line interlayer capacitance delays through in dielectric layer, making the cavity.
Description of drawings
Fig. 1 is a kind of method flow sketch map that reduces metal wiring layer layer capacitance in the dual damascene process of the present invention.
Embodiment
Below in conjunction with schematic diagram and concrete operations embodiment the present invention is described further.
As shown in Figure 1; A kind of method that reduces metal wiring layer layer capacitance in the dual damascene process of the present invention; Comprise the steps: at first to be utilized in and feed a certain amount of growth gasses under the high vacuum state; Under the radio frequency power source effect, form plasma, gas-phase nucleation on the substrate of heating then, deposit goes out dielectric layer on required substrate; Then, on said dielectric layer, utilize etching technics etching place a certain size with the groove of shape, the shape size of said groove and density must be able to make the follow-up metal wiring layer deposit can the effective closure opening; Then; The good depositing technics depositing metal wiring layer of utilization sealing property; In deposition process, must guarantee groove on the closed dielectric layer; Make it in groove, to form the cavity, must make the upper end in cavity certain distance arranged simultaneously, guarantee in the etching process of follow-up metal wiring layer, to be unlikely to etch into the cavity apart from metal wiring layer; In the 4th step, the dual damascene photoetching and the etching technics of utilization standard make through hole and hardware cloth wire casing, and the position of through hole and groove can not be overlapping, and promptly through hole should depart from the position of groove; At last, the dual damascene copper of utilization standard is electroplated and chemical-mechanical planarization technology, accomplishes the filling and the planarization of through hole and hardware cloth wire casing.So far, in dielectric layer, make the cavity, thereby reduce the dielectric constant of dielectric layer, and then realize reducing the electric capacity of metal line interlayer.
For guaranteeing that the metal wiring layer deposit can the effective closure opening, the density of groove is 5%-90%.
Groove middle part form the cavity depositing technics can be PECVD, any effectively depositing technics of closed groove such as SACVD.Deposition materials can be Oxide, PSG, and FSG, BD1, BD2 etc. meet the material of the membranous requirement of metal wiring layer.
In pecvd process or SACVD technology, the cavity space in chemical vapour deposition reaction chamber is little, and atmosphere has the diverse location film forming thickness relevant with surface contact angle; Surface contact angle and surface mobility are directly to influence the through hole porefilling capability.The easier more greatly film forming of surface contact angle, the more little difficult more film forming of contact angle, thus form the suspension film in 270 ゜ positions easily and seal, thus the step coverage that reduces sidewall is to reach the purpose that forms hole in the through hole.In addition; Method that also can be through the rising reaction pressure is to reach the surface mobility that reduces reactant molecule; Thereby the mean free path that shortens molecule (forms the suspension film thereby make reactant molecule arrive 270 ゜ positions; Also can reach the step coverage that reduces sidewall, in through hole, form the purpose of hole.
More than specific embodiment of the present invention is described in detail, but the present invention is not restricted to the specific embodiment of above description, it is just as example.To those skilled in the art, any to this equivalent modifications of carrying out and alternative also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of having done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (6)
1. a method that reduces metal wiring layer layer capacitance in the dual damascene process is characterized in that, comprise the steps,
Step 1, dielectric layer deposited feeds a certain amount of growth gasses under high vacuum state, under the radio frequency power source effect, form plasma, gas-phase nucleation on the substrate that heats then, deposit goes out dielectric layer on required substrate;
Step 2, etching groove on said dielectric layer;
Step 3, the depositing metal wiring layer wherein makes said metal wiring layer seal said groove opening, thereby forms the cavity;
Step 4, utilization dual damascene photoetching and etching technics form through hole and hardware cloth wire casing, the position of the said groove of position deviation of wherein said through hole at said metal wiring layer;
Step 5, utilization dual damascene copper is electroplated and chemical-mechanical planarization technology, accomplishes the filling and the planarization of through hole and hardware cloth wire casing.
2. the method that reduces metal wiring layer layer capacitance in the dual damascene process according to claim 1 is characterized in that, the density of said groove is 5%-90%.
3. the method that reduces metal wiring layer layer capacitance in the dual damascene process according to claim 1 and 2 is characterized in that, the technology of said depositing metal wiring layer is pecvd process or SACVD technology.
4. the method that reduces metal wiring layer layer capacitance in the dual damascene process according to claim 1 and 2 is characterized in that, the material of said dielectric layer be Oxide, PSG, FSG, BD1 or BD2 any one.
5. the method that reduces metal wiring layer layer capacitance in the dual damascene process according to claim 3 is characterized in that, the material of said dielectric layer be Oxide, PSG, FSG, BD1 or BD2 any one.
6. the method that reduces metal wiring layer layer capacitance in the dual damascene process according to claim 3 is characterized in that, surface contact angle is 270
0
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103562806A CN102446842A (en) | 2011-11-11 | 2011-11-11 | Method for reducing interlayer capacitance of metal wiring layer in dual damascene technology |
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| CN2011103562806A CN102446842A (en) | 2011-11-11 | 2011-11-11 | Method for reducing interlayer capacitance of metal wiring layer in dual damascene technology |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928095A (en) * | 2021-02-03 | 2021-06-08 | 长鑫存储技术有限公司 | Interconnection structure, preparation method thereof and semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040099951A1 (en) * | 2002-11-21 | 2004-05-27 | Hyun-Mog Park | Air gap interconnect structure and method |
| US20050208752A1 (en) * | 2004-03-19 | 2005-09-22 | Colburn Matthew E | Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby |
| CN1996588A (en) * | 2005-12-31 | 2007-07-11 | 上海集成电路研发中心有限公司 | A copper-gas media Damascus structure and its making method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040099951A1 (en) * | 2002-11-21 | 2004-05-27 | Hyun-Mog Park | Air gap interconnect structure and method |
| US20050208752A1 (en) * | 2004-03-19 | 2005-09-22 | Colburn Matthew E | Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby |
| CN1996588A (en) * | 2005-12-31 | 2007-07-11 | 上海集成电路研发中心有限公司 | A copper-gas media Damascus structure and its making method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928095A (en) * | 2021-02-03 | 2021-06-08 | 长鑫存储技术有限公司 | Interconnection structure, preparation method thereof and semiconductor structure |
| CN112928095B (en) * | 2021-02-03 | 2022-03-15 | 长鑫存储技术有限公司 | Interconnection structure, preparation method thereof and semiconductor structure |
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Application publication date: 20120509 |