CN102437730B - Anti-ringing circuit applied to high-voltage boosting type DC-DC (Direct Current to Direct Current) converter - Google Patents

Abstract

The invention discloses an anti-ringing circuit applied to a high-voltage boosting type DC-DC (Direct Current to Direct Current) converter, mainly solving the problem that the anti-ringing circuit in the prior art cannot work under high-voltage conditions. The circuit comprises a control circuit, a level shift circuit, a high-voltage PMOS (P-channel Metal Oxide Semiconductor) tube M3 and a high-voltage PMOS tube M4, wherein source electrodes of the high-voltage PMOS tubes M3 and M4 are connected with each other; an output voltage VH is connected with the input end of the level shift circuit; drain electrodes of the high-voltage PMOS tubes M3 and M4 are respectively connected with two ends of an inductor; output signals of the control circuit are connected with grid electrodes of the high-voltage PMOS tubes M3 and M4, so as to control the conduction and the stopping of the M3 and the M4 and eliminate ringing; and the input end of the control circuit is connected with the level shift circuit, so as to assure that voltage differences between the source electrodes and the grid electrodes of the high-voltage PMOS tubes M3 and M4 are not more than 5 V and prevent the high-voltage PMOS tubes M3 and M4 from being punctured due to the overlarge voltage differences between the source electrodes and the grid electrodes. The anti-ringing circuit provided by the invention can work under the high-voltage conditions so that the ringing phenomenon can be eliminated, the noises are reduced, the electromagnetic interferences on the system are reduced, and the performance of the DC-DC converter is improved; and therefore, the anti-ringing circuit can be applied to the high-voltage boosting type DC-DC converter.

Description

Be applied to the anti-ringing circuit in high voltage step-up type DC-DC transducer

Technical field

The invention belongs to electronic circuit technology field, relate to analog integrated circuit, particularly a kind of anti-ringing circuit being applied in high voltage step-up type DC-DC transducer.

Background technology

DC-DC converter can keep very high efficiency within the scope of very wide input and output voltage, is applied in widely in all kinds of portable type electronic products.But because DC-DC converter is operated on off state, larger output noise may be to some sensitive circuits, such as radio circuit impacts, especially when DC-DC is operated in inductive current DCM, in the time that switching tube is closed, the LC loop being made up of inductance and parasitic capacitance can produce the serious higher-order of oscillation, forms ring.The existence of ring can produce noise and electromagnetic interference problem, affects the normal work of system.Therefore be necessary to adopt special anti-ringing circuit to carry out ring decay.Wherein the most frequently used method is the object that inductance shorted on both ends or a small resistor in parallel is reached to antivibration bell.

Existing antivibration bell circuit is mainly used in the boosting type converter of some buck DC-DC transducers or low pressure, and as shown in Figure 1, wherein antivibration bell main circuit will comprise control circuit, and PMOS manages M ₃and PMOS pipe M ₄.When antivibration bell circuit working, control circuit output signal V _cfor zero level, make PMOS pipe M ₃with PMOS pipe M ₄conducting, and then make inductance two terminal shortcircuits, reach the object of antivibration bell; When anti-ringing circuit is out-of-work, control circuit output signal V _cvoltage equals PMOS pipe M ₃with PMOS pipe M ₄source voltage, make PMOS pipe M ₃with PMOS pipe M ₄cut-off, does not affect the normal work of DC-DC transducer.

PMOS pipe M in Fig. 1 in anti-ringing circuit ₃with PMOS pipe M ₄what adopt is low pressure PMOS pipe, can only bear the pressure reduction of 5V between the source electrode of low pressure PMOS pipe and drain electrode, also can only bear the pressure reduction of 5V between source electrode and grid, and therefore can only be applied to input and output is in the DC-DC transducer of low pressure.But, even PMOS is managed to M ₃with PMOS pipe M ₄change high voltage PMOS pipe into, such structure can not be applied in high voltage step-up type DC-DC converter.Can bear high voltage because normally used high voltage PMOS pipe only has between source electrode and drain electrode, and between source electrode and grid, can only bear the pressure reduction of 5V.In the time of antivibration bell circuit working, PMOS manages M ₃with PMOS pipe M ₄grid be 0 level, and PMOS pipe M ₃with PMOS pipe M ₄source level after conducting is but high pressure, thereby makes the pressure reduction between source electrode and the grid of PMOS pipe be greater than 5V, causes PMOS pipe over-voltage breakdown, damages circuit.

Summary of the invention

The object of the invention is to for above-mentioned deficiency of the prior art, a kind of anti-ringing circuit being applied in high voltage step-up type DC-DC transducer is proposed, during so that work in the situation of step-up DC-DC transducer high pressure, can eliminate ringing, reduce noise, reduce the electromagnetic interference to system, improve the performance of DC-DC transducer.

For achieving the above object, the anti-ringing circuit for high voltage step-up type DC-DC transducer of the present invention comprises that control circuit, PMOS manage M ₃with PMOS pipe M ₄, this PMOS pipe M ₃and M ₄source electrode be connected, output voltage V _hbe connected to the input of level shift circuit, drain electrode connects respectively the two ends of inductance; The output signal V of control circuit _cbe connected to high voltage PMOS pipe M ₃and M ₄grid, for controlling M ₃and M ₄conducting and cut-off, eliminate ring; It is characterized in that: PMOS manages M ₃with PMOS pipe M ₄all adopt withstand voltage between source electrode and drain electrode to be greater than the high voltage PMOS pipe of 12V; The input of control circuit is connected with level shift circuit, for guaranteeing the output signal V of control circuit _cthe pressure reduction that logic height changes is no more than 5V, prevents high voltage PMOS pipe M ₃and M ₄because of excessive the puncturing of pressure reduction of source electrode and grid;

Described level shift circuit, comprises that withstand voltage between bias current source circuit, drain electrode and source electrode is greater than the high pressure NMOS pipe M of 12V ₅, two high voltage PMOS pipe M ₈, M ₉the low pressure PMOS that is all less than 5V with two each utmost point withstand voltages manages M ₆, M ₇; This high pressure NMOS pipe M ₅drain electrode connect the output voltage V of DC-DC _oUT, grid meets high voltage PMOS pipe M ₃and M ₄the output voltage V of source electrode _h, source electrode and low pressure PMOS pipe M ₆, M ₇after series connection, be connected to high voltage PMOS pipe M ₈source electrode; High voltage PMOS pipe M ₈grid and high voltage PMOS pipe M ₉grid connect, high voltage PMOS pipe M ₉drain electrode connecting to neutral level, source electrode output voltage V _l, be connected to control circuit; This bias current source circuit has two outputs, respectively with high voltage PMOS pipe M ₈drain electrode and high voltage PMOS pipe M ₉source electrode be connected, for these two high voltage PMOS pipes provide constant current.

Described bias current source circuit, comprises current source I ₁, resistance R, three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂, two high voltage PMOS pipe M ₁₈, M ₁₉, three each utmost point withstand voltages are all less than 5V low pressure NMOS pipe M ₁₃, M ₁₄, M ₁₅with two low pressure PMOS pipe M ₁₆, M ₁₇;

Described high pressure NMOS pipe M ₁₀with low pressure NMOS pipe M ₁₃be connected in series high pressure NMOS pipe M ₁₁with low pressure NMOS pipe M ₁₄be connected in series; High pressure NMOS pipe M ₁₂with low pressure NMOS pipe M ₁₅be connected in series; Three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂grid be connected, three low pressure NMOS pipe M ₁₃, M ₁₄, M ₁₅grid be connected, source electrode connecting to neutral level, form common-source common-gate current mirror; High pressure NMOS pipe M ₁₂drain electrode be connected to high voltage PMOS pipe M ₈drain electrode, be high voltage PMOS pipe M ₈constant current I is provided ₂;

Described high voltage PMOS pipe M ₁₈with low pressure PMOS pipe M ₁₆be connected in series high voltage PMOS pipe M ₁₉with low pressure PMOS pipe M ₁₇be connected in series; High voltage PMOS pipe M ₁₈with M ₁₉grid be connected, low pressure PMOS manages M ₁₆and M ₁₇grid be connected, source electrode connects the output voltage V of DC-DC _oUT, form common-source common-gate current mirror; High voltage PMOS pipe M ₁₈drain electrode be connected to high pressure NMOS pipe M ₁₁drain electrode, high voltage PMOS pipe M ₁₉drain electrode be connected to high voltage PMOS pipe M ₉source electrode, be high voltage PMOS pipe M ₉constant current I is provided ₃.

Described control circuit, comprises inverter INV, comparator, clamp circuit and output circuit; The input of inverter INV is connected with the positive input of comparator, and meets control signal K, and the output signal XK of inverter INV is connected to the reverse input end of comparator; The output of comparator and high voltage PMOS pipe M ₃and M ₄source voltage V _hbetween be connected with clamp circuit; The input of output circuit is connected with the output of comparator, and output is connected to high voltage PMOS pipe M ₃and M ₄grid.

Described comparator, comprises two high pressure NMOS pipe M ₂₀, M ₂₁, two low pressure PMOS pipe M ₂₂, M ₂₃with current source I ₄; This high pressure NMOS pipe M ₂₀, M ₂₁as the input of this comparator to pipe, high pressure NMOS pipe M ₂₀grid meet input control signal K, high pressure NMOS pipe M ₂₁grid meet the output signal XK of inverter INV; Current source I ₄one end connecting to neutral level, the other end is connected to this high pressure NMOS pipe M ₂₀and M ₂₁source electrode, for comparator provides tail current; Low pressure PMOS manages M ₂₂and M ₂₃grid be connected, source electrode meets high voltage PMOS pipe M ₃and M ₄source voltage V _h, composition active electric current mirror, the load of device as a comparison; Low pressure PMOS manages M ₂₂drain electrode be connected to high pressure NMOS pipe M ₂₀drain electrode, low pressure PMOS manages M ₂₃drain electrode be connected to high pressure NMOS pipe M ₂₁drain electrode, the output of device as a comparison.

Described clamp circuit, comprises three low pressure PMOS pipe M ₂₄, M ₂₅and M ₂₆, these three low pressure PMOS pipes are connected in series in high voltage PMOS pipe M ₃, M ₄source voltage V _hwith between the output of comparator, their grid is connected with drain electrode separately respectively, form diode connection, comparator output voltage is carried out to clamp.

Described output circuit, comprises 2 low pressure PMOS pipe M ₂₇, M ₂₉with 2 low pressure NMOS pipe M ₂₈, M ₃₀; This low pressure PMOS manages M ₂₇with low pressure NMOS pipe M ₂₈grid be connected and be connected to the output of comparator, low pressure PMOS manages M ₂₇source electrode meet high voltage PMOS pipe M ₃and M ₄source voltage V _h, low pressure NMOS manages M ₂₈source electrode connect the output voltage V of level shift circuit _l, low pressure PMOS manages M ₂₇with low pressure NMOS pipe M ₂₈drain electrode be connected, and be connected to low pressure PMOS pipe M ₂₉with low pressure NMOS pipe M ₃₀grid; Low pressure PMOS manages M ₂₉source electrode meet high voltage PMOS pipe M ₃and M ₄source voltage V _h, low pressure NMOS manages M ₃₀source electrode connect the output voltage V of level shift circuit _l, low pressure PMOS manages M ₂₉with low pressure NMOS pipe M ₃₀drain electrode be connected, the voltage V of output _cbe connected to high voltage PMOS pipe M ₃with high voltage PMOS pipe M ₄grid.

The present invention compared with prior art has the following advantages:

The present invention is owing to having adopted high voltage PMOS pipe belt to replace low pressure PMOS pipe, and the input at control circuit is connected with level shift circuit, can guarantee that the pressure reduction of high voltage PMOS tube grid and source electrode is in its withstand voltage, anti-ringing circuit can be worked under the condition of high pressure, eliminate the ringing of high voltage step-up type DC-DC transducer, reduce noise, reduced the electromagnetic interference to system, improved the performance of DC-DC transducer.

Accompanying drawing explanation

Fig. 1 is the step-up DC-DC commutator principle figure with the anti-ringing circuit of tradition;

Fig. 2 is the step-up DC-DC commutator principle figure with anti-ringing circuit of the present invention;

Fig. 3 is level shift circuit structure chart in the present invention;

Fig. 4 is control circuit structure chart in the present invention.

Embodiment

Below in conjunction with accompanying drawing and embodiment, the invention will be further described.

With reference to figure 2, high voltage step-up type DC-DC transducer mainly comprises anti-ringing circuit of the present invention, high pressure NMOS pipe M ₁, high voltage PMOS pipe M ₂, inductance L and output capacitance C; One termination input power VIN of inductance L, the other end is connected to high pressure NMOS pipe M ₁with high voltage PMOS pipe M ₂drain electrode, high pressure NMOS pipe M ₁grid connect and drive signal VC1, source electrode connecting to neutral level; High voltage PMOS pipe M ₂grid connect and drive signal VC2, source electrode connects one end of output capacitance C, as the output of step-up DC-DC.With reference to the maximum voltage value in DC-DC converter application, determine the withstand voltage of high voltage PMOS pipe, withstand voltage is greater than 12V conventionally.

Described anti-ringing circuit of the present invention, comprises control circuit, level shift circuit, high voltage PMOS pipe M ₃and M ₄; D1 and D2 are respectively high voltage PMOS pipe M ₃and M ₄parasitic diode; This PMOS pipe M ₃and M ₄source electrode be connected, output voltage V _hbe connected to the input of level shift circuit, drain electrode connects respectively the two ends of inductance L; The output signal V of this control circuit _cbe connected to high voltage PMOS pipe M ₃and M ₄grid, control M ₃and M ₄conducting and cut-off, eliminate ring; This level shift circuit is provided with two inputs and an output, and first input end meets high voltage PMOS pipe M ₃and M ₄source voltage V _h, the output voltage V of the second input termination DC-DC transducer _oUT, the output voltage V of output _lbe connected to control circuit, so that the output signal V of control circuit to be provided _clogic low, guarantee the output signal V of control circuit _cthe pressure reduction that logic height changes is no more than 5V, prevents high voltage PMOS pipe M ₃and M ₄because of excessive the puncturing of pressure reduction of source electrode and grid.

With reference to figure 3, described level shift circuit, comprises bias current source circuit, high pressure NMOS pipe M ₅, two high voltage PMOS pipe M ₈, M ₉the low pressure PMOS that is all less than 5V with two each utmost point withstand voltages manages M ₆, M ₇; This high pressure NMOS pipe M ₅drain electrode connect the output voltage V of DC-DC _oUT, grid meets high voltage PMOS pipe M ₃and M ₄the output voltage V of source electrode _h, source electrode and low pressure PMOS pipe M ₆, M ₇after series connection, be connected to high voltage PMOS pipe M ₈source electrode; High voltage PMOS pipe M ₈grid and high voltage PMOS pipe M ₉grid connect, high voltage PMOS pipe M ₉drain electrode connecting to neutral level, source electrode output voltage V _l, be connected to control circuit; This bias current source circuit has two outputs, respectively with high voltage PMOS pipe M ₈drain electrode and high voltage PMOS pipe M ₉source electrode be connected, for these two high voltage PMOS pipes provide constant current.Level shift circuit output voltage V _lfor:

V _l=V _h-V _gS5-V _sG6-V _sG7-V _sG8+ V _sG9(1) wherein, V _gS5for high pressure NMOS pipe M ₅grid-source voltage, V _sG6for low pressure PMOS pipe M ₆source electrode-grid voltage, V _sG7for low pressure PMOS pipe M ₇source electrode-grid voltage, V _sG8for high voltage PMOS pipe M ₈source electrode-grid voltage, V _sG9for high voltage PMOS pipe M ₉source electrode-grid voltage.

Described bias current source circuit, comprises current source I ₁, resistance R, three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂, two high voltage PMOS pipe M ₁₈, M ₁₉, three each utmost point withstand voltages are all less than the low pressure NMOS pipe M of 5V ₁₃, M ₁₄, M ₁₅with two low pressure PMOS pipe M ₁₆, M ₁₇;

High pressure NMOS pipe M ₁₀with low pressure NMOS pipe M ₁₃be connected in series high pressure NMOS pipe M ₁₁with low pressure NMOS pipe M ₁₄be connected in series; High pressure NMOS pipe M ₁₂with low pressure NMOS pipe M ₁₅be connected in series three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂grid be connected, the grid of three low pressure NMOS pipes is connected, source electrode connecting to neutral level forms common-source common-gate current mirror; Current source I ₁after series resistance R, be connected to high pressure NMOS pipe M ₁₀drain electrode, high pressure NMOS pipe M ₁₂drain electrode be connected to high voltage PMOS pipe M ₈drain electrode, be high voltage PMOS pipe M ₈constant current I is provided ₂:

$I_2\≈\frac{1}{2}{\mathrm{\μ}}_p{C}_{\mathrm{OX}}\frac{W_8}{L_8}{(V_{\mathrm{SG}8}-V_{\mathrm{TH}8})}^2---\left(2\right)$

Wherein, μ _pfor carrier mobility, C _oXfor the gate oxide electric capacity of unit are, V _tH8for high voltage PMOS pipe M ₈threshold voltage, L ₈and W ₈be respectively high voltage PMOS pipe M ₈channel length and width.

High voltage PMOS pipe M ₁₈with low pressure PMOS pipe M ₁₆be connected in series high voltage PMOS pipe M ₁₉with low pressure PMOS pipe M ₁₇be connected in series; High voltage PMOS pipe M ₁₈with M ₁₉grid be connected, low pressure PMOS manages M ₁₆and M ₁₇grid be connected, source electrode connects the output voltage V of DC-DC _oUT, form common-source common-gate current mirror; High voltage PMOS pipe M ₁₈drain electrode be connected to high pressure NMOS pipe M ₁₁drain electrode, high voltage PMOS pipe M ₁₉drain electrode be connected to high voltage PMOS pipe M ₉source electrode, be high voltage PMOS pipe M ₉constant current I is provided ₃:

$I_3\≈\frac{1}{2}{\mathrm{\μ}}_P{C}_{\mathrm{OX}}\frac{W_9}{L_9}{(V_{\mathrm{SG}9}-V_{\mathrm{TH}9})}^2---\left(3\right)$

Wherein, V _tH9for high voltage PMOS pipe M ₉threshold voltage, L ₉and W ₉be respectively high voltage PMOS pipe M ₉channel length and width.

Low pressure NMOS manages M ₁₄and M ₁₅breadth length ratio identical, low pressure PMOS manages M ₁₆and M ₁₇breadth length ratio identical, thereby make image current I ₂and I ₃be worth identical.Due to high voltage PMOS pipe M ₈and M ₉match, the length of raceway groove is identical with width, therefore their threshold voltage V _tH8and V _tH9also identical.Can obtain according to formula (2) and formula (3):

V _sG8=V _sG9(4) by formula (4) substitution formula (1), can obtain level shift circuit output voltage V _l:

V _L≈V _H-V _GS5-V _SG6-V _SG7 (5)

Electric current I is set ₂value, make V _gS5+ V _sG6+ V _sG7be less than 5V, i.e. level shift circuit output voltage V _lwith high voltage PMOS pipe M ₃, M ₄source voltage V _hpressure reduction be no more than 5V; Again because high pressure NMOS pipe M5 and low pressure PMOS pipe M ₆, M ₇all, in conducting state, therefore have

3V _tH< V _gS5+ V _sG6+ V _sG7wherein V of < 5 (6) _tHbe the threshold voltage of metal-oxide-semiconductor conducting.

With reference to figure 4, described control circuit, comprises inverter INV, comparator, clamp circuit and output circuit; The input of inverter INV is connected with the positive input of comparator, and meets control signal K, and the output signal XK of inverter INV is connected to the reverse input end of comparator; The output of comparator and high voltage PMOS pipe M ₃and M ₄source voltage V _hbetween be connected with clamp circuit; The input of output circuit is connected with the output of comparator, and output is connected to high voltage PMOS pipe M ₃and M ₄grid.

Described comparator, comprises two high pressure NMOS pipe M ₂₀, M ₂₁, two low pressure PMOS pipe M ₂₂, M ₂₃with current source I ₄; This high pressure NMOS pipe M ₂₀, M ₂₁as the input of this comparator to pipe, high pressure NMOS pipe M ₂₀grid meet input control signal K, high pressure NMOS pipe M ₂₁grid meet the output signal XK of inverter INV; Current source I ₄one end connecting to neutral level, the other end is connected to this high pressure NMOS pipe M ₂₀and M ₂₁source electrode, for comparator provides tail current; Low pressure PMOS manages M ₂₂and M ₂₃grid be connected, source electrode meets high voltage PMOS pipe M ₃and M ₄source voltage V _h, composition active electric current mirror, the load of device as a comparison; Low pressure PMOS manages M ₂₂drain electrode be connected to high pressure NMOS pipe M ₂₀drain electrode, low pressure PMOS manages M ₂₃drain electrode be connected to high pressure NMOS pipe M ₂₁drain electrode, the output of device as a comparison.

Described output circuit, comprises 2 low pressure PMOS pipe M ₂₇, M ₂₉with 2 low pressure NMOS pipe M ₂₈, M ₃₀; This low pressure PMOS manages M ₂₇with low pressure NMOS pipe M ₂₈grid be connected and be connected to the output of comparator, low pressure PMOS manages M ₂₇source electrode meet high voltage PMOS pipe M ₃and M ₄source voltage V _h, low pressure NMOS manages M ₂₈source electrode connect the output voltage V of level shift circuit _l, low pressure PMOS manages M ₂₇with low pressure NMOS pipe M ₂₈drain electrode be connected, and be connected to low pressure PMOS pipe M ₂₉with low pressure NMOS pipe M ₃₀grid; Low pressure PMOS manages M ₂₉source electrode meet high voltage PMOS pipe M ₃and M ₄source voltage V _h, low pressure NMOS manages M ₃₀source electrode connect the output voltage V of level shift circuit _l, low pressure PMOS manages M ₂₉with low pressure NMOS pipe M ₃₀drain electrode be connected, the voltage V of output _cbe connected to the grid of high voltage PMOS pipe M3 and high voltage PMOS pipe M4.

In the time that control signal K is zero level, the output signal XK of inverter INV is high level VDD, tail current I ₄high pressure NMOS pipe M all flows through ₂₁, comparator output voltage reduces, and makes low pressure PMOS pipe M ₂₇with low pressure NMOS pipe M ₃₀conducting, the output signal V of control circuit _cvoltage equal the output voltage V of level shift circuit _l; In the time that control signal K is high level VDD, the output signal XK of inverter INV is zero level, tail current I ₄high pressure NMOS pipe M all flows through ₂₀, comparator output voltage rises, and makes low pressure PMOS pipe M ₂₉with low pressure NMOS pipe M ₂₈conducting, the output signal V of control circuit _cvoltage equal high voltage PMOS pipe M ₃and M ₄source voltage V _h.

Because the output of comparator is directly connected to low pressure PMOS pipe M ₂₇grid, and low pressure PMOS pipe M ₂₇source electrode meet high voltage PMOS pipe M ₃, M ₄source voltage V _h, for preventing low pressure PMOS pipe M ₂₇source electrode-grid pressure reduction excessive, and introduced clamp circuit.Described clamp circuit, comprises three low pressure PMOS pipe M ₂₄, M ₂₅and M ₂₆, these three low pressure PMOS pipes are connected in series in high voltage PMOS pipe M ₃, M ₄source voltage V _hwith between the output of comparator, their grid is connected with drain electrode separately respectively, form diode connection, the output of comparator is carried out to clamp, prevent low pressure PMOS pipe M ₂₇grid voltage too low.

Operation principle of the present invention is as follows:

If step-up DC-DC transducer is operated in inductive current DCM, high pressure NMOS pipe M ₁with high voltage PMOS pipe M ₂switch alternate conduction, cut-off while needing only two pipe differences, ring can not occur, and the input signal K of anti-ringing circuit is high level, the output signal V of control circuit _cvoltage equal high voltage PMOS pipe M ₃, M ₄source voltage V _h, control signal V _cbe connected to high voltage PMOS pipe M ₃, M ₄grid, therefore high voltage PMOS pipe M ₃, M ₄source electrode-grid voltage equate, pressure reduction is 0, high voltage PMOS pipe M ₃, M ₄cut-off, two pipe source voltage terminal V _hthe voltage higher value that equals inductance L two ends deducts the pressure drop on diode, and due to the reverse-biased connection of diode, path thoroughly turn-offs, and does not affect the normal work of DC-DC.

If high pressure NMOS pipe M ₁with high voltage PMOS pipe M ₂while cut-off, the input signal K of anti-ringing circuit is zero level, the output signal V of control circuit simultaneously _cvoltage equal the output voltage V of level shift circuit _l, known according to the analysis in level shift circuit, voltage V _lwith high voltage PMOS pipe M ₃, M ₄source voltage V _hdifference V _gS5+ V _sG6+ V _sG7be greater than 3V _tH, exceeded high voltage PMOS pipe M ₃and M ₄on state threshold voltage, make high voltage PMOS pipe M ₃and M ₄conducting, makes inductance L two terminal shortcircuits, has destroyed the LC loop that ring forms, and has eliminated ringing.

High voltage PMOS pipe M ₃and M ₄when conducting, known according to the operation principle of above-mentioned level shift circuit, the output voltage V of level shift circuit _lfollow high voltage PMOS pipe M ₃, M ₄source voltage change, make high voltage PMOS pipe M ₃, M ₄source electrode-grid pressure reduction V _gS5+ V _sG6+ V _sG7keep being less than 5V, in high-voltage tube source electrode-gate withstand voltage value scope, thereby can prevent high voltage PMOS pipe M ₃and M ₄because of overvoltage punch through damage.

Below be only a preferred example of the present invention, do not form any limitation of the invention, obviously, under design of the present invention, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.

Claims (5)

1. be applied to the anti-ringing circuit in high voltage step-up type DC-DC transducer, comprise that control circuit, PMOS manage M ₃with PMOS pipe M ₄, this PMOS pipe M ₃and M ₄source electrode be connected, output voltage V _hbe connected to the input of level shift circuit, drain electrode connects respectively the two ends of inductance; The output signal V of control circuit _cbe connected to high voltage PMOS pipe M ₃and M ₄grid, for controlling M ₃and M ₄conducting and cut-off, eliminate ring; It is characterized in that: PMOS manages M ₃with PMOS pipe M ₄all adopt withstand voltage between source electrode and drain electrode to be greater than the high voltage PMOS pipe of 12V; The input of control circuit is connected with level shift circuit, for guaranteeing the output signal V of control circuit _cthe pressure reduction that logic height changes is no more than 5V, prevents high voltage PMOS pipe M ₃and M ₄because of excessive the puncturing of pressure reduction of source electrode and grid;

Described level shift circuit, comprises that withstand voltage between bias current source circuit, drain electrode and source electrode is greater than the high pressure NMOS pipe M of 12V ₅, two high voltage PMOS pipe M ₈, M ₉the low pressure PMOS that is all less than 5V with two each utmost point withstand voltages manages M ₆, M ₇; This high pressure NMOS pipe M ₅drain electrode connect the output voltage V of DC-DC _oUT, grid meets high voltage PMOS pipe M ₃and M ₄the output voltage V of source electrode _h, source electrode and low pressure PMOS pipe M ₆, M ₇after series connection, be connected to high voltage PMOS pipe M ₈source electrode; High voltage PMOS pipe M ₈grid and high voltage PMOS pipe M ₉grid connect, high voltage PMOS pipe M ₉drain electrode connecting to neutral level, source electrode output voltage V _l, be connected to control circuit; This bias current source circuit has two outputs, respectively with high voltage PMOS pipe M ₈drain electrode and high voltage PMOS pipe M ₉source electrode be connected, for these two high voltage PMOS pipes provide constant current;

Described bias current source circuit, comprises current source I ₁, resistance R, three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂, two high voltage PMOS pipe M ₁₈, M ₁₉, three each utmost point withstand voltages are all less than the low pressure NMOS pipe M of 5V ₁₃, M ₁₄, M ₁₅with two low pressure PMOS pipe M ₁₆, M ₁₇;

Described high pressure NMOS pipe M ₁₀with low pressure NMOS pipe M ₁₃be connected in series high pressure NMOS pipe M ₁₁with low pressure NMOS pipe M ₁₄be connected in series; High pressure NMOS pipe M ₁₂with low pressure NMOS pipe M ₁₅be connected in series; Three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂grid be connected, three low pressure NMOS pipe M ₁₃, M ₁₄, M ₁₅grid be connected, source electrode connecting to neutral level, form common-source common-gate current mirror; High pressure NMOS pipe M ₁₂drain electrode be connected to high voltage PMOS pipe M ₈drain electrode, be high voltage PMOS pipe M ₈constant current I is provided ₂;

Described high voltage PMOS pipe M ₁₈with low pressure PMOS pipe M ₁₆be connected in series high voltage PMOS pipe M ₁₉with low pressure PMOS pipe M ₁₇be connected in series; High voltage PMOS pipe M ₁₈with M ₁₉grid be connected, low pressure PMOS manages M ₁₆and M ₁₇grid be connected, source electrode connects the output voltage V of DC-DC _oUT, form common-source common-gate current mirror; High voltage PMOS pipe M ₁₈drain electrode be connected to high pressure NMOS pipe M ₁₁drain electrode, high voltage PMOS pipe M ₁₉drain electrode be connected to high voltage PMOS pipe M ₉source electrode, be high voltage PMOS pipe M ₉constant current I is provided ₃.

2. anti-ringing circuit according to claim 1, is characterized in that described control circuit, comprises inverter INV, comparator, clamp circuit and output circuit; The input of inverter INV is connected with the positive input of comparator, and meets control signal K, and the output signal XK of inverter INV is connected to the reverse input end of comparator; The output of comparator and high voltage PMOS pipe M ₃and M ₄source voltage V _hbetween be connected with clamp circuit; The input of output circuit is connected with the output of comparator, and output is connected to high voltage PMOS pipe M ₃and M ₄grid.

3. anti-ringing circuit according to claim 2, is characterized in that described comparator, comprises two high pressure NMOS pipe M ₂₀, M ₂₁, two low pressure PMOS pipe M ₂₂, M ₂₃with current source I ₄; This high pressure NMOS pipe M ₂₀, M ₂₁as the input of this comparator to pipe, high pressure NMOS pipe M ₂₀grid meet input control signal K, high pressure NMOS pipe M ₂₁grid meet the output signal XK of inverter INV; Current source I ₄one end connecting to neutral level, the other end is connected to this high pressure NMOS pipe M ₂₀and M ₂₁source electrode, for comparator provides tail current; Low pressure PMOS manages M ₂₂and M ₂₃grid be connected, source electrode meets high voltage PMOS pipe M ₃and M ₄source voltage V _h, composition active electric current mirror, the load of device as a comparison; Low pressure PMOS manages M ₂₂drain electrode be connected to high pressure NMOS pipe M ₂₀drain electrode, low pressure PMOS manages M ₂₃drain electrode be connected to high pressure NMOS pipe M ₂₁drain electrode, the output of device as a comparison.

4. anti-ringing circuit according to claim 3, is characterized in that described clamp circuit, comprises three low pressure PMOS pipe M ₂₄, M ₂₅and M ₂₆, these three low pressure PMOS pipes are connected in series in high voltage PMOS pipe M ₃, M ₄source voltage V _hwith between the output of comparator, their grid is connected with drain electrode separately respectively, form diode connection, comparator output voltage is carried out to clamp.

5. anti-ringing circuit according to claim 3, is characterized in that described output circuit, comprises 2 low pressure PMOS pipe M ₂₇, M ₂₉with 2 low pressure NMOS pipe M ₂₈, M ₃₀; This low pressure PMOS manages M ₂₇with low pressure NMOS pipe M ₂₈grid be connected and be connected to the output of comparator, low pressure PMOS manages M ₂₇source electrode meet high voltage PMOS pipe M ₃and M ₄source voltage V _h, low pressure NMOS manages M ₂₈source electrode connect the output voltage V of level shift circuit _l, low pressure PMOS manages M ₂₇with low pressure NMOS pipe M ₂₈drain electrode be connected, and be connected to low pressure PMOS pipe M ₂₉with low pressure NMOS pipe M ₃₀grid; Low pressure PMOS manages M ₂₉source electrode meet high voltage PMOS pipe M ₃and M ₄source voltage V _h, low pressure NMOS manages M ₃₀source electrode connect the output voltage V of level shift circuit _l, low pressure PMOS manages M ₂₉with low pressure NMOS pipe M ₃₀drain electrode be connected, the voltage V of output _cbe connected to high voltage PMOS pipe M ₃with high voltage PMOS pipe M ₄grid.

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