CN102411644B - Circuit layout regulation method - Google Patents
Circuit layout regulation method Download PDFInfo
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- CN102411644B CN102411644B CN 201010292482 CN201010292482A CN102411644B CN 102411644 B CN102411644 B CN 102411644B CN 201010292482 CN201010292482 CN 201010292482 CN 201010292482 A CN201010292482 A CN 201010292482A CN 102411644 B CN102411644 B CN 102411644B
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Abstract
The invention provides a circuit layout regulation method, which comprises the step of providing layout patterns, wherein the layout patterns comprise pressure stress film patterns and pull stress film patterns with overlapped regions and contact hole patterns at the overlapped regions, and the boundaries of the overlapped regions comprise relative pressure stress film pattern boundaries and pull stress film pattern boundaries. The circuit layout regulation method also comprises the following step of regulating the pressure stress pattern boundaries or the pull stress film pattern boundaries of the overlapped regions so that the contact hole patterns are only positioned in the regulated pressure stress film pattern regions or are only positioned in the regulated pull stress film pattern regions, so the interconnection plug performance is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method of adjustment of circuit layout.
Background technology
The Design and manufacture process of SIC (semiconductor integrated circuit) mainly comprises: the function according to required realization is carried out integrated circuit (IC) design; Carry out integrated circuit layout according to integrated circuit (IC) design; Integrated circuit layout is carried out DRC and logical operation; Optical proximity effect (OPE, Optical Proximity Effect) when considering exposure carries out optical proximity correction (OPC, Optical Proximity Correction) to integrated circuit layout; Then, make light shield with above-mentioned through the integrated circuit layout that checks and revise; At last, use photoetching process that the integrated circuit layout on the light shield is exposed on semi-conductor chip.
Past, Design and manufacture technique often independently, that is to say, the emphasis that the design engineer of integrated circuit (IC) design considers is to be the circuit function that will realize, rather than the manufacturability of designed circuit in the subsequent technique processing procedure, tend to like this to make semiconductor devices on the chip of formation to be difficult to reach requirement for performance.
For example at present for CMOS (Complementary Metal Oxide Semiconductor) (CMOS) semiconductor field effect transistor, normal strained channel zone of using the tension film to form nmos pass transistor, use compressive stress film to form the transistorized strained channel of PMOS zone, thereby can improve the mobility of nmos pass transistor and the transistorized charge carrier of PMOS, to increase the usefulness of element.Disclose a kind of semiconductor devices in application number is 200710101226.0 Chinese patent literature, it includes cmos device.
Describe below in conjunction with existing cmos device with stress film, as shown in Figure 1, cmos device comprises: active area 10, and it is made of the zone beyond the isolated area in the Semiconductor substrate 20; Gate insulating film 30, it is formed on the described active area 10; Gate electrode 40, it is formed on the described gate insulating film 30; Source/drain region 50, it is formed on the active area 10 that is arranged in described Semiconductor substrate gate electrode 40 both sides; And be formed on tension film 60 on the nmos pass transistor, it can produce tension on the grid length direction for the nmos pass transistor channel region, be formed on the compressive stress film 70 on the PMOS transistor, it can produce compressive stress on the grid length direction for the PMOS transistor channel region.
In the prior art, when forming stress film, in order to guarantee the space not occur between compressive stress film 70 and the tension film 60, usually tension film 60 and compressive stress film 70 can occur overlapping, if when design circuit, designed contact hole 80 in crossover position like this, have two-layer stress film owing to this position so, therefore very difficult fully etched open when etching forms contact hole 80, thus may be so that utilize the interconnection connector of described contact hole 80 formation to open circuit.
Summary of the invention
The problem that the present invention solves provides a kind of method of adjustment of circuit layout, thereby improves the performance of interconnection connector.
In order to address the above problem, the invention provides a kind of method of adjustment of circuit layout, comprise the step that the layout figure is provided, described layout figure comprises compressive stress film figure and the tension film pattern with overlapping region, and in the contact hole graph of described overlapping region, the border of described overlapping region comprises relative compressive stress film graphic limit and tension film pattern border, also comprises the steps:
Adjust compressive stress film graphic limit or the tension film pattern border of described overlapping region, the tension film pattern after adjustment is regional so that contact hole graph is only in the compressive stress film graphics field after the adjustment or only.
Optionally, described contact hole graph has the retive boundary right with the borderline phase of overlapping region.
Optionally, the described compressive stress film graphic limit of described adjustment is: described compressive stress film graphic limit is extremely overlapping with the retive boundary of described contact hole graph towards described tensile stress graphics boundary adjustment, perhaps be adjusted to described tension film pattern border overlappingly, perhaps be adjusted between the retive boundary and tension film pattern border of described contact hole graph.
Optionally, the described tension film pattern of described adjustment border is: be adjusted to the retive boundary of described contact hole graph overlapping towards described compressive stress graphic limit described tension film pattern border, perhaps be adjusted to described compressive stress film graphic limit overlappingly, perhaps be adjusted between the retive boundary and compressive stress film graphic limit of described contact hole graph.
Optionally, the described tension film pattern of described adjustment border is: be adjusted to the retive boundary of described contact hole graph overlapping towards described compressive stress film graphic limit part tension film pattern border, perhaps be adjusted to described compressive stress film graphic limit overlapping, perhaps be adjusted between the retive boundary and compressive stress film graphic limit of described contact hole graph, described part tension film pattern border refers to the described tension film pattern part relative with retive boundary described contact hole graph the border and the part of extending length-specific to both sides along described relative part.
Optionally, the described compressive stress film graphic limit of described adjustment is: part compressive stress film graphic limit is extremely overlapping with the retive boundary of described contact hole graph towards described tension film pattern boundary adjustment, perhaps be adjusted to described tension film pattern border overlapping, perhaps be adjusted between the retive boundary and tension film pattern border of described contact hole graph, described part compressive stress film graphic limit refers to the part relative with retive boundary described contact hole graph described compressive stress film graphic limit and the part of extending length-specific to both sides along described relative part.
Optionally, the described compressive stress film graphic limit of described adjustment refers to: if the compressive stress film graphic limit of described overlapping region is passed described contact hole graph, then adjust described compressive stress film graphic limit.
Optionally, the described tension film pattern of described adjustment border refers to: if described contact hole graph is passed on the tension film pattern border of described overlapping region, then adjust described tension film pattern border.
Optionally, described length-specific is 0.08 μ m.
Optionally, described contact hole is square, and the length of described contact hole * wide is: 0.06 μ m * 0.06 μ m, the width of overlapping region are 0.06 μ m.
Compared with prior art, the present invention mainly has the following advantages:
The present invention is by adjusting compressive stress film graphic limit or the tension film pattern border of described overlapping region, tension film pattern after adjustment is regional so that contact hole graph is only in the compressive stress film graphics field after the adjustment or only, like this so that the contact hole graph that obtains according to this layout owing to only be coated with compressive stress film figure or tension film pattern, rather than by tension film and the overlapping covering of compressive stress film, so open fully easily during etching.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Deliberately do not draw accompanying drawing by physical size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the existing synoptic diagram that forms contact hole in the semiconductor devices that is covered by stress film;
Fig. 2 is the method for adjustment process flow diagram of circuit layout of the present invention;
Fig. 3 to Fig. 5 is the method for adjustment synoptic diagram of one embodiment of the invention circuit layout;
Fig. 6 to Fig. 8 is the method for adjustment synoptic diagram of another embodiment of the present invention circuit layout.
Embodiment
By background technology as can be known, in the prior art, when forming stress film, in order the space not occur between proof stress mould stress film and the tension film, common tension film pattern and compressive stress film figure can occur overlapping, if designed contact hole in crossover position like this when design circuit, so because this position has two membranes, therefore very difficult fully etched open when etching forms contact hole, thus may be so that utilize the interconnection connector of described contact hole formation to open circuit.
The present inventor has obtained a kind of method of adjustment of circuit layout through a large amount of experimental studies, the present invention adjusts compressive stress film graphic limit or the tension film pattern border of described overlapping region, tension film pattern after adjustment is regional so that contact hole graph is only in the compressive stress film graphics field after the adjustment or only, so that the compressive stress film of contact hole position and tension film are not overlapping, like this so that the contact hole that obtains according to this layout owing to be coated with compressive stress film or tension film, rather than by tension film and the overlapping covering of compressive stress film, so open fully easily during etching.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing specific implementation of the present invention is described in detail.The present invention utilizes synoptic diagram to be described in detail; when the embodiment of the invention was described in detail in detail, for ease of explanation, the sectional view of expression device architecture can be disobeyed general ratio and be done local the amplification; and described synoptic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 is the method for adjustment process flow diagram of circuit layout of the present invention, and as shown in Figure 2, the method for adjustment of circuit layout of the present invention comprises step:
S10: the layout figure is provided, and described layout figure comprises compressive stress film figure and the tension film pattern with overlapping region at least, has contact hole graph at described overlapping region;
S20: adjust compressive stress film graphic limit or the tension film pattern border of described overlapping region, the tension film pattern after adjustment is regional so that contact hole graph is only in the compressive stress film graphics field after the adjustment or only.
Fig. 3 is the method for adjustment synoptic diagram of circuit layout of the present invention.Below in conjunction with Fig. 2 and Fig. 3 the method for adjustment of circuit layout of the present invention is elaborated.
At first, execution in step S10 with reference to figure 3, provides the layout figure, and described layout figure comprises compressive stress film figure 101 and the tension film pattern 103 with overlapping region 100 at least, has contact hole graph 105 at described overlapping region 100.In the present embodiment, described compressive stress film figure 101 can be for covering the stress film of PMOS device top, tension film pattern 103 can be for covering the stress film of nmos device top, therefore between compressive stress film figure 101 and the tension film pattern 103 space does not appear in order to guarantee, usually tension film pattern 103 can extend to PMOS device one side, same tension film pattern 101 can extend to nmos device one side, like this so that compressive stress film figure and tension film pattern will occur overlapping, be that (width from NMOS to PMOS direction of overlapping region 100 is 0.06 μ m to overlapping region 100 usually, namely the characteristic dimension with contact hole graph is identical), overlapping region 100 has two borders perpendicular to nmos device to PMOS device direction, for example the left side is compressive stress film figure 101 among Fig. 3, the right side is tension film pattern 103, therefore the border in overlapping region 100 left sides is tension film pattern border 103a, right side boundary is compressive stress film graphic limit 101a, hereinafter in order to describe easy border 101a and the 103a that above-mentioned two borders is called overlapping region 100.Needing to form contact hole graph 105 at nmos device and PMOS device links to each other with other circuit, for example contact hole graph 105 need to connect from the device of overlapping region 100 belows of compressive stress film figure 101 and tension film pattern 103 just, like this in the process of etching, because overlapping region 100 has the two-layer stress film of compressive stress film figure 101 and tension film pattern 103, so etching is not easy fully etched open.Described contact hole graph 105 have the retive boundary relative with the border (being 101a and 103a) of overlapping region 100 (for example retive boundary shown in Figure 3 be contact hole graph 105 with overlapping region 100 border 101a or the parallel border of 103a).
Adopt in the present invention the following step layout regulation figure, so that the contact hole graph position only has one deck stress film figure, only had one deck stress film under the contact hole of follow-up like this formation.
Then, carry out step S20, continuation is adjusted compressive stress film graphic limit 101a or the tension film pattern border 103a of described overlapping region with reference to figure 3, so that contact hole graph figure 105 tension film pattern 103 zones after adjustment in the zone of the compressive stress film figure 101 after the adjustment or only only.
In the present embodiment, the following method of concrete employing:
Calculate the coordinate of retive boundary of described contact hole graph 105 and the boundary coordinate of described overlapping region 100.Example as shown in FIG. 3, can set up coordinate system with the border of overlapping region 100 first, thereby can obtain the retive boundary coordinate of contact hole graph 105, in the present embodiment, take tension film 103 and borders compressive stress film 101 overlapping 103a as Y-axis, compressive stress film 101 to tension film 103 directions are X-axis, obtain the coordinate of retive boundary of contact hole graph 105 and the boundary coordinate of overlapping region 100.In the present embodiment, described contact hole graph 105 is square, the length of described contact hole graph 105 * wide is: 0.06 μ m * 0.06 μ m, and the width of overlapping region 100 is 0.06 μ m, the coordinate of the retive boundary of contact hole graph 105 is: X=-0.02 μ m and X=0.04 μ m.The boundary coordinate of overlapping region 100 is X=0 (be tension film 103 with the overlapping border 103a of compressive stress film 101) and X=0.06 μ m (be compressive stress film 101 with the overlapping border 101a of tension film 103), and contact hole graph 105 is passed on the border of visible described tension film 103.
In a preferred version, if the compressive stress film graphic limit 101a of described overlapping region 100 passes described contact hole graph 105, then adjust described compressive stress film graphic limit 101a; If the tension film pattern border 103a of described overlapping region 100 passes described contact hole graph 105, then adjust described tension film pattern border 103a.If described tension membrane boundary 103a passes contact hole graph 105, then be adjusted to the retive boundary of described contact hole graph 105 overlapping towards described compressive stress graphic limit 101a described tension film pattern border 103a, perhaps described tension film pattern border 103a is adjusted to described compressive stress film graphic limit 101a overlappingly towards described compressive stress graphic limit 101a, perhaps described tension film pattern border 103a is adjusted between the retive boundary and compressive stress film graphic limit 101a of described contact hole graph 105 towards described compressive stress graphic limit 101a.If described compressive stress film border 101a passes contact hole graph 105, then be adjusted to the retive boundary of described contact hole graph 105 overlapping towards described tension film pattern border 103a described compressive stress film graphic limit 101a, perhaps described compressive stress film graphic limit 101a is adjusted to described tension film pattern border 103a overlappingly towards described tension film pattern border 103a, perhaps described compressive stress film graphic limit 101a is adjusted between the retive boundary and tension film pattern border 103a of described contact hole graph 105 towards described tension film pattern border 103a.
In the present embodiment, described tension film pattern border 103a passes contact hole graph 105, therefore is adjusted to the described compressive stress film graphic limit 101a of overlapping region 100 overlapping towards described compressive stress film graphic limit 101a described tension film pattern border 103a with reference to figure 4.Can certainly adjust to overlap with the retive boundary (X=0.04) of contact hole graph 105 and get final product, also can adjust between the border 101a of the retive boundary of contact hole graph 105 and described compressive stress film 101, can also keep like this overlapping region of a part of compressive stress film 101 and tension film 103, prevent the space.
In a preferred implementation, tension film pattern border or compressive stress film graphic limit that can adjustment member, particularly, be adjusted to the retive boundary of described contact hole graph overlapping towards described compressive stress film graphic limit described tension film pattern border, perhaps described tension film pattern border is adjusted to described compressive stress film graphic limit overlappingly towards described compressive stress film graphic limit, perhaps is adjusted to described tension film pattern border between the retive boundary and compressive stress film graphic limit of described contact hole graph towards described compressive stress film graphic limit; Perhaps, described compressive stress film graphic limit is extremely overlapping with the retive boundary of described contact hole graph towards described tension film pattern boundary adjustment, perhaps with described compressive stress film graphic limit towards described tension film pattern boundary adjustment to overlapping with described tension film pattern border, perhaps with described compressive stress film graphic limit towards described tension film pattern boundary adjustment between the retive boundary and tension film pattern border of described contact hole graph.Described part tension film pattern border refers to the described tension film pattern part relative with retive boundary described contact hole graph the border and the part of extending length-specific to both sides along described relative part, and described part compressive stress film graphic limit refers to the part relative with retive boundary described contact hole graph described compressive stress film graphic limit and the part of extending length-specific to both sides along described relative part.
In the present embodiment, can be with reference to figure 3, two end points coordinates along the border of PMOS to NMOS direction that at first calculate contact hole graph 105 are X=-0.02 μ m, Y=2 μ m and X=-0.02 μ m, Y=2.06 μ m, another two end points coordinates along the border of PMOS to NMOS direction are X=0.04 μ m, Y=2 and X=0.04 μ m, Y=2.06 μ m.Then with reference to figure 5, a segment boundary that tension film pattern border 103a is passed contact hole graph 105 (is X=0, and between Y=2 and Y=2.06 μ m one section, the part relative with the retive boundary of described contact hole graph namely), and along passing the segment boundary of contact hole graph 105, extend to contact hole graph 105 both sides length-specific tension film pattern border 103a segment boundary (namely, extend the part of length-specific to both sides along described relative part), extend in the present embodiment 0.08 μ m, (be X=0, and one section and X=0 between Y=2.06 μ m and Y=2.06 μ m+0.08 μ m, and between Y=2 μ m and Y=2 μ m-0.08 μ m one section) adjusts to compressive stress film graphic limit 101a and overlap.
Like this because the characteristic dimension of contact hole graph and the width of overlapping region all are 0.06 μ m just, if therefore contact hole graph 105 is just through described tension film pattern border 103a, preferably adjust the border of tension film pattern 103 to compressive stress film graphic limit 101a one side, adjusting＜0.06 μ m (for example can adjust in the present embodiment 0.04 μ m) just can be so that the contact hole graph position have overlapping stress film, and that compressive stress film figure 101 and tension film pattern 103 zone beyond contact hole graph 105 can also have is overlapping on a small quantity, and same like this can the assurance space do not occur between compressive stress film 101 and the tension film 103.And if adjust conversely the border of compressive stress film figure 101 to tension film pattern border 103a one side, then need to adjust equal 0.06 μ m just can be so that contact hole graph 105 positions have overlapping stress film, so just make between compressive stress film 101 and the tension film 103 easily and the space occurs, so technical scheme of above-described embodiment, so that realization is simpler, better effects if.
Export at last current layout figure, utilize this layout figure just can carry out the follow-up manufacturing steps such as photoetching, form semiconductor devices.
In another embodiment, when carrying out step S20, with reference to figure 6, calculate the boundary coordinate of described contact hole graph 105 and the boundary coordinate of described overlapping region 100.Example as shown in FIG. 6, can set up coordinate system with the border of overlapping region 100 first, thereby can obtain the coordinate of the retive boundary of contact hole graph 105, in the present embodiment, take tension film pattern border 103a as Y-axis, compressive stress film 101 to tension film 103 directions are X-axis, obtain the boundary coordinate of contact hole graph 105 and the boundary coordinate of overlapping region 100.In the present embodiment, described contact hole graph 105 is square, the length of described contact hole graph 105 * wide is: 0.06 μ m * 0.06 μ m, and the width of overlapping region 100 is 0.06 μ m, the coordinate of the retive boundary of contact hole graph 105 is: X=0.02 μ m and X=0.08 μ m.The boundary coordinate of overlapping region 100 is X=0 (be tension film pattern 103 with the overlapping border 103a of compressive stress film figure 101) and X=0.06 μ m (be compressive stress film figure 101 with the overlapping border 101a of tension film pattern 103), as seen described compressive stress film graphic limit 101a passes contact hole graph 105, therefore with reference to figure 7, described compressive stress film figure 101 transferred to border 103a overlapping (namely overlapping) with the described tension film 103 of overlapping region 100 with the overlapping border 101a of described tension film 103 towards the border of described tension film pattern 103 103a, can certainly adjust to overlap with the retive boundary (X=0.02) of contact hole graph 105 and get final product, also can adjust between the border 103a of the retive boundary of contact hole graph 105 and described tension film 103, can also keep like this overlapping region of a part of compressive stress film 101 and tension film 103, prevent the space.。
In another embodiment, with reference to figure 6, two end points coordinates along the border of PMOS to NMOS direction that at first calculate contact hole graph 105 are X=0.02 μ m, Y=2 and X=0.02 μ m, Y=2.06 μ m, another two end points coordinates along the border of PMOS to NMOS direction are X=0.08 μ m, Y=2 and X=0.08 μ m, Y=2.06 μ m.Then with reference to figure 8, a segment boundary that compressive stress film graphic limit 101a is passed contact hole graph 105 (is X=0.06 μ m, and between Y=2 and Y=2.06 μ m one section), and the segment boundary that passes contact hole graph 105 extends 0.08 μ m, be X=0.06 μ m, and one section and X=0.06 μ m between Y=2.06 μ m and Y=2.06 μ m+0.08 μ m, and between Y=2 μ m and Y=2 μ m-0.08 μ m one section is adjusted to the retive boundary (X=0.02) of contact hole graph and is overlapped, can also keep like this overlapping region of a part of compressive stress film and tension film, prevent the space.Can certainly adjust to the border 103a of tension film 103 and overlap.
In the present embodiment, like this because the characteristic dimension of contact hole graph 105 and the width of overlapping region 100 all are 0.06 μ m just, if so contact hole graph 105 lucky border 101a through described compressive stress film figure 101, preferably adjust the border 101a of compressive stress film figure 101 to tension film pattern border 103a one side, adjusting＜0.06 μ m just can be so that contact hole graph 105 positions have overlapping stress film, and that external beyond contact hole graph 105 of compressive stress film figure 101 and tension film pattern 103 can also have is overlapping on a small quantity, and same like this can the assurance space do not occur between compressive stress film figure 101 and the tension film pattern 103.And if adjust conversely the border of tension film pattern 103 to compressive stress film graphic limit 101a one side, then need to adjust=0.06 μ m just can be so that the contact hole graph position have overlapping stress film, between compressive stress film figure 101 and the tension film pattern 103 space appears so just easily, so technical scheme of above-described embodiment, so that realization is simpler, better effects if.
What deserves to be explained is in the above-described embodiments, only illustrated a contact hole graph, if the above-mentioned layout adjustment method of the same signal of a plurality of contact hole graph is arranged, can analogize from above-mentioned layout adjustment method and obtain.
The present invention is by the boundary coordinate of calculating contact hole graph and the boundary coordinate of described overlapping region; Boundary coordinate according to the overlapping region of the boundary coordinate of described contact hole graph and compressive stress film and tension film, that adjust described compressive stress film and the coordinate overlapping border of described tension film, or adjust the tension film with the exert oneself coordinate on the overlapping border of film of described pressure, so that the compressive stress film of contact hole graph position and tension film are not overlapping, like this so that the contact hole graph that obtains according to this layout owing to be coated with compressive stress film or tension film, rather than by tension film and the overlapping covering of compressive stress film, therefore open fully easily during etching, thereby so that the contact of the metal plug that this contact hole graph of later use forms is good, performance is more excellent.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (4)
1. the method for adjustment of a circuit layout, comprise the step that the layout figure is provided, described layout figure comprises compressive stress film figure and the tension film pattern with overlapping region, and in the contact hole graph of described overlapping region, the border of described overlapping region comprises relative compressive stress film graphic limit and tension film pattern border, described contact hole graph has the retive boundary right with the borderline phase of overlapping region, it is characterized in that, also comprises the steps:
Adjust compressive stress film graphic limit or the tension film pattern border of described overlapping region, the tension film pattern after adjustment is regional so that contact hole graph is only in the compressive stress film graphics field after the adjustment or only;
Wherein, pass described contact hole graph if only have the tension film pattern border of described overlapping region, then adjust described tension film pattern border, the described tension film pattern of described adjustment border is: be adjusted to the retive boundary of described contact hole graph overlapping towards described compressive stress film graphic limit part tension film pattern border, perhaps overlapping with described compressive stress film graphic limit, perhaps between the retive boundary and compressive stress film graphic limit of described contact hole graph, described part tension film pattern border refers to the described tension film pattern part relative with retive boundary described contact hole graph the border and the part of extending length-specific to both sides along described relative part;
Pass described contact hole graph if only have the compressive stress film graphic limit of described overlapping region, then adjust described compressive stress film graphic limit, the described compressive stress film graphic limit of described adjustment is: part compressive stress film graphic limit is extremely overlapping with the retive boundary of described contact hole graph towards described tension film pattern boundary adjustment, perhaps overlapping with described tension film pattern border, perhaps between the retive boundary and tension film pattern border of described contact hole graph, described part compressive stress film graphic limit refers to the part relative with retive boundary described contact hole graph described compressive stress film graphic limit and the part of extending length-specific to both sides along described relative part.
2. the method for adjustment of circuit layout according to claim 1 is characterized in that, the length-specific in the described part tension film pattern border is 0.08 μ m.
3. the method for adjustment of circuit layout according to claim 1 is characterized in that, the length-specific in the described part compressive stress film graphic limit is 0.08 μ m.
4. the method for adjustment of circuit layout according to claim 1 is characterized in that, described contact hole is square, and the length of described contact hole * wide is: 0.06 μ m * 0.06 μ m, the width of overlapping region are 0.06 μ m.
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| JP2008066484A (en) * | 2006-09-06 | 2008-03-21 | Fujitsu Ltd | Cmos semiconductor device and its manufacturing method |
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Effective date of registration: 20121101 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
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