CN102254945A - Metal oxide semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof - Google Patents

Metal oxide semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof Download PDF

Info

Publication number
CN102254945A
CN102254945A CN 201010181616 CN201010181616A CN102254945A CN 102254945 A CN102254945 A CN 102254945A CN 201010181616 CN201010181616 CN 201010181616 CN 201010181616 A CN201010181616 A CN 201010181616A CN 102254945 A CN102254945 A CN 102254945A
Authority
CN
Grant status
Application
Patent type
Prior art keywords
sidewall
layer
oxide
gate
spacer
Prior art date
Application number
CN 201010181616
Other languages
Chinese (zh)
Inventor
尹海洲
朱慧珑
骆志炯
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

The invention discloses a metal oxide semiconductor field effect transistor (MOSFET) structure and a manufacturing method thereof. The MOSFET structure comprises a semiconductor substrate, a gate stack and a side wall, wherein the gate stack is formed on the semiconductor substrate and comprises a high k gate medium layer and a gate main body layer; and the side wall comprises a first side wall and a second side wall which are formed outside the gate stack in turn, and the first side wall is made of a La-containing oxide. The MOSFET structure is applied to manufacturing an integrated circuit.

Description

MOSFET结构及其制作方法 MOSFET structure and manufacturing method thereof

技术领域 FIELD

[0001] 本申请一般地涉及半导体器件及其制作领域,更为具体地,涉及一种MOSFET (金属氧化物半导体场效应晶体管)结构及其制作方法。 [0001] The present application relates to semiconductor devices and fabrication generally to the field, more particularly, to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure and its manufacturing method.

背景技术 Background technique

[0002] 随着半导体技术的发展,晶体管尺寸不断缩小,器件和系统的速度随之提高。 [0002] With the development of semiconductor technology, shrinking transistor size, speed devices and systems increases. 在这种尺寸减小的晶体管中,栅介质层例如S^2的厚度也随之变薄。 In such a transistor is reduced in size, the gate dielectric layer thickness, for example, S ^ 2, also will be thinned. 然而,当S^2的厚度薄到一定程度时,其将不再能很好地起到绝缘的作用,容易产生从栅极到有源区的漏电流。 However, when the thickness of the thin S ^ 2 to a certain extent, it will no longer functions well as an insulating easily leak current from the gate to the active region. 这使得器件性能极大恶化。 This makes a great deterioration in device performance.

[0003] 为此,替代常规的SiO2/多晶硅的栅堆叠,提出了高k材料/金属的栅堆叠结构。 [0003] For this purpose, place of a conventional SiO2 / polysilicon gate stack, the gate stack structure proposed high-k / metal. 所谓高k材料是指介电常数k大于3. 9的材料。 The so-called high-k material refers to a dielectric constant k greater than 3.9 of the material. 例如,高k材料可以包括Hf02、HfSi0、HfSi0N、 HfTaO, HfTiO, HfZrOai2O3或La2O3等。 For example, high-k material may include Hf02, HfSi0, HfSi0N, HfTaO, HfTiO, HfZrOai2O3 or the like La2O3. 通过使用这种高k材料作为栅介质层,可以极大程度上克服上述漏电流问题。 By using such a high-k material as a gate dielectric layer, a leakage current problem may be overcome to a great extent.

[0004] 在现有技术中已经知道,在作为栅介质层的材料中加入La等材料,将能够有效地降低晶体管的阈值电压(Vt),这有助于改善器件性能。 [0004] It has been known in the prior art, the addition of La and other materials as the gate dielectric material layer, will be able to effectively reduce the threshold voltage of a transistor (Vt of), which helps to improve device performance. 然而,La等材料的这种降低阈值电压Vt的有效性受到多种因素的影响。 However, this reduction in the effectiveness of the threshold voltage Vt La like material is affected by many factors. 例如,在参考文献1(M. Inoue et al, "Impact of Area Scaling onThreshold Voltage Lowering in La-Containing High-k/Metal GateNMOSFETs Fabricated on (100) and(110)Si2009Symposium on VLSITechnology Digest of Technical Papers,pp. 40-41)中,对La的这种有效性进行了详细的研究,发现存在着较强的窄宽度效应(即,栅极宽度越窄,La的有效性越低)和角效应(即,沟道区的圆角影响La的有效性)。 For example, in Reference 1 (M. Inoue et al, "Impact of Area Scaling onThreshold Voltage Lowering in La-Containing High-k / Metal GateNMOSFETs Fabricated on (100) and (110) Si2009Symposium on VLSITechnology Digest of Technical Papers, pp. 40-41), the effectiveness of such La conducted detailed study, found that there is a strong effect of narrow width (i.e., the narrower the width of the gate, the lower the effectiveness of La) and angle effect (i.e., fillet channel region of La affect the validity).

[0005] 随着沟道不断变窄,栅介质层的有效性在沟道区的范围内受到影响。 [0005] As the channel narrows constantly, the effectiveness of the gate dielectric layer is influenced in a range of the channel region. 因此有必要进一步采取其他措施,以便有效应对阈值电压Vt的降低。 It is necessary to further take other measures to respond effectively to lower the threshold voltage Vt.

发明内容 SUMMARY

[0006] 鉴于上述问题,本发明的目的在于提供一种金属氧化物半导体场效应晶体管(MOSFET)结构及其制作方法,该MOSFET能够减小阈值电压(Vt)沿沟道长度和宽度方向的变化,从而改善器件性能。 [0006] In view of the above problems, an object of the present invention is to provide a metal oxide semiconductor field effect transistor (MOSFET) structure and its manufacturing method, capable of reducing the MOSFET threshold voltage (Vt) variations in the channel length and width directions , thereby improving the device performance.

[0007] 根据本发明的一个方面,提供了一种金属氧化物半导体场效应晶体管,包括:半导体衬底;在所述半导体衬底上形成的栅堆叠,所述栅堆叠包括高k栅介质层和栅极主体层; 侧墙,包括在所述栅堆叠外侧依次形成的第一侧墙和第二侧墙,所述第一侧墙由含La氧化物形成。 [0007] In accordance with one aspect of the present invention, there is provided a metal oxide semiconductor field effect transistor comprising: a semiconductor substrate; a gate formed on the semiconductor substrate of the stack, the gate stack comprises a high-k gate dielectric layer and a gate body layer; spacers, comprising a first sidewall and a second sidewall stacked sequentially formed outside the gate, the first sidewall is formed of a La-containing oxide.

[0008]优选地,所述高 k 栅介质层包括Hf02、HfSiO、HfSiON、HfTaO, HfTiO, HfZrO, A1203、 La2O3, ZrO2, LaAlO和中任一种或多种的组合。 [0008] Preferably, the high-k gate dielectric layer comprises Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1203, La2O3, ZrO2, LaAlO any one or combination of more.

[0009] 其中,所述含La氧化物包括La203、LaAlO, LaHfO, LaZrO中任一种或多种的组合。 [0009] wherein the La-containing oxide comprises La203, LaAlO, LaHfO, LaZrO any one or plural combination.

[0010] 优选地,所述第一侧墙的厚度小于等于5nm ;第二侧墙由氮化物形成。 [0010] Preferably, the thickness of the first spacer 5 nm or less; a second spacer is formed of nitride. [0011] 第二侧墙的外侧可以包括第三侧墙,即第二侧墙位于第一侧墙和第三侧墙之间。 [0011] outside of the second sidewall spacer may include a third, i.e., a second spacer positioned between the first sidewall and the third sidewall. 第三侧墙可以为氧化物、氮化物或低k材料形成。 The third spacer may be an oxide, a nitride or a low k material. 低k材料可以为Si02、Si0F、SiC0H、Si0、 SiCO, HSQ和MSQ中的任一种或多种的组合。 Low-k material can be Si02, Si0F, SiC0H, Si0, SiCO, HSQ and MSQ any one or more thereof.

[0012] 根据本发明的另一方面,提供了一种制作金属氧化物半导体场效应晶体管的方法,包括:提供半导体衬底;在所述半导体衬底上依次形成高k栅介质层、栅极主体层,并进行构图以形成栅堆叠;在所述栅堆叠的外侧依次形成第一侧墙和第二侧墙,所述第一侧墙由含La氧化物形成。 [0012] According to another aspect of the present invention, there is provided a method of making a metal oxide semiconductor field effect transistor, comprising: providing a semiconductor substrate; sequentially forming a high-k gate dielectric layer on the semiconductor substrate, a gate body layer, and patterned to form the gate stack; forming a first sidewall and a second sidewall of said gate stack on the outside of the first spacer is formed of a La-containing oxide.

[0013] 根据本发明的实施例,在侧墙中加入了一层由含La氧化物形成的第一侧墙,由于La元素向栅介质层中扩散,因此能够有效降低晶体管的阈值电压Vt0 [0013] According to an embodiment of the present invention, the addition of a first spacer formed of a La-containing oxide in the spacer layer, due to the diffusion of La element in the gate dielectric layer, it is possible to effectively reduce the threshold voltage of a transistor Vt0

附图说明 BRIEF DESCRIPTION

[0014] 通过以下参照附图对本发明实施例的描述,本发明的上述以及其他目的、特征和有点将更为清楚,在附图中: [0014] The following description of embodiments with reference to the accompanying drawings of embodiments of the present invention, the above and other objects, features, and little will be more apparent in the drawings:

[0015] 图1-5示出了根据本发明一个实施例的制作金属氧化物半导体场效应晶体管(MOSFET)的流程中部分阶段的示意截面图。 [0015] FIG. 1-5 shows a schematic sectional view showing the process of building MOSFET transistor (MOSFET) according to one embodiment of the present invention is based on the stage portion.

具体实施方式 detailed description

[0016] 以下,通过附图中示出的具体实施例来描述本发明。 [0016] Hereinafter, the present invention will be described by way of embodiments shown in the drawings. 但是应该理解,这些描述只是示例性的,而并非要限制本发明的范围。 It should be understood that these descriptions are exemplary only, and are not intended to limit the scope of the invention. 此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本发明的概念。 In the following description, description is omitted for well-known structures and techniques, in order to avoid unnecessarily obscuring the concepts of the present invention.

[0017] 在附图中示出了根据本发明实施例的半导体器件的截面图。 [0017] In the accompanying drawings shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention. 这些图并非是按比例绘制的,其中为了清楚的目的,放大了某些细节,并且可能省略了某些细节。 These figures are not drawn to scale, for clarity purposes, some details enlarged and some details may be omitted. 图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的,实际中可能由于制造公差或技术限制而有所偏差,并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。 The various regions shown in the drawings, the shape of the layer and the relative sizes therebetween, the positional relationship is exemplary only, and in practice may be due to manufacturing tolerances or deviations technical limits, and those skilled in the art based on the actual you can also devise have different shapes, sizes and relative locations of the regions / layers.

[0018] 图1-4示出了根据本发明一个实施例的制作金属氧化物半导体场效应晶体管(MOSFET)的流程中部分阶段的示意截面图。 [0018] Figures 1-4 show a schematic cross-sectional view the process of building MOSFET transistor (MOSFET) according to one embodiment of the present invention is based on the stage portion.

[0019] 优选地,首先如图1所示,在半导体衬底1001中形成浅沟槽隔离(STI) 1002,以隔离各单独的器件区域。 [0019] Preferably, first, as shown in FIG. 1, a shallow trench isolation (STI) 1002, to isolate each individual device regions in a semiconductor substrate 1001. STI 1002例如可以通过在半导体衬底1001中蚀刻出浅槽并淀积SiO2而形成。 STI 1002, for example, may be formed by etching the semiconductor substrate 1001 in the shallow trench and depositing SiO2.

[0020] 接着,在半导体衬底1001上形成晶体管结构的栅堆叠100A、100B。 A gate [0020] Next, the transistor structure formed on a semiconductor substrate 1001 are stacked 100A, 100B. 在此,示出了两个晶体管结构。 Here, the structure shows the two transistors. 但是,本领域普通技术人员应当理解,本发明不限于此,可以仅存在单个晶体管结构,或者存在三个乃至更多晶体管结构;而且所示两个晶体管结构的位置关系也不限于图中所示。 However, those of ordinary skill in the art will appreciate that the present invention is not limited thereto, there may be only a single transistor structure, there are three or more and the transistor structure; and the positional relationship shown is not limited to two transistor structures shown in FIG. .

[0021] 栅堆叠100AU00B例如分别包括高k材料层1003、栅极金属层1004 ;优选地,还可以包括多晶硅1005。 [0021] 100AU00B gate stack comprising high-k material layer, for example, 1003, 1004, respectively, the gate metal layer; preferably, may further include polysilicon 1005. 本发明实施例中所举的栅极主体包括栅极金属层1004和多晶硅1005。 Examples cited in the gate body of the embodiment of the present invention comprises a metal layer 1004 and the polysilicon gate 1005. 在其他的实施例中,栅极主体可以包括其他的结构,例如,多晶硅上可以形成NiSi等结构来减小栅电阻。 In other embodiments, the gate may include other body structures, e.g., NiSi can be formed on the polysilicon structures and the like to reduce the gate resistance. 这种栅堆叠100AU00B可以通过多种方式来形成。 100AU00B Such gate stack may be formed by a variety of ways. 具体地,例如在衬底上依次淀积高k材料的栅介质层、栅极金属层以及可选的多晶硅或非晶硅层。 Specifically, for example, sequentially depositing a gate dielectric layer of high k material, the gate metal layer and optional polycrystalline or amorphous silicon layer on a substrate. 例如,高k材料可以包括Hf02、HfSiO、HfSiON、HfTaO, HfTiO, HfZrO, A1203、La2O3, ZrO2, LaAlO 和11¾ 中的任一种或多种,厚度例如为l_5nm。 For example, high-k material may include Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1203, La2O3, ZrO2, LaAlO 11¾ and any one or more of, for example, a thickness l_5nm. 栅极金属层例如可以包括TaN、T£i2C、HfN、HfC、TiC、TiN、 MoN, MoC、TaTbN, TaErN, TaYbN, TaSiN, TaAlN, TiAIN、TaHfN, TiHfN, HfSiN, MoSiN, MoAIN、 Mo、Ru、RuO2, RuTax, NiTax等,厚度例如可以为10-20nm。 The gate metal layer may comprise TaN, T £ i2C, HfN, HfC, TiC, TiN, MoN, MoC, TaTbN, TaErN, TaYbN, TaSiN, TaAlN, TiAIN, TaHfN, TiHfN, HfSiN, MoSiN, MoAIN, Mo, Ru , RuO2, RuTax, NiTax the like, for example, a thickness of 10-20nm. 可选的多晶硅或非晶硅层厚度例如为50-100nm。 Alternatively, for example, polysilicon or amorphous silicon layer of thickness 50-100nm. 然后,对淀积的各层进行构图,以形成栅堆叠。 Then, the deposited layers is patterned to form a gate stack.

[0022] 然后,例如可以进行LDD (轻掺杂漏)掺杂,从而在栅堆叠的两侧形成轻掺杂区,也称为源/漏延伸区(SDE),SDE在沟道两端形成的浅结有利于抑制短沟道效应。 [0022] Then, for example, may be an LDD (lightly doped drain) doping, thereby forming lightly doped regions on both sides of the gate stack, also referred to as source / drain extension regions (SDE), SDE is formed at both ends of the channel shallow junction is advantageous in suppressing the short channel effect.

[0023] 接着,如图2所示,在半导体衬底1001包括栅堆叠100A、100B上淀积含La氧化物层1006,例如厚度约为3-5nm,材料例如为La203、LaAW、LaHf0、LaZrO中任一种或多种的组合。 [0023] Next, as shown in FIG semiconductor substrate comprising the gate stack 1001 100A 2, La-containing oxide layer 1006 is deposited on 100B, for example, a thickness of about 3-5nm, material such as La203, LaAW, LaHf0, LaZrO any one or more thereof. 在此所说的“淀积”可以包括各种淀积材料的方式,例如包括但不限于CVD(化学气相淀积)、分子束外延(MBE)、蒸镀等。 The term "deposition" may include depositing material in various ways, including but not limited to, for example, CVD (chemical vapor deposition), molecular beam epitaxy (MBE), vapor deposition.

[0024] 随后,如图3所示,对所淀积的含La氧化物层1006进行构图,例如通过RIE (反应离子刻蚀)等干法刻蚀,使得该含La氧化物层仅留在栅堆叠100AU00B的侧壁,如图3中1006'所示,从而构成第一侧墙1006'。 [0024] Subsequently, as shown in FIG La-containing oxide layer 1006 deposited 3 is patterned, e.g., by RIE (reactive ion etching) or the like dry etching, so that the La-containing oxide layer is left only in 100AU00B sidewalls of the gate stack, as shown in 1006 'shown, thereby forming the first spacer 1006'.

[0025] 与上述形成第一侧墙的方法类似,接着进一步形成侧墙的其他部分,如第二侧墙1007、第三侧墙1008。 [0025] The method of forming the first sidewall and similarly, followed by further formation of other portions of the spacers, such as spacers 1007 of the second, third spacer 1008. 可以在形成了第一侧墙的半导体衬底1001上淀积另一氧化物层,例如SiO2,并采用干法刻蚀该氧化物层,从而在第一侧墙1006'的外侧形成第二侧墙1007。 It may be further formed an oxide layer deposited on the semiconductor substrate a first spacer 1001, for example, of SiO2, and dry etching the oxide layer to form a second side of the outside of the first spacer 1006 apos wall 1007. 接着在形成了第二侧墙1007的外壁上淀积氮化物层,例如Si3N4,对该氮化物层进行刻蚀以在第二侧墙1007的外侧形成第三侧墙。 Followed by a second spacer formed on the outer wall 1007 of depositing a nitride layer, such as Si3N4, the nitride layer is etched to form outside the second sidewall 1007. The third sidewall spacer. 第三侧墙的材料还可以是氧化物或低k材料,包括: SiO2, SiOF, SiCOH, SiO, SiCO, HSQ和MSQ中的任一种或多种的组合。 The third spacer material may also be an oxide or a low-k material, comprising: SiO2, SiOF, SiCOH, SiO, SiCO, HSQ and MSQ any one or more combinations. 形成侧墙的方法在现有技术中是已知的,在此不再赘述。 The method of forming spacers are known in the prior art, which is not repeated herein.

[0026] 可以选择是否形成第三侧墙1008,该侧墙不是必须的。 [0026] 1008 can choose whether to form a third spacer, the spacer is not essential. 如果不形成第三侧墙,那么形成的结构如图5所示,包括第一侧墙和第二侧墙。 If the third spacer is not formed, the structure formed as shown in FIG 5, comprises a first sidewall and a second sidewall.

[0027] 一般地,第一侧墙的厚度可以为l-5nm,第二侧墙为氧化物,厚度为3-lOnm,第三侧墙可以为氧化物、氮化物或低k介质材料,例如Si02、SiOF, SiCOH、SiO、SiCO、HSQ和MSQ 中的任一种或多种的组合,厚度约为10-50nm。 [0027] Generally, the thickness of the first spacer may be a l-5nm, a second sidewall oxide thickness is 3-lOnm, a third spacer may be an oxide, a nitride or a low k dielectric material, e.g. si02, SiOF, SiCOH, SiO, SiCO, HSQ and MSQ any one or more of a combination of a thickness of about 10-50nm.

[0028] 形成侧墙之后,以栅堆叠100A、100B为掩模,进行源/漏区注入,之后,在形成侧墙(1006'、1007、1008)后,以栅堆叠和侧墙一起为掩模来进行源/漏区注入,以形成源/漏区,如图4中虚线所示。 After [0028] After forming the sidewall spacers, the gate stack 100A, 100B as a mask, the source / drain implantation, after forming the spacer (1006 ', 1007, 1008), and the gate stack as a mask with spacer die to the source / drain implantation, to form source / drain regions, as shown in Figure 4 in broken lines. 由于这种源/漏区的形成与本发明的主旨并无直接关联,在此省略了对其的详细描述。 Since the formation of this spirit of the source / drain regions of the present invention is not directly related in this detailed description thereof is omitted.

[0029] 最终,得到了图4所示的根据本发明一个实施例的MOSFET结构。 [0029] Finally, the resulting structure of the MOSFET according to the present embodiment of the invention, an embodiment shown in FIG. 具体地,如图4所示,该MOSFET包括:半导体衬底1001 ;在半导体衬底1001上形成的栅堆叠,栅堆叠包括栅介质层1003、栅极主体层(包括栅极金属层1004以及可选的多晶硅层1005);以及侧墙,从栅堆叠一侧开始依次包括第一侧墙1006'、第二侧墙1007、以及可选的第三侧墙1008。 Specifically, as shown in FIG. 4, the MOSFET comprising: a semiconductor substrate 1001; a gate formed on the semiconductor substrate 1001 are stacked, the gate stack comprising a gate dielectric layer 1003, the gate body layer (including the gate metal layer 1004 and a selected from the polysilicon layer 1005); and a side wall, from one side of the gate stack includes sequentially a first spacer 1006 ', a second sidewall 1007, a third sidewall 1008 and optionally. 其中,栅介质层1003 可以包括HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1203、La2O3> ZrO2, LaAW和TW2中的任一种或多种的组合,栅介质层1003厚度例如为l-5nm。 Wherein the gate dielectric layer 1003 may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1203, La2O3> ZrO2, and TW2 LaAW any one or a combination of more, a thickness of the gate dielectric layer 1003, for example, l-5nm . 第一侧墙1006 ' 厚度优选为小于等于5nm,可以由含La氧化物形成,例如La203、LaAlO, LaHfO, LaZrO中任一种或多种的组合。 The first spacer 1006 'is preferably of a thickness of 5 nm or less, it may be formed of an oxide containing La, e.g. La203, LaAlO, LaHfO, LaZrO any one or more thereof. 第二侧墙的厚度约为3-lOnm,由氧化物形成,例如Si02、SiOF, SiCOH、 SiO、SiCO等。 Thickness of the second spacer is about 3-lOnm, formed of an oxide such as Si02, SiOF, SiCOH, SiO, SiCO like. 第三侧墙的厚度约为10-50nm,可以是氮化物、氧化物或低k介质材料,例如Si3N4, SiO2, SiOF、SiCOH, SiO, SiCO, HSQ 和MSQ 等或它们的组合。 About 10 to 50 nm thickness of the third side wall, may be a nitride, oxide or low-k dielectric material such as Si3N4, SiO2, SiOF, SiCOH, SiO, SiCO, HSQ and MSQ like, or combinations thereof.

[0030] 根据本发明另一实施例的MOSFET如图5所示,与图4的结构不同的是,栅堆叠的两侧只包括第一侧墙1006'和第二侧墙1007。 [0030] According to another embodiment shown in FIG MOSFET embodiment 5 of the present invention, the structure of Figure 4 except that the sides of the gate stack includes only a first spacer 1006 'and a second sidewall 1007.

[0031] 对于采用高k栅介质层的MOSFET来说,沟道越窄,栅介质层的有效性很容易受到影响,尤其是在沟道的边缘。 [0031] For the high-k gate dielectric layer is a MOSFET, the channel is narrower, the effectiveness of the gate dielectric layer is vulnerable, especially at the edges of the channel. 本发明的实施例在栅堆叠的外侧形成了含La氧化物形成的第一侧墙1006',部分La元素扩散到栅介质层中,能够有效降低晶体管的阈值电压Vt,改善器件的性能。 Embodiments of the present invention is formed outside the gate stack comprising a first spacer 1006 formed in the oxide La ', part of La element is diffused into the gate dielectric layer, can effectively reduce the threshold voltage Vt of the transistor to improve the performance of the device. 优选地,还可以在栅介质层1003中引入La2O3,以便降低最终形成的晶体管结构的阈值电压(Vt)。 Preferably, La2O3 may also be introduced in the gate dielectric layer 1003 in order to reduce the threshold voltage of the transistor structure formed by the final (Vt).

[0032] 在以上的描述中,对于各层的构图、刻蚀等技术细节并没有做出详细的说明。 [0032] In the above description, details of patterning the layers, and etching the detailed description is not made. 但是本领域技术人员应当理解,可以通过现有技术中的各种手段,来形成所需形状的层、区域等。 Those skilled in the art will appreciate, the prior art by various means, to form the desired shape of a layer, region and the like. 另外,为了形成同一结构,本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。 Further, to achieve the same structure, those skilled in the art can devise methods described above are not exactly the same way.

[0033] 以上参照本发明的实施例对本发明予以了说明。 [0033] The above embodiment of the present invention with reference to embodiments of the present invention to be described. 但是,这些实施例仅仅是为了说明的目的,而并非为了限制本发明的范围。 However, these examples are merely for illustrative purposes and are not intended to limit the scope of the invention. 本发明的范围由所附权利要求及其等价物限定。 Scope of the invention defined by the appended claims and their equivalents. 不脱离本发明的范围,本领域技术人员可以做出多种替换和修改,这些替换和修改都应落在本发明的范围之内。 Without departing from the scope of the invention, those skilled in the art can make various substitutions and modifications, such alterations and modifications are intended to fall within the scope of the invention.

Claims (14)

  1. 1. 一种金属氧化物半导体场效应晶体管,包括: 半导体衬底;在所述半导体衬底上形成的栅堆叠,所述栅堆叠包括高k栅介质层和栅极主体层; 侧墙,包括在所述栅堆叠外侧依次形成的第一侧墙和第二侧墙,所述第一侧墙由含La 氧化物形成。 A metal oxide semiconductor field effect transistor comprising: a semiconductor substrate; a gate formed on the semiconductor substrate of the stack, the gate stack comprises a high-k gate dielectric layer and a gate body layer; spacer, comprising the first sidewall and second sidewall are sequentially formed on the outer side of the gate stack, the first sidewall is formed by a La-containing oxide.
  2. 2.如权利要求1所述的晶体管,其中,所述高k栅介质层包括Hf02、HfSiO、HfSiON、 HfTaO, HfTiO, HfZrO, A1203、La2O3, ZrO2, LaAlO 和11¾ 中任一种或多种的组合。 2. The transistor according to claim 1, wherein the high-k gate dielectric layer comprises Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1203, La2O3, ZrO2, LaAlO, and any one or more of 11¾ combination.
  3. 3.如权利要求1所述的方法,其中,所述含La氧化物包括Lei203、LaAlO, LaHfO, LaZrO 中任一种或多种的组合。 The method according to claim 1, wherein the La-containing oxide comprises Lei203, LaAlO, LaHfO, LaZrO any one or plural combination.
  4. 4.如权利要求1所述的方法,其中,所述第一侧墙的厚度小于等于5nm。 4. The method according to claim 1, wherein the first sidewall thickness is less than equal to 5nm.
  5. 5.如权利要求1所述的方法,其中所述第二侧墙由氧化物形成。 5. The method according to claim 1, wherein the second spacer is formed of an oxide.
  6. 6.如权利要求1至5中任一项所述的方法,其中所述第二侧墙的外侧形成有第三侧墙。 6. The method according to claim 5 claim, wherein the second outer sidewall is formed with a third spacer.
  7. 7.如权利要求6所述的方法,其中所述第三侧墙为氧化物、氮化物或低k材料。 7. The method of claim 6, wherein the third spacer is an oxide, a nitride or a low k material requirements.
  8. 8.如权利要求7所述的方法,其中所述低k材料包括=SiO2, SiOF、SiCOH, SiO, SiCO, HSQ和MSQ中的任一种或多种的组合。 8. The method according to claim 7, wherein said material comprises low-k = SiO2, SiOF, SiCOH, SiO, SiCO, HSQ and MSQ any one or more combinations.
  9. 9. 一种制作金属氧化物半导体场效应晶体管的方法,包括: 提供半导体衬底;在所述半导体衬底上依次形成高k栅介质层、栅极主体层,并进行构图以形成栅堆叠; 在所述栅堆叠的外侧依次形成第一侧墙和第二侧墙,所述第一侧墙由含La氧化物形成。 A metal oxide semiconductor field effect transistor fabrication, comprising: providing a semiconductor substrate; sequentially forming a high-k gate dielectric layer, a gate electrode layer on the main body of the semiconductor substrate, and patterned to form a gate stack; the gate stack forming a first outer side wall and a second sidewall, the first sidewall is formed of a La-containing oxide.
  10. 10.如权利要求9所述的方法,其中在栅堆叠的外侧依次形成第一侧墙和第二侧墙的步骤包括:淀积第一氧化物层,并刻蚀所述第一氧化物层以在所述栅堆叠外侧形成第一侧墙,所述第一氧化物为含La氧化物;淀积第二氧化物层,并干法刻蚀所述第二氧化物层以在第一侧墙外侧形成第二侧墙。 10. The method according to claim 9, wherein forming a first sidewall and a second sidewall spacer on the outside of the gate stack comprising: depositing a first oxide layer, and etching the first oxide layer outside the gate stack to form a first spacer, the first oxide is a La-containing oxide; depositing a second oxide layer, the dry etching process and a second oxide layer on a first side the outer wall forming a second sidewall spacer.
  11. 11.如权利要求10所述的方法,其中所述含La氧化物为La2OyLaAWALaHfCKLaZrO中任一种或多种的组合。 11. The method according to claim 10, wherein the La-containing oxide is any one or plural combination La2OyLaAWALaHfCKLaZrO.
  12. 12.如权利要求9所述的方法,所述栅介质层包括Hf02、HfSiO、HfSiON、HfTaO, HfTiO, HfZr0,Al203> La2O3, ZrO2, LaAlO 和中任一种或多种的组合。 12. The method as claimed in claim 9, said gate dielectric layer comprises Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZr0, Al203> La2O3, ZrO2, LaAlO, and any combination of one or more thereof.
  13. 13.根据权利要求9至12中任一项所述的方法,在形成第二侧墙之后,还包括: 淀积第三氧化物层、氮化物层或低k材料层,并干法刻蚀所述第三氧化物层、氮化物层或低k材料层以在第二侧墙外侧形成第三侧墙。 9 to 12 13. A method according to any one of the claim, after forming the second sidewall spacer, further comprising: depositing a third oxide layer, a nitride layer or a low-k material layer and dry etching the third oxide layer, a nitride layer or a low-k material to form a third layer outside the second sidewall spacer.
  14. 14.如权利要求13所述的方法,其中所述低k材料包括:Si02、Si0F、SiC0H、Si0、SiC0、 HSQ和MSQ中的任一种或多种的组合。 14. The method according to claim 13, wherein said low-k material include: Si02, Si0F, SiC0H, Si0, SiC0, HSQ and MSQ any one or more combinations.
CN 201010181616 2010-05-19 2010-05-19 Metal oxide semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof CN102254945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201010181616 CN102254945A (en) 2010-05-19 2010-05-19 Metal oxide semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201010181616 CN102254945A (en) 2010-05-19 2010-05-19 Metal oxide semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN102254945A true true CN102254945A (en) 2011-11-23

Family

ID=44982069

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201010181616 CN102254945A (en) 2010-05-19 2010-05-19 Metal oxide semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN102254945A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105438962A (en) * 2015-12-31 2016-03-30 建峰索具有限公司 High-strength steel wire rope casting rigging

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1203445A (en) * 1997-06-23 1998-12-30 日本电气株式会社 Method of manufacturing semiconductor device of which parasitic capacitance is decreased
US6204112B1 (en) * 1997-07-18 2001-03-20 International Business Machines Corporation Process for forming a high density semiconductor device
US6630712B2 (en) * 1999-08-11 2003-10-07 Advanced Micro Devices, Inc. Transistor with dynamic source/drain extensions
CN101232015A (en) * 2007-01-22 2008-07-30 台湾积体电路制造股份有限公司 Semiconductor device
CN101425479A (en) * 2007-10-29 2009-05-06 台湾积体电路制造股份有限公司 High-k dielectric metal gate device structure and method for forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1203445A (en) * 1997-06-23 1998-12-30 日本电气株式会社 Method of manufacturing semiconductor device of which parasitic capacitance is decreased
US6204112B1 (en) * 1997-07-18 2001-03-20 International Business Machines Corporation Process for forming a high density semiconductor device
US6630712B2 (en) * 1999-08-11 2003-10-07 Advanced Micro Devices, Inc. Transistor with dynamic source/drain extensions
CN101232015A (en) * 2007-01-22 2008-07-30 台湾积体电路制造股份有限公司 Semiconductor device
CN101425479A (en) * 2007-10-29 2009-05-06 台湾积体电路制造股份有限公司 High-k dielectric metal gate device structure and method for forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105438962A (en) * 2015-12-31 2016-03-30 建峰索具有限公司 High-strength steel wire rope casting rigging
CN105438962B (en) * 2015-12-31 2017-10-03 建峰索具有限公司 A high-strength steel wire rope rigging casting

Similar Documents

Publication Publication Date Title
US6812111B2 (en) Methods for fabricating MOS transistors with notched gate electrodes
US20040266077A1 (en) Structure and method for forming the gate electrode in a multiple-gate transistor
US7388259B2 (en) Strained finFET CMOS device structures
US20070075351A1 (en) Semiconductor devices and methods of manufacture thereof
US20060214226A1 (en) Method for forming an SOI structure with improved carrier mobility and ESD protection
US20060175669A1 (en) Semiconductor device including FinFET having metal gate electrode and fabricating method thereof
US7172943B2 (en) Multiple-gate transistors formed on bulk substrates
US20150102411A1 (en) FinFET with Buried Insulator Layer and Method for Forming
US20110117679A1 (en) Sacrificial offset protection film for a finfet device
US20140001575A1 (en) Semiconductor devices having different gate oxide thicknesses
US20070102763A1 (en) Multiple-gate transistors formed on bulk substrates
US8174073B2 (en) Integrated circuit structures with multiple FinFETs
US20140264604A1 (en) FinFET Having Source-Drain Sidewall Spacers with Reduced Heights
US20100065925A1 (en) Local charge and work function engineering on mosfet
US20100078728A1 (en) Raise s/d for gate-last ild0 gap filling
US20140027783A1 (en) Semiconductor device and method of manufacturing the same
US20120146142A1 (en) Mos transistor and method for manufacturing the same
US20120217583A1 (en) Semiconductor device and method for forming the same
US20070063224A1 (en) Metal insulator semiconductor field effect transistor having fin structure
CN1695227A (en) Strained FinFET CMOS device structures
US20110089493A1 (en) Finfet method and device
US20020142523A1 (en) Method of fabricating semiconductor device having notched gate
US20080122011A1 (en) Variable width offset spacers for mixed signal and system on chip devices
US20060157750A1 (en) Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof
US8120073B2 (en) Trigate transistor having extended metal gate electrode

Legal Events

Date Code Title Description
C06 Publication
C10 Request of examination as to substance
C12 Rejection of an application for a patent