CN102237369A - Semiconductor germanium-base substrate material and preparation method thereof - Google Patents

Semiconductor germanium-base substrate material and preparation method thereof Download PDF

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CN102237369A
CN102237369A CN 201010151362 CN201010151362A CN102237369A CN 102237369 A CN102237369 A CN 102237369A CN 201010151362 CN201010151362 CN 201010151362 CN 201010151362 A CN201010151362 A CN 201010151362A CN 102237369 A CN102237369 A CN 102237369A
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germanium
substrate
semiconductor
layer
porous layer
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CN 201010151362
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CN102237369B (en )
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安霞
张兴
杜菲
郭岳
黄如
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北京大学
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

The invention provides a semiconductor germanium-base substrate material and a preparation method thereof and belongs to the technical field of manufacturing of super-large-scale integrated circuits. The method comprises the following steps of: forming a porous layer on a semiconductor substrate; arranging a semiconductor germanium sheet on the porous layer; and forming the semiconductor germanium-base substrate material on the porous layer. In the invention, by using a low dielectric constant of the porous layer and by forming the semiconductor germanium-base substrate material on the porouslayer, a coupling effect of a drain terminal on the potential of a trench by a buried layer can be effectively reduced, so a drain induced barrier lowering (DIBL) effect is effectively restrained, the parasitic capacitance of a source, a drain and a substrate can be reduced, and the speed characteristic of a device is improved. Meanwhile, the invention provides the preparation method of the semiconductor germanium-base substrate material. An ultra-thin semiconductor germanium material is prepared on a porous insulating layer by skillfully using an intelligent liftoff technology. The inventionsolves the problem of thinning during the application of a bonded and etched-back silicon-on-insulator (BESOI) technology and has the advantages of a separation by implantation of oxygen (SIMOX) technology and a bonding technology.

Description

一种半导体锗基衬底材料及其制备方法 A semiconductor substrate, a germanium substrate material and method

技术领域 FIELD

[0001] 本发明属于超大规模集成电路工艺制造技术领域,具体涉及一种锗基衬底材料及其制备方法。 [0001] The present invention belongs to the field of ultra large scale integrated circuit fabrication process technology, particularly relates to a germanium-based substrate material and its preparation method.

背景技术 Background technique

[0002] 随着器件尺寸地不断缩小,载流子迁移率退化成为影响器件性能提升的关键因素之一。 [0002] As device sizes continue to shrink, the carrier mobility degradation become one of the key factors affecting the performance of the device. 与硅材料相比,锗材料具有较低的载流子有效质量,更高、更加对称的低场载流子迁移率,能带宽度窄,而且与硅CMOS工艺兼容,因此,锗基器件是高速MOSFET器件一个很有希望的方向。 Compared with silicon, germanium material having a lower carrier effective mass, higher, more symmetrical carrier mobility, low bandgap narrower field, and is compatible with silicon CMOS process, and therefore, the device is a germanium- High-speed MOSFET device is a promising direction. 为了实现更好的器件特性,锗基衬底材料的制备也是当前关注的热点之一。 For better device characteristics, the preparation of a germanium-based substrate materials are also currently focused hot spot.

[0003] 绝缘体上的锗材料(GeOI)由于结合了体锗材料和绝缘体上的硅材料(SOI)的优势,成为当前工业界和学术界的关注焦点之一,人们也提出了不同的制备方法,如锗聚集技术等。 [0003] germanium material (GeOI) on the insulator due to a combination of silicon germanium material on the body and insulator (SOI) advantage, become one of the focus of the current industry and academia, people have proposed different methods of preparation , such as germanium aggregation technology. 然而,锗与SiO2界面接触特性较差,从而会使相应的器件性能退化。 However, SiO2 interface in contact with the germanium poor characteristics such degradation causes the corresponding device. 对于SOI器件,漏还会通过隐埋氧化层影响沟道电势,因而DIBL效应加剧,器件性能进一步退化。 For SOI devices, the channel potential will also affect the leakage through the buried oxide layer, thereby increasing DIBL effect, further degradation of device performance. 虽然减小埋层的厚度可抑制DIBL效应,但会增大源漏与衬底之间的寄生电容,使得器件性能退化。 Although the thickness of the buried layer is reduced DIBL effect can be suppressed, but the parasitic capacitance between the source and drain and the substrate increases, so that the device performance degradation. 因此对于GeOI材料,改变埋层介质材料是改善器件性能的有效方式。 Thus for GeOI material, changing the dielectric material buried layer is an effective way to improve device performance.

发明内容 SUMMARY

[0004] 本发明克服了现有技术中的不足,提供了一种多孔层上锗基衬底材料及其制备方法。 [0004] The present invention overcomes the disadvantages of the prior art, there is provided a method of preparing a germanium substrate material and a porous layer on the substrate.

[0005] 本发明的技术方案是: [0005] aspect of the present invention is:

[0006] 一种半导体锗基衬底材料,其特征在于,包括一半导体基片,在半导体基片上形成一多孔层,在多孔层上设有半导体锗片,形成多孔层上锗基衬底材料。 [0006] A germanium-based semiconductor material substrate, characterized in that it comprises a semiconductor substrate, forming a porous layer on a semiconductor substrate, a germanium semiconductor substrate provided on the porous layer, a germanium layer is formed on the porous base substrate material.

[0007] 所述半导体基片是硅片或者锗片,半导体基片上的多孔层厚度范围为30nm-400nm。 [0007] The semiconductor substrate is a silicon or germanium substrate, the thickness of the porous layer on a semiconductor substrate a range of 30nm-400nm.

[0008] 在半导体锗层与多孔层之间可设有一钝化层。 [0008] between the germanium layer and the porous semiconductor layer may be provided with a passivation layer. 所述钝化层为氮氧锗,其厚度为0. 7nm-3nm。 The passivation layer is a germanium oxynitride having a thickness of 0. 7nm-3nm.

[0009] 锗片为体锗片或硅上外延锗片。 [0009] Germanium is a sheet or on a bulk germanium epitaxial silicon germanium film.

[0010] 一种半导体锗基衬底材料的制备方法,包括以下步骤: [0010] A process for producing a semiconductor substrate, a germanium substrate material, comprising the steps of:

[0011] 1)采用多孔硅或多孔锗技术,在半导体基片形成一多孔层; [0011] 1) porous or porous silicon germanium technology, a porous layer is formed in a semiconductor substrate;

[0012] 2)半导体锗片上形成表面钝化层(氮氧锗层); [0012] 2) a surface passivation layer (germanium oxynitride layer) is formed on a germanium substrate;

[0013] 3)对半导体锗片进行H+注入; [0013] 3) of the germanium substrate for H + implantation;

[0014] 4)将半导体基片的位于多孔层一面与半导体锗片的位于氮氧锗层一面进行低温键合; [0014] 4) The porous layer of the semiconductor substrate located on one side of the semiconductor layer located in a germanium oxynitride bonded to one surface of a low temperature germanium sheet;

[0015] 5)对上述键合片进行热处理,温度为400-600°C,使半导体锗片在H+注入射程分布峰值处剥离,从而形成多孔层上锗基衬底结构。 [0015] 5) of the bonding sheet is heat-treated at a temperature of 400-600 ° C, the semiconductor Germanium implantation depth profile in H + peak peel, thereby forming a germanium-substrate structure on the porous layer.

[0016] 6)对上述多孔层上锗基衬底退火处理来增加键合强度,并再利用CMP技术抛光,以完成半导体锗基衬底材料的制备。 [0016] 6) of the porous layer on the substrate, a germanium-annealing treatment to increase bonding strength, and then polishing using a CMP technique, to complete preparation of a germanium-based semiconductor material of the substrate.

[0017] 所述H+注入射程分布峰值距离锗片表面在30-150nm之间,注入剂量在lel6-lel7cnT2 之间。 [0017] The H + implantation depth distribution of germanium substrate surface peak distance between 30-150nm, implantation dose is between lel6-lel7cnT2.

[0018] 其中,所述半导体基片与半导体锗片键合温度一股为150-300°C。 [0018] wherein the semiconductor substrate and the semiconductor Germanium is an bonding temperature 150-300 ° C.

[0019] 所述退火温度150_250°C,退火时间为5_150h。 The [0019] annealing temperature 150_250 ° C, annealing time 5_150h.

[0020] 与现有技术相比,本发明的有益效果是: [0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] 1)多孔层的介电常数约为1. 0,是最理想的埋层。 Dielectric constant [0021] 1) a porous layer is approximately 1.0, the buried layer is ideal.

[0022] 2)利用了多孔层的低介电常数,在多孔层上形成Ge衬底材料,可以有效减小漏端通过埋层对沟道和源端的电势耦合作用,从而有效抑制DIBL效应; [0022] 2) the use of low dielectric constant porous layer, a Ge substrate material is formed on the porous layer, can effectively reduce the drain terminal through the buried layer and the channel coupling the source of electrical potential, thereby effectively suppressing DIBL effect;

[0023] 3)降低源漏和衬底的寄生电容改善器件速度特性; [0023] 3) the speed of the device to reduce parasitic capacitance to improve the characteristics of the source-drain and the substrate;

[0024] 4)减小了寄生电容,降低了漏电,功耗更低; [0024] 4) reduces parasitic capacitance, reduced leakage, lower power consumption;

[0025] 5)消除了闩锁效应; [0025] 5) eliminating the latch;

[0026] 6)抑制衬底脉冲电流的干扰; [0026] 6) a pulse current suppressing interference of the substrate;

[0027] 7)避免了锗与二氧化硅界面接触特性差的问题; [0027] 7) avoids germanium SiO2 interface problem of poor contact characteristics;

[0028] 8)本发明提供的这种半导体锗基衬底材料的制备方法,巧妙利用智能剥离技术在多孔绝缘层上制备超薄的半导体锗材料。 Preparation of [0028] 8) The method of such a semiconductor material is germanium-based substrate provided by the present invention, the preparation of ultra-thin semiconductor ingenious germanium material on the porous insulating layer using a Smart Cut technology. 这样既解决了运用BESOI技术时减薄的困难,同时又兼顾了SIMOX技术和键合技术的优点。 This will not only solve the problem of thinning when using BESOI technology, while taking into account the advantages of SIMOX technology and bonding technology.

[0029] 9)制备工艺简单,且与传统硅工艺兼容。 Preparation of [0029] 9) the process is simple and compatible with conventional silicon process.

附图说明 BRIEF DESCRIPTION

[0030] 图1是本发明半导体锗基衬底材料的结构示意图; [0030] FIG. 1 is a schematic view of a semiconductor substrate, a germanium substrate material of the present invention;

[0031] 图2是本发明制备工艺流程图。 [0031] FIG. 2 is a process flow diagram for the preparation of the present invention.

具体实施方式 detailed description

[0032] 下面结合附图和具体实施方式对本发明作进一步详细描述: [0032] The present invention will be described in further detail in conjunction with accompanying drawings and specific embodiments:

[0033] 图1是本发明半导体锗基衬底材料的示意图。 [0033] FIG. 1 is a schematic diagram of the present invention, the germanium-based semiconductor material of the substrate. 其中包括半导体基片1,其上形成的多孔层2,半导体锗片3,以及界面处的钝化层4。 Wherein the substrate comprises a semiconductor substrate 1, a passivation layer 43, and at the interface of the porous layer 2, the germanium sheet formed thereon.

[0034] 图2是本发明制作半导体锗基衬底材料的各步骤工艺流程图。 [0034] FIG. 2 is a process flow diagram of the steps of making a germanium-based semiconductor material of the substrate of the present invention. 本发明制作半导体锗基衬底材料的方法包括如下步骤: The method of making a germanium-based semiconductor material of the substrate of the present invention comprises the steps of:

[0035] 步骤一:半导体基片1上形成多孔层2,如图2(a)所示。 [0035] Step a: 2, FIG. 2 (a) forming a porous layer 1 shown in the semiconductor substrate.

[0036] 采用多孔硅或者多孔锗技术在半导体基片1上形成多孔层2。 [0036] The porous layer 2 is a porous silicon germanium technology or a porous formed on the semiconductor substrate 1. 多孔层2的厚度和孔密度由电解条件决定,一股控制多孔层2厚度在30nm至400nm之间,且孔密度在30%至97%之间。 The thickness of the porous layer and the pore density is determined by the electrolysis conditions, control of the thickness of the porous layer 2 is an between 30nm to 400 nm, and a pore density between 30% to 97%.

[0037] 步骤二:半导体锗片3上生成氮氧锗钝化层4 (GeON),如图2(b)所示。 [0037] Step Two: generating sheet 3 germanium germanium oxynitride passivation layer 4 (GeON), FIG. 2 (b) shown in FIG.

[0038] 对半导体锗片3进行表面处理,首先用1 : 50的HF漂去表面的自然氧化层,再生长一层氮氧锗层4作为健合的表面钝化层,有助于改善半导体锗片3和半导体基片1的界面质量,从而改善制备的半导体衬底材料的质量。 [0038] 3 pieces of the germanium surface treated first with 1: HF 50 drift to the surface of the native oxide layer, and then growing a germanium oxynitride layer as a surface passivation layer 4 bonded healthy, it helps to improve the semiconductor germanium 3 and the semiconductor substrate 1 interface quality, thereby improving the quality of the semiconductor substrate materials prepared. 氮氧锗层4的厚度为0. 7-3nm。 The thickness of the germanium oxynitride layer 4 is 0. 7-3nm.

[0039] 本实施例中制备氮氧锗层4的方法是,首先,半导体锗片3在氧气中退火,温度为500-600°C,生成氧化锗。 Method [0039] In this example embodiment prepared oxynitride germanium layer 4 is, first, the semiconductor chip 3 germanium annealing in oxygen at a temperature of 500-600 ° C, to generate germanium oxide. 氧化锗的厚度由退火时间决定,一股控制在IOs至aiiin。 Germanium oxide thickness is determined by the annealing time, the IOs to control an aiiin. 然后通入氮气排空氧气,同时温度降为300至400°C。 Nitrogen gas was then evacuated of oxygen, while the temperature was reduced to 300 to 400 ° C. 最后锗片4在氨气气氛中退火600°C,时间30s-aiiin,引入氮以生成氮氧锗层4。 Germanium 4 finally annealed 600 ° C in ammonia atmosphere, time of 30s-aiiin, introducing nitrogen to create the germanium oxynitride layer 4. 同时,氮的引入不局限于在氨气中退火,也可以采用在Ν20、Ν0中退火的方法,或者是用ICP方法引入高密度的反应离子氮。 At the same time, the introduction of nitrogen in the annealing is not limited to ammonia, may be used in Ν20, Ν0 annealing method, or the introduction of a high density of reactive ion nitrogen ICP method. 另外,也可以采用不做氧化,直接在氨气气氛中退火以生成氮氧锗层4的方法。 Further, oxidation may not be used directly in ammonia atmosphere annealing method to form a germanium oxynitride layer 4.

[0040] 步骤三:对半导体锗片3中进行H+注入,如图2(c)所示。 [0040] Step Three: on the semiconductor chip 3 is H + Ge implantation, as shown in FIG. 2 (c).

[0041] 在半导体锗片3中注入H+后,在后续剥离热处理过程中会在注入的投影射程分布峰值处5形成空腔层,从而实现半导体锗片3从半导体基片1上智能剥离。 After [0041] H + was implanted in the semiconductor chip 3 germanium, delamination heat treatment in a subsequent process will be at the peak of the distribution layer to form a cavity 5 in the projection range of implanted, thereby realizing a semiconductor chip 3 on the smart germanium peeled from the semiconductor substrate 1. 智能剥离的位置由注入H+的能量决定,一股控制H+注入射程分布峰值在距离半导体锗片3表面30-150nm 之间。 Smart peeling position is determined by the implantation energy of H + and H + to control an injection range distribution peak distance between the surface of the germanium substrate 3 30-150nm. 注入氢的剂量在lel6〜Ie 17cm"2之间。 Hydrogen implantation dose of between lel6~Ie 17cm "2.

[0042] 步骤四:半导体基片1与半导体锗片3低温键合,如图2(d)所示。 [0042] Step Four: the semiconductor substrate 1 and the semiconductor chip 3 germanium low bonding, as shown in FIG 2 (d) shown in FIG.

[0043] 将半导体基片1的位于多孔层2 —面与半导体锗片3的位于氮氧锗层4 一面进行低温键合,为了防止界面变差、锗外扩散和注入的氢形成空腔层,采用低温健合工艺,键合温度一股为150-300°C。 [0043] The semiconductor substrate 1 is located in the porous layer 2 - surface of the germanium oxynitride sheet 3 is positioned germanium layer 4 bonded to one side of a low temperature, in order to prevent deterioration of the interface, the external diffusion of germanium and hydrogen implanted layer to form a cavity , health low temperature bonding process, the bonding temperature of an 150-300 ° C.

[0044] 步骤五:采用智能剥离技术,形成多孔层上的锗基衬底材料结构,如图2(e)所示。 [0044] Step Five: smart lift-off technique, the substrate material is formed germanium-based structure on the porous layer, as shown in FIG 2 (e) shown in FIG.

[0045] 对键合片进行热处理,温度为400-600°C,使半导体锗片3在H+注入射程分布峰值(Rp)处5起泡剥离,使半导体锗片3上的一薄层单晶Ge转移到半导体基片1上键合形成多孔层上锗基衬底材料结构,如图2(f)所示。 [0045] The heat-treated sheet is bonded, a temperature of 400-600 ° C, the germanium semiconductor substrate 3 in H + implantation profile peak range (Rp) at the 5-foaming release, so that a thin layer of single-crystal germanium on a semiconductor chip 3 Ge is transferred to the semiconductor substrate 1 bonded to the germanium-formed on the porous layer structure of the substrate material, FIG. 2 (f) shown in FIG. 半导体锗片3剩余部分可以继续使用。 The remaining portion of the semiconductor chip 3 can continue to use the germanium.

[0046] 步骤六:进一步退火处理来增加键合强度,并利用CMP技术再抛光。 [0046] Step Six: further annealed to increase the bonding strength, and then polishing using CMP technique.

[0047] 通过退火处理来增加键合强度,一股为150_250°C,退火时间为5_150h。 [0047] to increase the bonding strength by an annealing treatment, as an 150_250 ° C, annealing time 5_150h. 为改善表面状况及均勻性,需再利用CMP技术抛光。 In order to improve the surface condition and uniformity, to be reused CMP technique polishing. 至此完成该半导体锗基衬底材料的制备。 Preparation of the germanium-based semiconductor material of the substrate thus completed.

[0048] 以上通过详细实施例描述了本发明所提供的半导体锗基衬底材料,本领域的技术人员应当理解,在不脱离本发明实质的范围内,可以对本发明做一定的变换或修改;其制备方法也不限于实施例中所公开的内容。 Detailed embodiments described in the germanium-based substrate material of the present invention provides [0048] the above by those skilled in the art will appreciate, without departing from the spirit scope of the invention may be made in certain transformation or modification of the present invention; the preparation method is not limited to those embodiments disclosed embodiments.

Claims (10)

  1. 1. 一种半导体锗基衬底材料,其特征在于,包括一半导体基片,在半导体基片上形成一多孔层,在多孔层上设有半导体锗片,形成多孔层上锗基衬底材料。 A germanium-based semiconductor material substrate, characterized in that it comprises a semiconductor substrate, forming a porous layer on a semiconductor substrate, a germanium semiconductor substrate provided on the porous layer, the porous layer is formed on the germanium-based substrate material .
  2. 2.如权利要求1所述的半导体锗基衬底材料,其特征在于,所述半导体基片是硅片或者锗片。 2. The semiconductor germanium-based substrate material according to claim 1, wherein said semiconductor substrate is a silicon or germanium substrate.
  3. 3.如权利要求1或2所述的半导体锗基衬底材料,其特征在于,所述多孔层厚度范围为30nm-400nm。 Germanium-based semiconductor material or substrate according to claim 12, characterized in that the porous layer thickness in the range of 30nm-400nm.
  4. 4.如权利要求1所述的半导体锗基衬底材料,其特征在于,所述半导体锗片与多孔层之间有一钝化层。 Germanium-based semiconductor material of the substrate as claimed in claim 1, wherein a passivation layer between the germanium layer and the porous sheet.
  5. 5.如权利要求4所述的半导体锗基衬底材料,其特征在于,所述钝化层为氮氧锗,其厚度为0. 7nm-3nm。 The germanium-based semiconductor material substrate according to claim 4, wherein the passivation layer is a germanium oxynitride having a thickness of 0. 7nm-3nm.
  6. 6.如权利要求1所述的半导体锗基衬底材料,其特征在于,所述锗片为体锗片或硅上外延锗片。 Germanium-based semiconductor material of the substrate as claimed in claim 1, characterized in that the germanium plate is a sheet on a bulk germanium or silicon germanium epitaxial film.
  7. 7. 一种半导体锗基衬底材料的制备方法,包括以下步骤:1)采用多孔硅或多孔锗技术,在半导体基片上形成一多孔层;2)半导体锗片上形成氮氧锗层;3)对半导体锗片进行H+注入;4)将半导体基片的位于多孔层一面与半导体锗片的位于氮氧锗层一面进行低温键合;5)对上述键合结构进行热处理,温度为400-600°C,使半导体锗片在H+注入射程分布峰值处剥离,从而形成多孔层上锗基衬底;6)对上述多孔层上锗基衬底材料进行退火处理,并利用CMP技术抛光。 A method of preparing a semiconductor substrate, a germanium substrate material, comprising the following steps: 1) porous or porous silicon germanium technology, a porous layer is formed on a semiconductor substrate; germanium oxynitride layer 2 is formed) of the semiconductor chip germanium; 3 ) of germanium slices H + implanted; a porous layer 4) of the semiconductor substrate on one side located oxynitride layer of germanium semiconductor germanium is a low temperature bonding side; 5) of the bonding structure is heat-treated at a temperature of 400- 600 ° C, the semiconductor germanium implantation depth profile in H + peak peel, thereby forming a porous layer on the substrate, a germanium substrate; 6) of the porous layer on a germanium substrate the substrate material is annealed, and polished by the CMP technique.
  8. 8.如权利要求7所述的方法,其特征在于,步骤3) H+注入射程分布峰值在距离锗片表面30-150nm之间,注入剂量在lel6-lel7cnT2之间。 8. The method according to claim 7, wherein the step 3) H + implanted between the peak of the distribution in the range 30 to 150 nm from the surface of the germanium substrate, the implantation dose between lel6-lel7cnT2.
  9. 9.如权利要求7或8所述的方法,其特征在于,步骤4)低温键合温度为150-300°C。 9. The method according to claim 78, wherein step 4) bonding temperature is low 150-300 ° C.
  10. 10.如权利要求7所述的方法,其特征在于,所述步骤6)中退火温度150-250°C,退火时间为5-150h。 10. The method according to claim 7, wherein said step 6), the annealing temperature 150-250 ° C, annealing time 5-150h.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409411A (en) * 2014-11-24 2015-03-11 上海华虹宏力半导体制造有限公司 Semiconductor device and forming method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1698206A (en) * 2003-05-06 2005-11-16 佳能株式会社 Substrate, manufacturing method therefor, and semiconductor device
CN1956149A (en) * 2005-10-26 2007-05-02 国际商业机器公司 Methods for forming germanium-on-insulator semiconductor structures and semiconductor structures formed by these methods
US20080286952A1 (en) * 2007-05-18 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004073043A3 (en) * 2003-02-13 2005-04-21 Zhiyuan Cheng Semiconductor-on-insulator article and method of making same
US7365399B2 (en) * 2006-01-17 2008-04-29 International Business Machines Corporation Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1698206A (en) * 2003-05-06 2005-11-16 佳能株式会社 Substrate, manufacturing method therefor, and semiconductor device
CN1956149A (en) * 2005-10-26 2007-05-02 国际商业机器公司 Methods for forming germanium-on-insulator semiconductor structures and semiconductor structures formed by these methods
US20080286952A1 (en) * 2007-05-18 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409411A (en) * 2014-11-24 2015-03-11 上海华虹宏力半导体制造有限公司 Semiconductor device and forming method thereof
CN104409411B (en) * 2014-11-24 2017-12-08 上海华虹宏力半导体制造有限公司 The method for forming a semiconductor device and

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