CN102205943A - Preparation method of monocrystalline silicon nanostructure - Google Patents
Preparation method of monocrystalline silicon nanostructure Download PDFInfo
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- CN102205943A CN102205943A CN2011100894212A CN201110089421A CN102205943A CN 102205943 A CN102205943 A CN 102205943A CN 2011100894212 A CN2011100894212 A CN 2011100894212A CN 201110089421 A CN201110089421 A CN 201110089421A CN 102205943 A CN102205943 A CN 102205943A
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Abstract
The invention discloses a preparation method of a monocrystalline silicon nanostructure. The preparation method comprises the following steps of: forming a mask pattern on a silicon substrate or an SOI (Silicon On Insulator) wafer serving as a substrate according to a required monocrystalline silicon nanostructure, wherein the line width of the mask pattern is not more than 2 mum; etching to form a micrometer-grade silicon structure, and then oxidizing the substrate to form a silicon dioxide layer on the surface of silicon; and finally etching off the silicon dioxide layer by using a hydrofluoric acid solution, wherein because partial silicon can be consumed during oxidation, the line width of the micrometer-grade silicon structure can be reduced so that the monocrystalline silicon nanostructure can be obtained. In the invention, the method combining common photoetching and thermal oxidation is used for preparing the monocrystalline silicon nanostructure, has the advantages of good compatibility, low cost and the like, is convenient in operation and large-scale production, and has better line width controllability compared with the traditional nanostructure preparation method based on a micromachining process.
Description
Technical field
The present invention relates to the minute mechanical and electrical system field, particularly a kind of preparation method that is applied to the monocrystalline silicon nanostructured in the micro-nano mechanical device.
Background technology
Nano-fabrication technique, nanoelectronics, nanobiology, nanomaterial science are four big fields of nanosecond science and technology, wherein, nano-fabrication technique is as one of center of nanometer technology, be basic " art " of mixing other diverse discipline, it is the basis of current nano science research, it not only provides strong means for the research and the expansion of nano science every field, and is the pillar of following nanometer industry, especially in the nanoelectronics field.Nano-fabrication technique is the driving source of nanoelectronics development, and both fusions indicate that human science and technology will enter into one and stride the development of times stage.
The method of making nanostructured at present mainly contains chemical synthesis and self assembly, template manufacturing and " from top to bottom " the micro-nano mechanical manufacturing method of " from bottom to top ".Though different technology is very important for producing specific structure, but nobody can provide a comprehensive solution to make nanostructured, this is because there are different shortcomings in each method, as adaptability limited in the form, narrow application, complicated experimental provision etc.
In recent years, semiconductor nano material and device research obtain people's great attention, utilize " from bottom to top " technology of preparing and template manufacturing technology, quantum dot, nano wire, the nano tube structure of materials such as Cde, CdSe, CdS, HgS, CdHgTe, Si, Ge, SiGe prepared in people growth, and the novel physical property that shows based on the semiconductor nano device of these materials provides opportunity for the development of microelectronics and opto-electronic device.But structures one such as the quantum dot that these class methods are prepared, quantum wire, nanotube are the three dimension scales of structure is not easy to independent control, the 2nd, be difficult for realizing striding the processing of micro/nano-scale, to realize electrical interconnection, the most important thing is the monocrystalline silicon nanostructured that this technology can not be prepared high-quality, hang down defect state density.
" from top to bottom " micro-nano Machining Technology is the possible production method of preparation monocrystalline silicon nanostructured.Utilize the micro-nano Machining Technology, the researcher prepares monocrystalline silicon nanometer cantilever beam, and has realized that its highly sensitive biochemical sensitive detects application, and the mass measurement resolution ratio of nanometer cantilever beam can reach 10
-21G[Yang, Y.T.et al.Nano Lett.6,583-586 (2006); Arlett, J.L.et al.Nano Lett.6,1000-1006 (2006)]; The monocrystalline silicon nano line (silicon NWs) of development can combine with MOSFET and carry out such as protein, the detection of large biological molecules such as DNA [Clara Moldovan et al.Semiconductor Conference, 2009.CAS 2009.International.Vol.2.pp.549-552], also can be used for photonic crystal research [V.Poborchii, T.Tada, T.Kanayama, Opt.Commun., vol.210, pp.285-290,2002].At present, the main method for preparing the monocrystalline silicon nanostructured from top to bottom is the direct electronic beam write method, and electron-beam direct writing is a very expensive and technology consuming time.Other method is side wall mask technique and photoresist ashing technology.These two kinds of methods all are to utilize the material of deposit or the photoresist of silication to form side wall earlier, carry out etching with this as mask again, obtain nano wire, but the live width controllable degree are not high.
Summary of the invention
The preparation method that the purpose of this invention is to provide a kind of monocrystalline silicon nanostructured, this method cost of manufacture is low, simple and reliable process, with micromachined technology and IC process compatible, and the easy processing that realizes striding millimeter, micron, nanoscale.
The inventive method can be on silicon chip or soi wafer work sheet crystal silicon nanostructured, machinable structure includes but not limited to silicon nanowires and nano dot, the monocrystalline silicon nanostructured that is processed can be applicable to make micro-nano mechanical senser element and nanometer quantum device.
The present invention utilizes the lateral oxidation consume silicon in the silicon thermal oxidation process to make the monocrystalline silicon nanostructured.According to Deal-Grove model, the thermal oxide of silicon is divided into 4 continuous processes:
1) oxidant passes gas-substrate boundary-layer from gas interior with the form of diffusion and moves to gas-SiO
2The interface;
2) oxidant passes silica with the form of diffusion, arrives silica-silicon interface;
3) oxidant generates silica at silicon face and pasc reaction;
4) Fan Ying accessory substance leaves the interface.
Under the condition of quasistatic approximation, obtain the thickness x of silica and the pass of oxidization time t and be:
A in the formula, B, τ are the constant relevant with material and technological parameter.On the other hand, this model think oxidant always with the form of diffusion near reactant, chemical reaction takes place, leave reactant with the form of diffusion again.This is similar to the diffusion of impurity in monocrystalline silicon, in the longitudinal diffusion oxidation, the sideways diffusion oxidation will take place inevitably.In the process of oxidation, oxidant can diffuse through silica-silicon interface and consume silicon, and the silica of growth unit thickness need consume the silicon of 0.44 unit thickness.For both sides all by the silicon under the mask that can oxidation, if think that two sidewall oxidation speed are equal to, oxidation growth 50nm so, the silica that 100nm and 300nm are thick will can consume 44nm respectively at sidewall, the silicon that 88nm and 264nm are thick.
If make the structure of micron order live width earlier with the method for conventional photoetching, carry out thermal oxide again, along with the increase of oxide thickness, oxidant meeting sideways diffusion also consumes silicon so, erode silica with hydrofluoric acid more at last, will make the silicon structure live width be reduced to nanometer scale.Based on this principle, the present invention adopts following technical scheme:
A kind of preparation method of monocrystalline silicon nanostructured comprises the steps:
1) with silicon chip or soi wafer as substrate, on substrate, make mask layer, form mask pattern, mask pattern live width≤2 μ m according to needed monocrystalline silicon nanostructured;
2) substrate is carried out oxidation, form silicon dioxide layer at silicon face, and consume part silicon;
3) erode silica with hydrofluoric acid solution, obtain the monocrystalline silicon nanostructured.
Further, above-mentioned steps 1) method that forms mask pattern can be: thermal oxide growth one deck Si0 on substrate earlier
2As cushion and sacrifice layer, deposit one deck silicon nitride forms the photoresist mask by photoetching process then as mask layer on silicon nitride layer again, and etch silicon nitride layer and silicon dioxide layer form mask pattern again.The live width of mask pattern is according to the precision of common photoetching and for the time that reduces subsequent oxidation defines, generally at 1～2 μ m.In this step, preferably adopt low-pressure chemical vapor phase deposition technology (LPCVD) deposit silicon nitride; Adopt reactive ion etching technology (RIE) etch silicon nitride layer and silicon dioxide layer.
For ease of the side diffusion of the structure of oxidant under mask pattern, above-mentioned steps 1) and 2) between can further increase following step: adopt ASE (Advance Silicon Etch) etched substrate silicon, form the silicon bench of certain altitude.In order to prevent that nanostructured (as nano wire) from rupturing and come off, but the degree of depth is unsuitable excessive, and the silicon bench height is 0.1 μ m-5 μ m.
Above-mentioned steps 2) in order to guarantee the structure live width, adopt oxidation rate wet-oxygen oxidation method faster usually earlier, adopt the slower dry-oxygen oxidation method of oxidation rate again.Oxidization time is determined according to the size of needed nanostructured.Because dry-oxygen oxidation speed only is 0.3nm/min, so the nanostructure size ratio is easier to control.
The present invention is based on micromachined technology, propose lateral oxidation consume silicon in a kind of thermal oxidation process that utilizes silicon and made the processing method of monocrystalline silicon nanostructured, this method has not only possessed the advantage of traditional MEMS technology, good, easy to operate, with low cost such as compatibility, be convenient to large-scale production etc., with respect to the method for utilizing side wall and photoresist ashing, have better live width controllability simultaneously.
Description of drawings
Fig. 1 (a)-(e) is the process flow diagram of embodiment of the invention making monocrystalline silicon nano line, wherein: (a) shown the step that forms silica cushion and silicon nitride mask; (b) shown that photoetching and etching form the step of mask pattern; (c) shown that etch silicon forms the step of step; (d) shown the step of silicon oxide substrate; (e) shown that buffered hydrofluoric acid solution selective corrosion silica forms the step of nanostructured.
Fig. 2 is the stereoscan photograph that adopts the micro wire structure that obtains after common photoetching and the etch silicon.
Fig. 3 is the silicon nanowires stereoscan photograph behind the micro wire structure process wet-oxygen oxidation 300nm.
Fig. 4 is the silicon nanowires stereoscan photograph after Fig. 3 structure is carried out the 200nm wet-oxygen oxidation again.
Fig. 5 is the silicon nanowires stereoscan photograph after Fig. 4 structure is carried out the 50nm dry-oxygen oxidation again.
The specific embodiment
Monocrystalline silicon nanostructured of the present invention can be processed on silicon substrate or soi wafer, and version includes but not limited to one dimension silicon nanowires and zero-dimension nano point.Below in conjunction with accompanying drawing, the present invention is described further by embodiment.
Referring to Fig. 1, prepare the monocrystalline silicon nanostructured according to following step:
1) adopt silicon chip or soi wafer as substrate 1, at first thermal oxide growth layer of silicon dioxide layer 2 adopts low-pressure chemical vapor phase deposition (LPCVD) deposition techniques one deck silicon nitride layer 3 as etch mask as cushion and sacrifice layer again, sees Fig. 1 (a);
2) photoetching forms the photoresist mask, adopts reactive ion etching (RIE) to etch away silica and silicon nitride layer, form mask pattern 4, according to the precision of common photoetching and in order to reduce the time of subsequent oxidation, the live width of figure is defined in 1～2 μ m, sees Fig. 1 (b);
3) adopt the ASE etch silicon, form the silicon bench 5 of certain altitude, see Fig. 3 (c);
4) structure after the etching is carried out oxidation, form oxide layer 6 on the silicon bench surface, and can consume part silicon, reduce physical dimension, see Fig. 1 (d).In order to guarantee the structure live width, adopt oxidation rate wet-oxygen oxidation method faster usually earlier, adopt the slower dry-oxygen oxidation method of oxidation rate again.Oxidization time is determined according to needed nanostructure size.
Because dry-oxygen oxidation speed only is 0.3nm/min, so the nanostructure size ratio is easier to control.
5) adopt the buffered hydrofluoric acid solution corrosion to fall silica at last, obtain monocrystalline silicon nanostructured 7, see Fig. 1 (e).Because there is silicon dioxide sacrificial layer in body structure surface, and the silicon nitride mask layer is peeled off simultaneously.
Comparison diagram 2-5, Fig. 2 be for obtaining the micro wire structure after common photoetching and the etch silicon, and Fig. 3 is the silicon nanowires stereoscan photograph of micro wire structure after through wet-oxygen oxidation 300nm.Fig. 4 is the silicon nanowires stereoscan photograph after Fig. 3 structure is carried out the 200nm wet-oxygen oxidation again.Fig. 5 is the silicon nanowires stereoscan photograph after Fig. 4 structure is carried out the 50nm dry-oxygen oxidation again.Record Fig. 5 structure live width at last and be about 30～40nm.
More than described the present invention by the specific embodiment and utilize the lateral oxidation consume silicon to make the method for monocrystalline silicon nanostructured, it will be understood by those of skill in the art that foregoing description should not be considered as limitation of the present invention.In the scope that does not break away from the present invention's spirit and essence, can make certain deformation or modification to the present invention, protection scope of the present invention is decided on appended claims.
Claims (7)
1. the preparation method of a monocrystalline silicon nanostructured comprises the steps:
1) with silicon chip or soi wafer as substrate, on substrate, make mask layer, form mask pattern, mask pattern live width≤2 μ m according to needed monocrystalline silicon nanostructured; 2) substrate is carried out oxidation, form silicon dioxide layer at silicon face, and consume part silicon;
3) erode silica with hydrofluoric acid solution, obtain the monocrystalline silicon nanostructured.
2. preparation method as claimed in claim 1, it is characterized in that, described step 1) is thermal oxide growth silicon dioxide layer and deposit silicon nitride layer successively on substrate earlier, and photoetching forms the photoresist mask then, and etch silicon nitride layer and silicon dioxide layer form mask pattern again.
3. preparation method as claimed in claim 2 is characterized in that, the live width of described mask pattern is 1～2 μ m.
4. preparation method as claimed in claim 2 is characterized in that, adopts low-pressure chemical vapor phase deposition deposition techniques silicon nitride in the described step 1); Adopt reactive ion etching technology etch silicon nitride layer and silicon dioxide layer.
5. preparation method as claimed in claim 1 is characterized in that, in step 1) and 2) between increase following step: the dry etching substrate silicon, form the silicon bench of certain altitude, form the micron silicon structure.
6. preparation method as claimed in claim 5 is characterized in that, described silicon bench height is 0.1 μ m-5 μ m.
7. preparation method as claimed in claim 1 is characterized in that step 2) adopt the wet-oxygen oxidation method earlier, adopt the dry-oxygen oxidation method again.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364660A (en) * | 2011-10-28 | 2012-02-29 | 北京大学 | Method for manufacturing ultrathin line based on common photoetching and oxidation technology |
| CN102509697A (en) * | 2011-11-01 | 2012-06-20 | 北京大学 | Method for preparing ultra-thin lines |
| CN102509698A (en) * | 2011-11-23 | 2012-06-20 | 北京大学 | Method for preparing superfine wire |
| CN102560565A (en) * | 2012-02-07 | 2012-07-11 | 中国科学院光电技术研究所 | Metal nanowire array based on SOI and electroforming technology and preparation method thereof |
| CN102842495A (en) * | 2012-09-28 | 2012-12-26 | 中国科学院上海微系统与信息技术研究所 | Preparation method for silicon-based nanometer array patterned substrate and silicon-based epitaxial layer |
| CN102842496A (en) * | 2012-09-28 | 2012-12-26 | 中国科学院上海微系统与信息技术研究所 | Preparation method for silicon-based nanometer array patterned substrate and silicon-based epitaxial layer |
| CN103489753A (en) * | 2013-09-27 | 2014-01-01 | 清华大学 | Method for manufacturing large-area small-size core-shell structure silicon nanowire array |
| CN103578917A (en) * | 2012-07-24 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing critical dimension of metal hard mask layer |
| CN108163803A (en) * | 2017-12-26 | 2018-06-15 | 中国计量大学 | A kind of MEMS three-dimensional tunnel structures |
| CN112216600A (en) * | 2020-10-13 | 2021-01-12 | 西安交通大学 | Method for preparing large-area SiC nano-pillar array rapidly, controllably and at low cost |
| CN112462468A (en) * | 2020-10-27 | 2021-03-09 | 中国科学院微电子研究所 | Method for manufacturing photonic crystal by utilizing graph inversion and photonic crystal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1502051A (en) * | 2001-02-02 | 2004-06-02 | 英特尔公司 | Method for providing optical quality silicon surface |
| CN101266919A (en) * | 2008-04-25 | 2008-09-17 | 华东师范大学 | A method for selectively etching silicon nano line |
| CN101638215A (en) * | 2009-08-25 | 2010-02-03 | 华东师范大学 | Manufacture method of micro-nano gap electrode |
| CN101937928A (en) * | 2010-06-28 | 2011-01-05 | 启东吉莱电子有限公司 | Silicon controlled rectifier structure capable of eliminating hazards of punching through lithography pinholes and production method thereof |
-
2011
- 2011-04-11 CN CN2011100894212A patent/CN102205943A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1502051A (en) * | 2001-02-02 | 2004-06-02 | 英特尔公司 | Method for providing optical quality silicon surface |
| CN101266919A (en) * | 2008-04-25 | 2008-09-17 | 华东师范大学 | A method for selectively etching silicon nano line |
| CN101638215A (en) * | 2009-08-25 | 2010-02-03 | 华东师范大学 | Manufacture method of micro-nano gap electrode |
| CN101937928A (en) * | 2010-06-28 | 2011-01-05 | 启东吉莱电子有限公司 | Silicon controlled rectifier structure capable of eliminating hazards of punching through lithography pinholes and production method thereof |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364660A (en) * | 2011-10-28 | 2012-02-29 | 北京大学 | Method for manufacturing ultrathin line based on common photoetching and oxidation technology |
| CN102509697A (en) * | 2011-11-01 | 2012-06-20 | 北京大学 | Method for preparing ultra-thin lines |
| CN102509698A (en) * | 2011-11-23 | 2012-06-20 | 北京大学 | Method for preparing superfine wire |
| CN102560565B (en) * | 2012-02-07 | 2014-09-10 | 中国科学院光电技术研究所 | Metal nanowire array based on SOI and electroforming technology and preparation method thereof |
| CN102560565A (en) * | 2012-02-07 | 2012-07-11 | 中国科学院光电技术研究所 | Metal nanowire array based on SOI and electroforming technology and preparation method thereof |
| CN103578917A (en) * | 2012-07-24 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing critical dimension of metal hard mask layer |
| CN102842495A (en) * | 2012-09-28 | 2012-12-26 | 中国科学院上海微系统与信息技术研究所 | Preparation method for silicon-based nanometer array patterned substrate and silicon-based epitaxial layer |
| CN102842496A (en) * | 2012-09-28 | 2012-12-26 | 中国科学院上海微系统与信息技术研究所 | Preparation method for silicon-based nanometer array patterned substrate and silicon-based epitaxial layer |
| CN103489753A (en) * | 2013-09-27 | 2014-01-01 | 清华大学 | Method for manufacturing large-area small-size core-shell structure silicon nanowire array |
| CN103489753B (en) * | 2013-09-27 | 2016-04-06 | 清华大学 | A kind of preparation method of large-area small-size core-shell structure silicon nanowire array |
| CN108163803A (en) * | 2017-12-26 | 2018-06-15 | 中国计量大学 | A kind of MEMS three-dimensional tunnel structures |
| CN112216600A (en) * | 2020-10-13 | 2021-01-12 | 西安交通大学 | Method for preparing large-area SiC nano-pillar array rapidly, controllably and at low cost |
| CN112462468A (en) * | 2020-10-27 | 2021-03-09 | 中国科学院微电子研究所 | Method for manufacturing photonic crystal by utilizing graph inversion and photonic crystal |
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Application publication date: 20111005 |