CN102194753B - The method of fabricating a semiconductor device used to etch layers of stress - Google Patents

The method of fabricating a semiconductor device used to etch layers of stress Download PDF

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CN102194753B
CN102194753B CN 201010131920 CN201010131920A CN102194753B CN 102194753 B CN102194753 B CN 102194753B CN 201010131920 CN201010131920 CN 201010131920 CN 201010131920 A CN201010131920 A CN 201010131920A CN 102194753 B CN102194753 B CN 102194753B
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region
etching
layer
stress layer
shallow trench
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CN 201010131920
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CN102194753A (en )
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黄敬勇
沈满华
张海洋
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中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Abstract

本发明公开了一种用于制作半导体器件的应力层的刻蚀方法,所述方法包括:提供一个具有NMOS区域、浅沟槽区域和PMOS区域的半导体器件,所述半导体器件的上表面形成有张应力层;以光刻胶图层遮蔽所述NMOS区域上的张应力层,暴露出所述浅沟槽区域和PMOS区域的张应力层;采用各向异性的主刻蚀对所述浅沟槽区域和PMOS区域上的张应力层进行刻蚀,以除去至少部分的张应力层;和采用各向同性的过刻蚀去除所述浅沟槽区域和PMOS区域上残余的张应力层。 The present invention discloses a method of etching a stress layer for fabricating a semiconductor device, the method comprising: providing a semiconductor device is an NMOS region, the shallow trench region and the PMOS region having an upper surface of the semiconductor device is formed layer tensile stress; tensile stress shielding layer photoresist layer on the region of the NMOS, the region and the shallow trench to expose the PMOS region of tensile stress layer; anisotropically etching the shallow primary tensile stress layer on the groove area and the PMOS region is etched to remove at least a portion of a tensile stress layer; and an isotropic etch through the residual area is removed and the PMOS region of the shallow trench tensile stress layer. 使用该方法能够较好地去除残余的不需要的应力层,不会破坏需要应力的NMOS区域的张应力层。 Using this method can remove unwanted residual stress layer, you need not destroy the NMOS region stress tensile stress layer.

Description

用于制作半导体器件的应力层的刻蚀方法 The method of fabricating a semiconductor device used to etch layers of stress

技术领域 FIELD

[0001]本发明涉及半导体制作工艺,特别涉及制作互补型金属氧化物半导体器件的过程中去除应力层的方法。 [0001] The present invention relates to a semiconductor manufacturing process, particularly to a method of stress relief layer is the process of making a complementary metal oxide semiconductor device.

背景技术 Background technique

[0002]随着集成电路的制造向超大规模集成电路发展,其内部的电路密度越来越大,CMOS器件尺寸越来越小,操作速度越来越快,改善电路中CMOS器件的驱动电流变得越来越重要。 [0002] As to the fabrication of integrated circuits VLSI development, its internal circuit density increasing, CMOS devices getting smaller, faster operating speed, the drive current correction circuit CMOS device becomes more and more important. 电路的驱动电流与CMOS器件的栅极长度、栅极电容以及载流子的迀移率等多个参数密切相关,缩短栅极长度、增加栅极电容或提高载流子的迀移率都可以有效地改善CMOS器件的驱动电流。 Gate circuit are closely related with the length of the drive current of a CMOS device, and the gate capacitance of carriers Gan shift rate plurality of parameters, reducing the gate length, increasing the gate capacitance or carriers to improve the rate of shift can Gan effectively improve the driving current of the CMOS device. 其中,在不改变栅极结构的情况下,常利用应力工程向CMOS器件的沟道施加一定的应力,以提高沟道内的载流子的迀移率,改善CMOS器件的驱动电流。 Wherein, without changing the gate structure, often using engineering stress applying a certain stress to the channel of CMOS devices, in order to improve carriers in the channel shift Gan, improving the driving current of the CMOS device. 进入65nm工艺技术节点,传统的提高CMOS器件驱动电流的方法受到了诸多限制,通过应力工程改善CMOS器件的驱动电流已经成为当前的研究热点。 Into the 65nm technology nodes, conventional CMOS devices to improve the current driving method has been many limitations, improved CMOS device by the driving current stress engineering has become a research hotspot.

[0003]所谓应力工程是指在掺杂区上形成可在衬底上产生应力的应力层,该应力层的应力能够增加源极/漏极中掺杂杂质的活性,进而增加的源/漏极载流子的迀移率。 [0003] The so-called strain engineering stress refers to the formation of a stress layer on the substrate over the doped region, the stress can be increased stress layer active impurity source / drain doping, thereby increasing the source / drain Gan electrode carrier shift rate. 现已证实,沿沟道方向的压应力可以提高空穴的迀移率,可用于提高PMOS器件的电学性能;而沿沟道方向的张应力可以提高电子的迀移率,可用于提高匪OS器件的电学性能。 Has been confirmed that the compressive stress of the channel direction can be improved Gan holes drift rate, can be used to improve the electrical performance of the PMOS device; and the tensile stress in the channel direction can be improved Gan electrons drift rate, it can be used to increase the OS bandit the electrical performance of the device. 为了对沟道内的载流子的迀移率有明显的改进,该引入应力的材料层应该形成于接近沟道表面,通常可以利用在CMOS器件上直接形成具有应力的SIN层来实现。 To Gan of carriers in the channel of a shift significant improvement, the introduction of stress in the material layer to be formed on the surface close to the channel, may be utilized generally SIN layer formed directly on the CMOS device having a stress to achieve. 即在沿着源极-漏极的方向上,在NMOS的N型通道表面形成张应力(Tensile Stress)的SIN层,在PMOS的P型通道表面形成压应力(Compressive Stress)的SIN层。 I.e. along source - drain layer SIN direction, tensile stress is formed (Tensile Stress) of SIN N-type channel layer in the NMOS surface, forming a compressive stress (Compressive Stress) in the surface of the P-type channel of a PMOS.

[0004]图1A为现有的具有张应力层的CMOS器件的结构示意图,所述CMOS器件包括PMOS区域1 2和匪OS区域103。 [0004] FIG 1A is a schematic view of a conventional CMOS device layer having a tensile stress, said CMOS device comprising a PMOS region 12 and the region 103 bandit OS. 所述PMOS区域1 2和匪OS区域103通过填充有绝缘物的浅沟槽区域104隔离。 The PMOS region 12 and the region bandit OS 103 by an insulator filled shallow trench isolation region 104. 该PMOS区域102具有源极、漏极和第一栅极101',NM0S区域103具有源极、漏极和第二栅极101。 The PMOS 102 has a source region, a drain, and a first gate electrode 101 ', NM0S region 103 having a source, a drain and a second gate electrode 101. 在该CMOS器件上通过CVD方法形成有一层张应力层110,在实际的工艺中张应力层是一体形成的,因此在低于第一栅极101'和第二栅极101的区域,如浅沟槽区域104沉积有较多的张应力层。 In the CMOS device is formed by a CVD method with a layer of a tensile stress layer 110, in an actual process, the tensile stress layer are integrally formed, and therefore below the '101 and the second gate region of the first gate electrode 101, such as light trench region 104 is deposited more tensile stress layer.

[0005]现有技术中,匪OS区域103采用张应力层的张应力提高源-漏极的电子迀移率,而PMOS区域102通过压应力层的压应力提高源-漏极的空穴迀移率,由此需要将NMOS区域103上方的张应力层110保留,去除PMOS区域102和浅沟槽区域104上的张应力层110。 [0005] In the prior art, bandit OS area 103 using the tensile stress of the tensile stress layer to improve the source - drain Gan electron drift rate, and the PMOS region 102 improved by the compressive stress of the compressive stress layer, the source - drain hole Gan drift rate, thereby requiring the NMOS region 103 over the layer 110 to retain the tensile stress, tensile stress layer 110 is removed in the PMOS region 102 and shallow trench area 104. 如图1B所示,在NMOS区域103的张应力层110的上方涂覆光刻胶,利用一掩膜进行曝光,经显影等工艺得到第一光刻胶图层111,该第一光刻胶图层111覆盖匪OS区域103,暴露出PMOS区域102和浅沟槽区域104;接着,如图1C所示,利用第一光刻胶图层111为掩膜刻蚀掉PMOS区域102和浅沟槽区域104上的张应力层110;在实际的工艺中,采用干法刻蚀或湿法腐蚀或两种方法的组合来去除PMOS区域和浅沟槽上方的张应力层。 1B, photoresist is applied above the tensile stress layer 110 of NMOS region 103, using an exposure mask, a first resist layer 111 obtained by the developing process and the like, the first photoresist bandit OS layer 111 covering area 103, 102 to expose the PMOS region 104 and a shallow trench region; Next, as shown in FIG. 1C, by using the first photoresist layer 102 and PMOS region 111 out of the shallow trench etch mask tensile stress layer 110 on the groove area 104; in the actual process, using a combination of dry etching or wet etching, or the two methods to remove the PMOS region and a tensile stress layer above a shallow trench. 然后,如图1D所示,去除第一光刻胶图层111,以得到具有张应力层110的NMOS区域103。 Then, as shown in FIG. 1D, the first photoresist layer 111 is removed to obtain the NMOS region 103 has a tensile stress layer 110.

[0006] 然而,上述制备具有应力层110的匪OS区域103的过程中存在两个方面的问题,一是,该SIN材料的张应力层110通常是由化学气相沉积方法形成,在其沉积形成过程中是一体形成在CMOS器件的表面,通常会在PMOS区域102和匪OS区域103之间有较多的张应力层110沉积,即在浅沟槽区域104上沉积较多的张应力层110; 二是,当需要保留NMOS区域103的张应力层110时,该浅沟槽区域104和PMOS区域102上的张应力层110需要全部去除,而由于PMOS区域102和NMOS区域103的间距非常小,导致浅沟槽区域104上的张应力层105有较多的残余(如图1D中所示的虚线),若进一步去除该残余在浅沟槽区域104上的张应力层105,可能会破坏NMOS区域103上的张应力层110。 [0006] However, the above prepared having two problems exist during the OS area 103 bandit stress layer 110, first, the tensile stress SIN material layer 110 is usually formed by a chemical vapor deposition method, the deposition is formed thereon process is integrally formed on the surface of CMOS devices, there is usually more tensile stress layer 110 is deposited between the PMOS region 103 in the region 102 and the gang OS, i.e., the shallow trench region 104 in greater tensile stress layer 110 is deposited ; Second, when the need to keep the NMOS region 103 of the layer 110 is a tensile stress, tensile stress layer 110 needs the shallow trench region 104 and PMOS region 102 completely removed, and because the spacing NMOS region 102 and PMOS region 103 is very small , resulting in shallow trench region 104 has a residual tensile stress layer 105 more (shown in phantom in FIG. 1D), if further removal of the residual tensile stress layer 104 over the shallow trench region 105 may break tensile stress layer 110 on the NMOS region 103.

[0007]由此,上述方法并不能够有效地去除PMOS区域102和浅沟槽区域104上的张应力层110,导致现有的应力层对CMOS器件电性能的提高受到限制。 [0007] Thus, the method described above is not possible to effectively remove the tensile stress layer 110 on the PMOS region 102 and a shallow trench region 104, resulting in the existing stress layer is limited to improve the electrical performance of the CMOS device. 另外,还可能降低制备具有应力结构的半导体器件的良品率。 In addition, the yield may decrease prepared a semiconductor device having a stress structure.

[0008]在制备具有应力层的CMOS器件过程中,如何去除残余的不需要的应力层成为当前需要解决的技术问题。 [0008] in the manufacture of a CMOS device having a stress layer process, how to remove the residual stress layer becomes unnecessary current technical problem to be solved.

发明内容 SUMMARY

[0009]在发明内容部分中引入了一系列简化形式的概念,这将在具体实施方式部分中进一步详细说明。 [0009] introduced the concept of a series of simplified form in the Summary section, which will be described in further detail in the Detailed Description. 本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征,更不意味着试图确定所要求保护的技术方案的保护范围。 This summary of the present invention is not intended to identify key features or essential features of the claimed technical solutions, nor is it intended to determine the scope of the claimed technical solution.

[0010]为了解决上述问题,本发明提出了一种用于制作互补型金属氧化物半导体器件的应力层的刻蚀方法,所述方法包括: [0010] In order to solve the above problems, the present invention proposes a method of etching a layer made stress complementary metal oxide semiconductor device, said method comprising:

[0011]提供一个具有匪OS区域、浅沟槽区域和PMOS区域的半导体器件,所述半导体器件的上表面形成有张应力层; [0011] a semiconductor device bandit OS region, shallow trench region and the PMOS region having an upper surface of the semiconductor device is formed with a tensile stress layer;

[0012]以光刻胶图层遮蔽所述NMOS区域上的张应力层,暴露出所述浅沟槽区域和PMOS区域的张应力层; [0012] In a photoresist masking layer on said NMOS region of tensile stress layer, exposing the shallow trench region and the PMOS region of tensile stress layer;

[0013]采用各向异性的主刻蚀对所述浅沟槽区域和PMOS区域上的张应力层进行刻蚀,以除去所述浅沟槽区域和PMOS区域至少部分的张应力层;和 [0013] The anisotropic etch etching the primary layer on the tensile stress of the shallow trench region and the PMOS region, to remove the shallow trench region and a PMOS region of a tensile stress layer at least partially; and

[0014]采用各向同性的过刻蚀去除所述浅沟槽区域和PMOS区域上残余的张应力层。 [0014] The isotropic etching through the removal of residual shallow trench region and the PMOS region of tensile stress layer.

[0015]进一步地,所述方法还包括:在所述主刻蚀之前,对所述浅沟槽区域和PMOS区域的张应力层进行预刻蚀。 [0015] Preferably, the method further comprising: prior to the main etch, the layer of tensile stress shallow trench region and the PMOS region is pre-etched. 所述预刻蚀为穿透刻蚀。 The pre-etching to penetrate the etching.

[0016]进一步地,所述主刻蚀的刻蚀方向是垂直指向所述张应力层的表面。 [0016] Further, the etching direction of the main etch is directed perpendicular to the surface tensile stress layer.

[0017]进一步地,所述主刻蚀和过刻蚀均为干法刻蚀。 [0017] Further, the main etching and over etching are dry etching.

[0018] 进一步地,所述主刻蚀中所使用的气体为包含N2O与Cl2或包含N2O与HBr的混合气体。 [0018] Further, the main etching gas used was a mixed gas of Cl2 and HBr or comprises N2O containing N2O.

[0019]进一步地,所述主刻蚀中所使用的气体为包含CHF3的刻蚀气体。 [0019] Further, the main etching gas is used as etching gas containing CHF3.

[0020] 进一步地,所述主刻蚀中所使用的电源功率为300-1000W。 [0020] Further, the power supply of the main etching is used 300-1000W.

[0021 ] 进一步地,所述主刻蚀选择的压力为1-1OOmTorr。 [0021] Further, the primary pressure of the etching selectivity 1-1OOmTorr.

[0022]进一步地,所述过刻蚀中所使用的气体为包含O2与He或包含O2与HBr的混合气体。 [0022] Further, the over etching gas containing O2 is used with a He or a mixed gas of HBr and O2.

[0023]进一步地,所述过刻蚀中所使用的气体为包含CHF3和O2的刻蚀气体。 [0023] Further, the over etching gas used in etching gas comprising CHF3 and O2.

[0024] 进一步地,所述过刻蚀中所使用的电源功率为300-550W。 [0024] Further, the over-etching is used a power of 300-550W.

[0025]进一步地,所述穿透刻蚀中所使用的气体为CF4、C2F6和Cl2中的一种。 [0025] Further, the penetrating etching gas is used as a CF4, C2F6 and Cl2 gas.

[0026]进一步地,所述穿透刻蚀中所使用的电源功率为50-150W。 [0026] Furthermore, the penetrating power supply is used in etching 50-150W.

[0027]根据本发明的另一方面,本发明提出了一种用于制作互补型金属氧化物半导体器件的应力层的刻蚀方法,所述方法包括: [0027] According to another aspect of the present invention, the present invention proposes a method of etching a layer made stress complementary metal oxide semiconductor device, said method comprising:

[0028]提供一个具有匪OS区域、浅沟槽区域和PMOS区域的半导体器件,所述半导体器件的上表面形成有压应力层; [0028] a semiconductor device bandit OS region, shallow trench region and the PMOS region having an upper surface of the semiconductor device is formed with a compressive stress layer;

[0029]以光刻胶图层遮蔽所述PMOS区域上的压应力层,暴露出所述浅沟槽区域和匪OS区域的压应力层; [0029] In the masking photoresist layer compressive stress layer on the PMOS region, exposing the region of the compressive stress layer and the gang OS shallow trench region;

[0030]采用各向异性的主刻蚀对所述浅沟槽区域和NMOS区域上的压应力层进行刻蚀,以除去所述浅沟槽区域和NMOS区域至少部分的压应力层;和 [0030] anisotropically etching the main etching compressive stress layer on said NMOS region and a shallow trench region, said shallow trench region to remove the NMOS region and at least part of the compressive stress layer; and

[0031]采用各向同性的过刻蚀去除所述浅沟槽区域和NMOS区域上的残余的压应力层。 [0031] The isotropic etching through removal of the residual compressive stress layer on the NMOS region and a shallow trench region.

[0032]进一步地,所述方法还包括:在所述主刻蚀之前,对所述浅沟槽区域和NMOS区域的压应力层进行穿透刻蚀。 [0032] Preferably, the method further comprising: prior to the main etching, a compressive stress layer on the NMOS region and the shallow trench region is etched to penetrate.

[0033]在制备具有应力层的CMOS器件的过程中,使用本发明的方法能够较好地去除残余的不需要的应力层,不会破坏需要应力的PM0S/NM0S区域的应力层,进而能够有效提高CMOS器件的电学性能,以及提尚所制备的CMOS器件的良品率。 [0033] In preparing the CMOS device having a stress layer, the method of the present invention are better able to remove an unnecessary residual stress layer, need not destroy the stress layer stress PM0S / NM0S region, and thus can be effectively improve the electrical performance of a CMOS device, and provide CMOS devices is still prepared to yield.

附图说明 BRIEF DESCRIPTION

[0034]本发明的下列附图在此作为本发明的一部分用于理解本发明。 [0034] The following figures of the present invention is used herein as part of the present invention to understand the invention. 附图中示出了本发明的实施例及其描述,用来解释本发明的原理。 In the embodiment shown and described embodiments of the present invention are shown, serve to explain the principles of the invention. 在附图中, In the drawings,

[0035]图1A为现有的具有张应力层的CMOS器件的示意图; [0035] FIG 1A is a schematic view of a conventional CMOS device having a tensile stress layer;

[0036]图1B至图1D为去除图1A中的PMOS区域和浅沟槽区域上的张应力层时所涉及的结构的示意图; [0036] FIGS. 1B to 1D is a PMOS region is removed on the structure of FIG. 1A shallow trench area a tensile stress and a layer involved a schematic view;

[0037]图2A至图2F是根据本发明方法的一个实施例去除残余的张应力层的刻蚀过程示意图; [0037] FIGS. 2A to 2F is a method according to an embodiment of the present invention is removed during etching schematic residual tensile stress layer;

[0038]图3A是沉积有张应力层的CMOS器件的SEM图; [0038] FIG 3A is a CMOS device with a tensile stress layer is a SEM view of a deposition;

[0039]图3B是对图3A中PMOS区域和浅沟槽区域上的张应力层执行主刻蚀步骤后的CMOS器件的SEM图; [0039] FIG 3B is a SEM image of the CMOS device after the tensile stress layer executes the main etching step in the PMOS region 3A and the shallow trench region;

[0040]图3C是对图3B中PMOS区域和浅沟槽区域上的张应力层执行过刻蚀步骤后的CMOS器件的SEM图; [0040] FIG 3C is a SEM view of a CMOS device layer is performed after the step of etching the tensile stress on the PMOS region 3B and shallow trench region;

[0041 ]图4A是其NMOS区域上的张应力层被遮蔽后的CMOS器件的俯视图(SEM); [0041] FIG. 4A is a plan view of the CMOS device after which the tensile stress layer on the NMOS region is shielded (SEM);

[0042]图4B是现有技术中去除PMOS区域和浅沟槽区域上的张应力层后的CMOS器件的俯视图(SEM); [0042] FIG. 4B is a plan view of the CMOS device after the tensile stress layer on the PMOS region and the shallow trench area (SEM) is removed prior art;

[0043]图4C是本发明的一个实施例中去除PMOS区域和浅沟槽区域上的张应力层后的CMOS器件的俯视图(SEM); [0043] FIG 4C is a plan view of the embodiment of the present invention (SEM) after the tensile stress layer on the PMOS region and the shallow trench region is removed CMOS devices embodiment;

[0044]图5是本发明的一个实施例中去除PMOS区域和浅沟槽区域上的应力层的流程图。 [0044] FIG. 5 is a flowchart of a embodiment of the present invention, the stress layer on the PMOS region and the shallow trench region is removed embodiment.

具体实施方式 detailed description

[0045]在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。 [0045] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. 然而,对于本领域技术人员来说显而易见的是,本发明可以无需一个或多个这些细节而得以实施。 However, the skilled person it will be apparent that the present invention may be practiced without one or more of these details are implemented. 在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。 In other examples, in order to avoid confusion with the present invention, known in the art for some of the technical features are not described.

[0046]为了彻底了解本发明,将在下列的描述中提出详细的步骤,以便说明本发明是如何通过改进现有的刻蚀方法来去除残余在CMOS器件上的不需要的应力层。 [0046] For a thorough understanding of the present invention will be set forth in the following detailed description of the steps in order to explain how the present invention is to remove the residue on the CMOS device layer unnecessary stress by improving a conventional etching method. 本发明的实施并不限定于半导体领域的技术人员所熟习的特殊细节。 Embodiment of the present invention is not limited to the specific details of the semiconductor art are familiar with the art. 本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。 As described in detail preferred embodiments of the present invention, however, in addition to the detailed description, the present invention also may have other embodiments.

[0047] 参照图2A所示,图2A为本实施例中使用的CMOS器件的结构示意图。 [0047] Referring to FIG. FIG. 2A, a schematic structural diagram of CMOS devices used in the embodiment of FIG. 2A. 所述CMOS器件包括PMOS区域202和NMOS区域203,以及填充有绝缘物的浅沟槽区域204,该浅沟槽区域204将PMOS区域202和匪OS区域203隔离。 The CMOS device comprises an NMOS region 202 and PMOS region 203, and a shallow trench region is filled with an insulating material 204, 204 and PMOS region 202 bandit OS area 203 of the shallow trench isolation region. 该PMOS区域202具有源极、漏极和第一栅极201',NM0S区域203具有源极、漏极和第二栅极201。 The PMOS 202 has a source region, a drain, and a first gate electrode 201 ', NM0S region 203 having a source, a drain and a second gate electrode 201.

[0048]如图2B所示,在CMOS器件的上方形成一层张应力层210,该张应力层210是通过化学气相沉积方式进行沉积的。 [0048] As shown in FIG. 2B, the top layer of the CMOS device layer 210 is formed tensile stress, the tensile stress layer 210 is deposited by a chemical vapor deposition method. 应力层210的厚度在500埃至5000埃之间。 Between the thickness of the stress layer 210 is 500 Angstroms to 5000 Angstroms. 其应力层210具有的应力在-1OOMPa至-500MPa之间。 Stress layer having a stress between 210 to -1OOMPa -500MPa. 其应力层210的材料可以为氮化硅或氮氧化硅。 Stress material layer 210 may be silicon nitride or silicon oxynitride.

[0049]接着,如图2C所示,在NMOS区域203的张应力层210的上方涂覆光刻胶,利用一掩膜进行曝光,经显影等工艺得到第一光刻胶图层211,该第一光刻胶图层211覆盖NMOS区域203,暴露出PMOS区域202和浅沟槽区域204; [0049] Next, as shown in FIG. 2C, the tensile stress in NMOS region 203 of the photoresist 210 coated over the layer, the use of an exposure mask, a first resist layer 211 obtained by the developing process and the like, the The first photoresist layer 211 covers the NMOS region 203, 202 to expose the PMOS region 204 and a shallow trench region;

[0050]然后,利用第一光刻胶图层211为掩膜采用如下方式去除PMOS区域202和浅沟槽区域204上的张应力层210。 [0050] Then, the first photoresist mask layer 211 is removed in the following way tensile stress PMOS region 202 and shallow trench area 204 on the layer 210.

[0051 ] 在一个优选的实施方式中,在进行主刻蚀和过刻蚀之前,先采用预刻蚀(例如BT(breakthrough,穿透)刻蚀)去除PMOS区域202和浅沟槽区域204上的张应力层210上的氧化层或杂质(图中未示出),本实施方式中,该穿透刻蚀即BT刻蚀使用的气体为CF4、C2F6、C12中的一种,优选使用CF4气体;刻蚀的速率依据张应力层210的膜厚进行设定,其经验值是500埃/分,相对应的刻蚀时间在5s至15s之间,电源功率为50W至150W。 Before [0051] In a preferred embodiment, the main etching and over etching is performed, using the first pre-etching (e.g. BT (breakthrough, penetration) etching) is removed and the shallow trench area 204 PMOS region 202 tensile stress oxide layer or impurities (not shown) on the 210, the present embodiment, i.e., the penetrating etching gas used for etching BT CF4, C2F6, one kind of C12, preferably using CF4 gas; etching rates were based on a film thickness of the tensile stress layer 210 is set, which is an empirical value 500 Å / min, corresponding to the etching time between 5s to 15s, a power of 50W to 150W. 需要指出的是,对于本发明要解决的技术问题来说,所述预刻蚀并不是必需的,本领域技术人员可根据实际情况选择执行预刻蚀,以达到所需要的效果。 It is noted that, for the technical problem is to be solved by the present invention, the pre-etching is not required, the skilled person may choose to perform a pre-etched according to the actual situation, to achieve the desired effect.

[0052]其次,在可选的预刻蚀之后,如图2D所示,进行各向异性的主刻蚀步骤,进一步刻蚀PMOS区域202和浅沟槽区域204上的张应力层210,该主刻蚀采用从上到下(从半导体器件的上方向衬底的方向即如图2D中示出的箭头方向,垂直指向所述张应力层210的表面)的轰击式干法刻蚀方式。 [0052] Next, after the optional pre-etching, shown in Figure 2D, the main anisotropically etching step, a tensile stress layer 210 is further etched in the PMOS region 202 and shallow trench area 204, the etching using the main top to bottom (direction of the substrate in the direction from the direction of an arrow, i.e., the semiconductor device shown in FIG. 2D, directed perpendicular to the surface tensile stress layer 210) bombardment dry etching method. 该主刻蚀可以有效地去除PMOS区域202和浅沟槽区域204上的张应力层210的主要部分。 The main etch can effectively remove the major portion of the tensile stress layer 210 on the PMOS region 202 and shallow trench area 204. 其中,主刻蚀使用的气体可以是例如由N2O与Cl2、或由N2O与HBr构成的混合气体等常用的各向异性的主刻蚀气体,气体总流量可以是80-310SCCm,其中,Cl2为10-50sccm,HBr为50-200sccm;但优选使用包含CHF3的刻蚀气体,因为该刻蚀气体可以更彻底地去除张应力层210的主要部分。 Wherein, the main etching gas may be used for example with N2O Cl2, or by a conventional anisotropic etching of a main gas and N2O mixed gas composed of HBr and the total gas flow may be 80-310SCCm, wherein, Cl2 is 10-50sccm, HBr is 50-200 seem; but preferably the etching gas containing CHF3, since the etching gas can be more completely removed the main part of the tensile stress layer 210. 主刻蚀的速率依据张应力层210的膜厚进行设定,其经验值是1000埃/分,相对应的刻蚀时间在1s至30s之间。 Etching rate of the main set according to the film thickness of the tensile stress layer 210 having an empirical value is 1000 Å / min, corresponding to the etching time between 1s to 30s. 另外,该轰击式主刻蚀采用的第一偏置电压可以为50V至600V之间,压力可以是1mTorr至10mTorr,电源功率可以是300W至1000W; Further, the bias voltage of the first type master bombardment etch may be used between 50V to 600V, pressure may be 1mTorr to 10 mTorr, the power supply may be 300W to 1000W;

[0053]接着,再对上述主刻蚀后的PMOS区域202和浅沟槽区域204进行各向同性的过刻蚀。 [0053] Next, another pair of PMOS region after the main etching region 202 and the shallow trenches 204 isotropic over-etching. 如图2E所示,该过刻蚀主要是针对浅沟槽区域204上残余的张应力层205进行刻蚀。 2E, mainly for the over-etching the shallow trench area residual stress layer 204 is etched 205. 该过刻蚀采用从各向同性的干法刻蚀方式,如图2E中示出的箭头。 The use of over-etching from the isotropic dry etching embodiment, arrows shown in FIG. 2E. 其中,过刻蚀使用的气体可以是由O2与He、或由O2与HBr构成的混合气体等常用的各向同性的过刻蚀气体,气体总流量可以是155-530sccm,其中,例如,HBr为50-250sccm,He为100-250sccm,02为5-30sccm;优选使用包含CHF3和O2的刻蚀气体,因为该刻蚀气体可以更彻底地去除张应力层205。 Wherein, through the gas etching may be used by O2 and He, or a mixed gas composed of O2 and HBr conventional isotropic over etching gas, the total gas flow rate may be 155-530sccm, wherein, e.g., HBr is 50-250sccm, He is 100-250sccm, 02 is 5-30sccm; preferably using an etching gas comprising CHF3 and O2, because the etching gas can be more completely removed the tensile stress layer 205. 该过刻蚀的速率依据张应力层205的膜厚进行设定,其经验值是1300埃/分,相对应的刻蚀时间可以在3s至15s之间,电源功率可以为300W至550W之间。 The over-etching rate is set based on the film thickness of the tensile stress layer 205 having an empirical value is 1300 Å / min, corresponding to the etching time may be between 3s to 15s, source power may be between 300W to 550W .

[0054]最后,采用灰化的方法去除匪OS区域203的第一光刻胶图层211,得到如图2F所示的具有张应力层210的NMOS区域203的器件,该器件的PMOS区域202和浅沟槽区域204上没有残余的张应力层210。 [0054] Finally, the ashing method for removing a first region of the photoresist layer bandit OS 203 211, NMOS region 210 to obtain the device having tensile stress layer 203 shown in Figure 2F, the PMOS region of the device 202 and a shallow trench region 204 no residual tensile stress layer 210.

[0055]相应地,若在CMOS器件的上方预先沉积的是压应力层,也可以采用上述刻蚀去除应力层的步骤去除WOS区域和浅沟槽区域上的压应力层,进而保留PMOS区域的压应力层,即以光刻胶图层遮蔽所述PMOS区域上的压应力层,暴露出所述浅沟槽区域和NMOS区域的压应力层;采用各向异性的主刻蚀对所述浅沟槽区域和NMOS区域上的压应力层进行刻蚀,以除去至少部分的压应力层;和采用各向同性的过刻蚀去除所述浅沟槽区域和NMOS区域上的残余的压应力层。 [0055] Accordingly, if the previously deposited over the CMOS device is a compressive stress layer may be the above-mentioned etching step of removing the stress layer removal region and the WOS compressive stress layer on the shallow trench region, and thus retain the PMOS region the compressive stress layer, i.e. the photoresist masking layer a compressive stress layer on the PMOS region, the compressive stress layer is exposed shallow trench region and the NMOS region; anisotropically etching the shallow primary trench region and a compressive stress layer on the NMOS region is etched to remove at least part of the compressive stress layer; and isotropic etching through removal of the residual compressive stress layer on the NMOS region and a shallow trench region . 优选地,在所述主刻蚀之前,可以对所述浅沟槽区域和NMOS区域的压应力层进行预刻蚀(如穿透(BT)刻蚀)。 Preferably, prior to the main etch, may be pre-etched (e.g., penetration (BT) etching) a compressive stress layer on the shallow trench region and the NMOS region.

[0056]当然,还可以进一步在具有张应力层/压应力层的器件上方再沉积压应力层/张应力层,通过上述刻蚀方法去除匪OS区域和浅沟槽区域上的压应力层,或PMOS区域和浅沟槽区域上的张应力层,获取具有所需要的应力层的CMOS器件,即,该CMOS器件的NMOS区域具有张应力层、PMOS区域具有压应力层,浅沟槽区域无应力层。 [0056] Of course, may further device having the above tensile stress layer / a compressive stress layer is deposited and then the compressive stress layer / tensile stress layer, the compressive stress layer is removed bandit OS region and a shallow trench region by the above-described etching method, or a tensile stress layer on the PMOS region and the shallow trench region, the CMOS device having obtain desired stress layer, i.e., the NMOS region of the CMOS device layer having a tensile stress, compressive stress layer having a PMOS region, the shallow trench region without stress layer.

[0057] 参照图3A至图3C所示,图3A至图3C示出了本发明的另一实施例中去除张应力层时所涉及的CMOS器件的SEM图。 [0057] Referring to FIGS. 3A to Fig. 3C, FIGS. 3A to 3C illustrate another embodiment of the invention a SEM view of a CMOS device when a tensile stress layer is removed to an embodiment example.

[0058]图3A为一沉积有张应力层301的CMOS器件的SEM图,该CMOS器件包括PMOS区域、浅沟槽区域和匪OS区域,从图3A中,可以很明显的看出浅沟槽区域上沉积有较多的张应力层(图中箭头所示)。 [0058] Figure 3A is a SEM image of deposited tensile stress CMOS device layer 301, the CMOS device comprising a PMOS region, and a shallow trench region bandit OS region in FIG. 3A, can clearly be seen shallow trench depositing a tensile stress region more layer (arrow).

[0059]图3B为对上述PMOS区域和浅沟槽区域上的张应力层进行从上而下的轰击式的各向异性主刻蚀步骤后的CMOS器件的SEM图,该主刻蚀的气体是包含CHF3的刻蚀气体,气体总流量是300sccm,刻蚀速率为800埃/分,相对应的刻蚀时间在20s,第一偏置电压为500V,压力为90mTorr,电源功率为600W。 [0059] Figure 3B after the bombardment of formula anisotropic etching step for the main layer of tensile stress on the PMOS region and a shallow trench region from the upper-down SEM image of a CMOS device, the main etching gas comprising CHF3 etching gas, the total gas flow rate was 300 sccm, the etching rate was 800 Å / min, the etching time corresponding to the 20s, the first bias voltage of 500V, a pressure of 90 mTorr, a power of 600W. 由此,从图中可以看出PMOS区域上的张应力层已经基本被去除,而在浅沟槽区域上还残余有较多的张应力层302(如图3B中圈出的部分)。 Thus, it can be seen from the figure tensile stress layer on the PMOS region has been substantially removed, and in the shallow trench region further has a residue (circled in Figure 3B portion) 302 more tensile stress layer.

[0060] 进一步地,对上述图3B所示的器件再进行各向同性的过刻蚀,该过刻蚀选用的为包含CHF3和O2的刻蚀气体,速率1500埃/分,时间为3s,电源功率为350W,进而获取如图3C所示的器件中PMOS区域和浅沟槽区域的SEM图,从图3C中可以看出,在PMOS区域和浅沟槽区域上没有任何张应力层的残余。 [0060] Further, the device shown in FIG. 3B further isotropic over-etching, the etching over the selected etching gas comprising CHF3 and O2, the rate of 1500 Å / min, time of 3s, a power of 350W, and then obtain the device as shown in FIG 3C FIG SEM PMOS region and the shallow trench region, it can be seen from Figure 3C, without any residual tensile stress layer in the PMOS region and a shallow trench region .

[0061]参照图4A至图4C所示的采用现有技术的方法和本发明的方法中的上述实施例获取的去除了PMOS区域上的张应力层后的器件的SEM俯视图。 [0061] Referring to FIG embodiment employs the above-described embodiment shown in the prior art methods and methods according to the present invention. 4A to 4C to obtain a SEM top view of the device after the tensile stress layer on the PMOS region other. 图4A为其匪OS区域上的张应力层被遮蔽后的器件的SEM俯视图,图4B是以现有方法刻蚀PMOS区域和浅沟槽区域上的张应力层之后的器件的SEM俯视图;图4C是本发明的一个实施例中刻蚀PMOS区域和浅沟槽区域上的张应力层之后的器件的SEM俯视图。 FIG tensile stress layer on their bandit OS region 4A SEM plan view of the device after being masked, FIG. 4B is a top plan SEM view of the device after the tensile stress layer on the PMOS region and the conventional method of etching a shallow trench region; FIG. 4C is a top plan view of the device of the SEM after etching the tensile stress layers in the PMOS region and a shallow trench region embodiment of the present invention.

[0062]在没有刻蚀PMOS区域和浅沟槽区域上的张应力层之前,图4A所示的需要刻蚀的PMOS区域和浅沟槽区域的张应力层的宽度为250nm,如图4A中所示的双应力线之间的距离。 [0062] In the absence of a tensile stress layer on the etch shallow trench area and the PMOS region, the width of the tensile stress layer, the PMOS region and the shallow trench region where etching is required is 250 nm as shown in FIG. 4A, 4A in FIG. the distance between the dual-stress lines shown. 而在现有方法中,由于在去除PMOS区域上的张应力层后,还要去除浅沟槽区域上的张应力层,会导致NMOS区域上的张应力层受到破坏。 In the conventional method, since after removal of tensile stress layer on the PMOS region, but also removing the tensile stress layer on the shallow trench region, will cause a tensile stress on the NMOS region layer is damaged. 在如图4B所示的器件中,由401所指示的匪OS区域上的张应力层被部分刻蚀,导致最后测量的刻蚀宽度为399.0nm,远远大于原设计的250nm的宽度,其前后偏差在150nm左右。 In the device shown in FIG. 4B, the tensile stress on the layer 401 is indicated by area OS bandit partially etched, resulting in etching width of the last measurement is 399.0nm, 250nm is much greater than the width of the original design, which before and after the deviation is about 150nm.

[0063]当采用本发明的一个实施例的方法刻蚀PMOS区域和浅沟槽区域上的张应力层时,得到如图4C所示的俯视图,该图中显示匪OS区域的张应力层几乎没有受到破坏,其测量的刻蚀宽度为301nm,前后偏差在50nm左右,该图片的刻蚀宽度非常接近图4A中设计的宽度,符合了实际的工艺需求,提高所制备的具有应力层的CMOS器件的良品率。 [0063] When the tensile stress layer using an etching method of the present invention is a PMOS region and embodiments shallow trench area, resulting in a plan view as shown FIG. 4C, the display region of the OS bandit FIG tensile stress layer almost not damaged, etching width of 301nm is measured, before and after the deviation is about 50 nm, the width of the etching is very close to the width of the image in FIG. 4A designed to meet the actual needs of the process, to improve the stress layer having a CMOS prepared device yield.

[0064]参照图5所示,图5是本发明的方法去除PMOS区域和浅沟槽区域上的张应力层的流程图。 [0064] Referring to FIG. 5, FIG. 5 is a flowchart of a tensile stress layer on the PMOS region and a shallow trench region removing method of the present invention. 具体步骤包括: These steps include:

[0065] 步骤501:提供一个具有匪OS区域、浅沟槽区域和PMOS区域的半导体器件(CMOS器件),所述半导体器件的上表面形成有张应力层; [0065] Step 501: bandit OS area having a shallow trench region and the PMOS region of the semiconductor device (CMOS devices), the upper surface of the semiconductor device is formed with a tensile stress layer;

[0066]步骤502:采用光刻胶图层将匪OS区域上的张应力层遮蔽,暴露出浅沟槽区域和PMOS区域的张应力层; [0066] Step 502: the use of a photoresist layer on the tensile stress region bandit OS shielding layer, exposing the shallow trench region and the PMOS region of tensile stress layer;

[0067]步骤503:采用各向异性的主刻蚀方式对浅沟槽区域和PMOS区域上的张应力层进行刻蚀,以除去至少部分的浅沟槽区域和PMOS区域上的张应力层;该主刻蚀可以为干法刻蚀,其方向是从半导体器件的上方向衬底方向刻蚀; [0067] Step 503: an anisotropic etching manner the main tensile stress layer on the shallow trench region and the PMOS region is etched to remove the tensile stress layer on at least part of the shallow trench region and the PMOS region; the main etch can be a dry etching process, the direction is a direction from the substrate is etched in the direction of the semiconductor device;

[0068]步骤504:采用各向同性的过刻蚀方式去除浅沟槽区域和PMOS区域上残余的张应力层,该过刻蚀可以为干法刻蚀,其方向是从各个方向进行的; [0068] Step 504: isotropic manner overetching to remove residual shallow trench region and the PMOS region of tensile stress layer, the over-etching may be dry etching, the direction is performed from various directions;

[0069]优选地,在进行主刻蚀之前,还可以进行预刻蚀如BT刻蚀,用于去除张应力层上方的其他杂质,如氧化层等。 [0069] Preferably, prior to the main etch, further etching such as BT may be pre-etched for removing the tensile stress of the upper layers of other impurities, such as oxide layer.

[0070]根据如上所述的实施例的方法去除CMOS器件不需要的应力层,制备具有应力层的半导体器件可应用于多种集成电路(IC)中。 [0070] removing unnecessary stress CMOS device layer according to the method of Example described above, a semiconductor device having a stress layer may be applied in a variety of integrated circuit (IC). 根据本发明的IC例如是存储器电路,如随机存取存储器(RAM)、动态RAM (DRAM)、同步DRAM (SDRAM)、静态RAM (SRAM)、或只读存储器(ROM)等等。 The IC according to the present invention, for example, memory circuits such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or read only memory (ROM) and the like. 根据本发明的IC还可以是逻辑器件,如可编程逻辑阵列(PLA)、专用集成电路(ASIC)、合并式DRAM逻辑集成电路(掩埋式DRAM)或任意其他电路器件。 The IC according to the present invention may also be logic devices such as programmable logic arrays (PLA), application specific integrated circuit (ASIC), a merged DRAM-logic IC (embedded DRAM formula) or any other circuit devices. 根据本发明的IC芯片可用于例如用户电子产品,如个人计算机、便携式计算机、游戏机、蜂窝式电话、个人数字助理、摄像机、数码相机、手机等各种电子产品中,尤其是射频产品中。 The IC chip according to the present invention can be used, for example, consumer electronic products, such as personal computers, portable computers, game machines, cellular phones, personal digital assistants, cameras, digital cameras, mobile phones and other electronic products, especially in RF products.

[0071] 本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。 [0071] The present invention has been described by the above embodiments, it should be understood that the above examples are only for purposes of illustration and description, and are not intended to limit the invention within the scope of the described embodiments. 此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。 Moreover, those skilled in the art will be appreciated that the present invention is not limited to the above embodiment, in accordance with the teachings of the present invention may be made more of the variations and modifications, all such variations and modifications fall within the invention as claimed within the range. 本发明的保护范围由附属的权利要求书及其等效范围所界定。 The scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (15)

  1. 1.一种用于制作互补型金属氧化物半导体器件的应力层的刻蚀方法,其特征在于,所述方法包括: 提供一个具有匪OS区域、浅沟槽区域和PMOS区域的半导体器件,所述半导体器件的上表面形成有张应力层; 以光刻胶图层遮蔽所述NMOS区域上的张应力层,暴露出所述浅沟槽区域和PMOS区域的张应力层,所述光刻胶图层为经曝光、显影得到的光刻胶图层; 采用各向异性的主刻蚀对所述浅沟槽区域和PMOS区域上的张应力层进行刻蚀,以除去所述浅沟槽区域和PMOS区域至少部分的张应力层;和采用各向同性的过刻蚀去除所述浅沟槽区域和PMOS区域上残余的张应力层,其中,所述主刻蚀和过刻蚀均为干法刻蚀。 An etching method stress layer produced a complementary metal oxide semiconductor device, characterized in that, said method comprising: providing a semiconductor device bandit OS region, shallow trench region and the PMOS region having the the upper surface of said semiconductor device is formed with a tensile stress layer; tensile stress shielding layer photoresist layer on the region of the NMOS, the region and the shallow trench to expose the PMOS region of tensile stress layer, the photoresist layer is exposed and developed to give photoresist layer; anisotropically etched principal tensile stress layer on the PMOS region and the shallow trench region is etched to remove the shallow trench region PMOS region and at least part of the tensile stress layer; and the isotropic etch through the shallow trench region is removed and the PMOS region of residual tensile stress layer, wherein the primary over-etching and dry etching are etching.
  2. 2.如权利要求1所述的方法,其特征在于,所述方法还包括:在所述主刻蚀之前,对所述浅沟槽区域和PMOS区域的张应力层进行预刻蚀。 2. The method according to claim 1, characterized in that, said method further comprising: prior to the main etch, the layer of tensile stress shallow trench region and the PMOS region is pre-etched.
  3. 3.如权利要求2所述的方法,其特征在于,所述预刻蚀为穿透刻蚀。 The method according to claim 2, characterized in that the pre-etching to penetrate the etching.
  4. 4.如权利要求1所述的方法,其特征在于,所述主刻蚀的刻蚀方向是垂直指向所述张应力层的表面。 4. The method according to claim 1, wherein the etching direction of the main etch is directed perpendicular to the surface tensile stress layer.
  5. 5.如权利要求1所述的方法,其特征在于,所述主刻蚀中所使用的气体为包含N2O与Cl2或包含N2O与HBr的混合气体。 5. The method according to claim 1, characterized in that the main etching gas used is Cl2 containing N2O or with a mixed gas containing N2O and the HBr.
  6. 6.如权利要求1所述的方法,其特征在于,所述主刻蚀中所使用的气体为包含CHF3的刻蚀气体。 6. The method according to claim 1, characterized in that the main etching gas is used as etching gas containing CHF3.
  7. 7.如权利要求1所述的方法,其特征在于,所述主刻蚀中所使用的电源功率为300-1OOOffo 7. The method according to claim 1, wherein said main power supply is used for the etching 300-1OOOffo
  8. 8.如权利要求1所述的方法,其特征在于,所述主刻蚀选择的压力为lO-lOOmTorr。 8. The method according to claim 1, characterized in that the etching selectivity for the primary pressure lO-lOOmTorr.
  9. 9.如权利要求1所述的方法,其特征在于,所述过刻蚀中所使用的气体为包含O2与He或包含O2与HBr的混合气体。 9. The method according to claim 1, wherein said over etching gas used as containing O2 and He or a mixed gas of HBr and O2.
  10. 10.如权利要求1所述的方法,其特征在于,所述过刻蚀中所使用的气体为包含CHF3和O2的刻蚀气体。 10. The method according to claim 1, wherein said over etching gas used in etching gas comprising CHF3 and O2.
  11. 11.如权利要求1所述的方法,其特征在于,所述过刻蚀中所使用的电源功率为300-5501 11. The method according to claim 1, wherein said source power over etching is used 300-5501
  12. 12.如权利要求3所述的方法,其特征在于,所述穿透刻蚀中所使用的气体为CF4、C2F6和Cl2中的一种。 12. The method according to claim 3, wherein said etching gas penetrating used as a CF4, C2F6 and Cl2 gas.
  13. 13.如权利要求3所述的方法,其特征在于,所述穿透刻蚀中所使用的电源功率为50-1501 13. The method according to claim 3, wherein said etching penetrating power supply used is 50-1501
  14. 14.一种用于制作互补型金属氧化物半导体器件的应力层的刻蚀方法,其特征在于,所述方法包括: 提供一个具有匪OS区域、浅沟槽区域和PMOS区域的半导体器件,所述半导体器件的上表面形成有压应力层; 以光刻胶图层遮蔽所述PMOS区域上的压应力层,暴露出所述浅沟槽区域和NMOS区域的压应力层,所述光刻胶图层为经曝光、显影得到的光刻胶图层; 采用各向异性的主刻蚀对所述浅沟槽区域和NMOS区域上的压应力层进行刻蚀,以除去所述浅沟槽区域和NMOS区域至少部分的压应力层;和采用各向同性的过刻蚀去除所述浅沟槽区域和NMOS区域上的残余的压应力层,其中,所述主刻蚀和过刻蚀均为干法刻蚀。 14. A method of etching a stress layer produced a complementary metal oxide semiconductor device, characterized in that, said method comprising: providing a semiconductor device bandit OS region, shallow trench region and the PMOS region having the the upper surface of said semiconductor device is formed with a compressive stress layer; masking photoresist layer compressive stress layer on the PMOS region, the compressive stress layer is exposed shallow trench region and the NMOS region, the photoresist layer is exposed and developed to give photoresist layer; anisotropically etched principal compressive stress layer on said NMOS region and a shallow trench region is etched to remove the shallow trench region the compressive stress layer and at least a portion of the NMOS region; and isotropic etching through removal of the residual compressive stress layer on the NMOS region and a shallow trench region, wherein the main etching and over etching are dry etching.
  15. 15.如权利要求14所述的方法,其特征在于,所述方法还包括:在所述主刻蚀之前, 对所述浅沟槽区域和NMOS区域的压应力层进行穿透刻蚀。 15. The method according to claim 14, wherein said method further comprises: prior to the main etching, a compressive stress layer on the NMOS region and the shallow trench region is etched to penetrate.
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CN101330052A (en) * 2007-06-18 2008-12-24 中芯国际集成电路制造(上海)有限公司 Method for forming CMOS device stress film
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CN101330052A (en) * 2007-06-18 2008-12-24 中芯国际集成电路制造(上海)有限公司 Method for forming CMOS device stress film
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