CN102184946B - 金属半导体化合物薄膜和dram存储单元及其制备方法 - Google Patents

金属半导体化合物薄膜和dram存储单元及其制备方法 Download PDF

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CN102184946B
CN102184946B CN201110063882.2A CN201110063882A CN102184946B CN 102184946 B CN102184946 B CN 102184946B CN 201110063882 A CN201110063882 A CN 201110063882A CN 102184946 B CN102184946 B CN 102184946B
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metal
semiconductor
thin film
drain region
mos transistor
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CN102184946A (zh
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吴东平
张世理
朱志炜
张卫
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复旦大学
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    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
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    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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Abstract

本发明公开了一种金属半导体化合物薄膜,形成于半导体层与多晶半导体层之间,其厚度为2~5nm,从而改善所述半导体层与多晶半导体层之间的接触;还公开了一种DRAM存储单元,该存储单元中的MOS晶体管的漏区与多晶半导体缓冲层之间加入金属半导体化合物薄膜,且其厚度为2~5nm,从而可在提高晶体管的读写速度的同时,避免所述漏区与硅衬底之间的漏电流过度增大;同时,还公开了一种DRAM存储单元的制备方法,该方法形成的DRAM存储单元,其MOS晶体管器件的漏区与多晶半导体缓冲层之间形成有金属半导体化合物薄膜,且所述金属半导体化合物薄膜的厚度控制在2~5nm,从而可提高DRAM存储单元的性能。

Description

金属半导体化合物薄膜和DRAM存储单元及其制备方法

技术领域

[0001] 本发明涉及微电子器件技术领域,尤其涉及一种金属半导体化合物薄膜和DRAM存储单元及其制备方法。

背景技术

[0002]作为金属电极的金属半导体化合物薄膜被广泛用于金属氧化物半导体场效应晶体管(MOSFET)的源漏极和栅极,形成和硅、锗或硅-锗半导体的金-半接触。

[0003] 金属半导体化合物薄膜的主要作用从一开始的为简单的二极管提供可靠的接触,到近来利用自对准金属半导体化合物薄膜形成工艺(salicide)为MOSFET形成低阻源漏接触和低方块电阻栅电极,在CMOS器件尺寸的微缩化及提高器件性能上起着非常重要的作用。随着半导体制备工艺技术的进步,金属半导体化合物薄膜从早期的硅化钛(TiSi2)、硅化钴(CoSi2)发展到现在主流的的硅化镍(NiSi)或掺铂硅化镍(Ni (Pt) Si)。

[0004]并且随着器件尺寸的缩小,金属半导体化合物薄膜的厚度也要求越来越薄;这一点在动态随机存储器(DRAM,Dynamic Random Access Memory)中表现尤为明显。

[0005] DRAM通常由多个基本存储单元按照行和列组成,每个存储单元包括一个MOS晶体管及一个电容,所述MOS晶体管的源区与位线(bit line)相连,其栅区与字线(word line)相连,其漏区通过一缓冲层与所述电容相连,其中,所述缓冲层为高掺杂多晶硅层,所述电容为金属-绝缘层-金属(MIM,Metal-1nsulator_Metal)电容。之所以在漏区与所述电容之间加入高掺杂多晶硅层,是因为如果M頂电容的金属电极和硅衬底直接接触,将会使得漏区与硅衬底之间形成的PN结(简称漏极PN结)的漏电流增大,从而导致DRAM存储单元的电荷保持能力下降;加入高掺杂多晶硅层可避免漏极PN结的漏电流过度增大。

[0006] 然而,由于所述漏区的组成材料为Si,而Si与多晶硅之间的接触电阻很大,并且由于Si的表面通常会形成一层天然的氧化层,因而进一步增大了 Si与多晶硅之间的接触电阻,从而使得晶体管的读写速度降低。

[0007] 为了提高晶体管的读写速度,目前采取的办法是在所述漏区形成一层金属半导体化合物薄膜,所述漏区通过所述金属半导体化合物薄膜与所述多晶硅相连,从而可大大降低所述漏区与所述多晶硅之间的接触电阻,提高所述晶体管的读写速度。

[0008] 然而,在所述漏区形成一层金属半导体化合物薄膜后,所述漏区与半导体衬底之间形成的PN结的电阻也随之降低,使得所述PN结的漏电流增大,从而导致所述电容中存储的电荷容易流失,使得所述电容的存储能力下降,因而需对DRAM不断进行刷新;并且金属半导体化合物薄膜层的厚度越厚,所述电容的存储能力越差。

[0009]因此,为了在提高所述晶体管的读写能力的同时,保证所述电容的存储能力,希望所述金属半导体化合物薄膜的厚度越薄越好。

[0010]目前,形成金属半导体化合物薄膜的方法主要有以下几种:

[0011] I)硅化钛工艺

[0012] 硅化钛工艺是先将钛金属沉积在晶片上,然后经过稍低温度的第一次退火,得到高阻的中间亚稳相C49,然后再经过温度稍高的第二次退火,使C49相转变成最终需要的低阻C54相(稳定)。硅化钛具有形成工艺简单、高温稳定性好等优点。然而,随着MOSFET尺寸的不断变小,会出现硅化钛的形成和相变不彻底的现象,尤其是其窄线条效应,即硅化钛的形成和相变随着线宽或接触面积的减小而变得更加困难,这不仅大大增加了接触电阻和寄生串联电阻,而且导致了器件和器件、电路和电路及芯片和芯片之间特性的不稳定和不重复;

[0013] 2)硅化钴工艺

[0014] 为了解决较小尺寸下出现的线宽效应,硅化钴作为硅化钛的替代品应运而生,但当器件尺寸更小时,窄线条效应在硅化钴的形成中仍然会出现;随着有源区掺杂深度不断变浅,硅化钴形成过程中也会过度消耗表面高掺杂硅;

[0015] 3)硅化镍工艺

[0016] 相对于之前的硅化钛和硅化钴而言,硅化镍具有一系列独特的优势。硅化镍仍然沿用之前硅化物类似的两步退火工艺,但是退火温度有了明显降低(<600°C),这样就大大减少对器件已形成的超浅结的破坏,较低的退火温度不会导致已掺杂离子在硅化物形成过程中的扩散。同时,较低的退火温度也有利于更加先进的材料和技术的集成,这里特别包括了高介电系数的介质栅(high-K dielectric)和金属栅极(metal gate);镍的娃化物的形成即使在30纳米以下的线条中都没有发现窄线条效应;硅化镍的形成过程对源/漏区的硅的消耗较少,而靠近表面的硅刚好是掺杂浓度最大的区域,因而对于降低整体的接触电阻十分有利。

[0017] 然而,超薄镍硅化物也面临一系列的问题。一方面,通常使用的低阻硅化镍薄膜有着一镍一硅的化学组份比,即一硅化镍NiSi。而由于Si的存在并直接同NiSi接触,随着温度的升高,NiSi会和Si发生反应,形成更加稳定的二娃化镍NiSi2相,即低阻的一娃化镍相有着潜在的高温不稳定性,对随后的后端工艺中各个步骤的最高温度产生了限制;另一方面,随着超薄硅化物的厚度越来越小,原先的连续厚度均匀的薄膜会由于表面张力作用,会出现厚度不均匀甚至变成类似于岛状的不连续形状,从而导致电阻变大甚至不导电;另外,通常的硅化镍形成工艺在形成硅化物时的速度不易控,不利于形成超薄的硅化物层。

[0018]因此,有必要对现有的金属半导体化合物薄膜的制备方法进行改进。

发明内容

[0019] 本发明的目的在于提供一种金属半导体化合物薄膜和带金属半导体化合物薄膜的DRAM存储单元及其制备方法,以解决现有的DRAM存储单元的晶体管的读写速度与电容的存储能力矛盾制约的问题。

[0020] 为解决上述问题,本发明提出一种金属半导体化合物薄膜,形成于半导体层与多晶半导体层之间,用于改善所述半导体层与所述多晶半导体层之间的接触,所述金属半导体化合物薄膜的厚度为2〜5nm ο

[0021] 可选的,所述半导体层为硅或绝缘层上硅,所述多晶半导体层为掺杂多晶硅,所述金属半导体化合物薄膜为金属硅化物。

[0022] 可选的,所述半导体层为锗或绝缘层上锗,所述多晶半导体层为掺杂多晶锗,所述金属半导体化合物薄膜为金属锗化物。

[0023]可选的,所述金属半导体化合物薄膜由金属与所述半导体层反应生成,其中,所述金属为镍、钴、钛中的任一种,或镍、钴、钛中的任一种并掺入铂。

[0024] 可选的,所述金属中还掺入了钨和/或钼。

[0025]同时,为解决上述问题,本发明还提出一种DRAM存储单元,包括半导体衬底、形成于所述半导体衬底上的MOS晶体管及电容,所述MOS晶体管的源区与一位线相连,其栅区与一字线相连,其漏区通过一缓冲层与所述电容相连,所述缓冲层的材料为多晶半导体,在所述漏区与所述缓冲层之间还包括金属半导体化合物薄膜,所述金属半导体化合物薄膜的厚度为2〜5nm。

[0026] 可选的,所述半导体衬底为硅或绝缘层上硅,所述多晶半导体为掺杂多晶硅,所述金属半导体化合物薄膜为金属硅化物。

[0027]可选的,所述半导体衬底为锗或绝缘层上锗,所述多晶半导体为掺杂多晶锗,所述金属半导体化合物薄膜为金属锗化物。

[0028]可选的,所述金属半导体化合物薄膜由金属与所述漏区的半导体层反应生成,其中,所述金属为镍、钴、钛中的任一种,或镍、钴、钛中的任一种并掺入铂。

[0029] 可选的,所述金属中还掺入了钨和/或钼。

[0030] 同时,为解决上述问题,本发明还提出一种DRAM存储单元的制备方法,该方法包括如下步骤:

[0031] 提供一半导体衬底,并在所述半导体衬底上形成MOS晶体管器件;

[0032] 在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜,所述金属半导体化合物薄膜的厚度为2〜5nm;

[0033] 在所述金属半导体化合物薄膜上形成缓冲层;

[0034] 在所述半导体衬底上形成电容,所述电容与所述缓冲层相连。

[0035]可选的,在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜进一步包括如下步骤:

[0036] 在所述MOS晶体管器件的漏区上沉积金属层,所述金属向所述漏区扩散;

[0037]去除所述漏区表面剩余的金属层;

[0038] 进行退火,在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜。

[0039]可选的,在所述半导体衬底上沉积金属层时的衬底温度为O〜300°C。

[0040] 可选的,所述退火的温度为200〜900°C。

[0041] 可选的,所述半导体衬底为硅或绝缘层上硅,所述多晶半导体为掺杂多晶硅,所述金属半导体化合物薄膜为金属硅化物。

[0042]可选的,所述半导体衬底为锗或绝缘层上锗,所述多晶半导体为掺杂多晶锗,所述金属半导体化合物薄膜为金属锗化物。

[0043]可选的,所述金属半导体化合物薄膜由金属与所述漏区的半导体层反应生成,其中,所述金属为镍、钴、钛中的任一种,或镍、钴、钛中的任一种并掺入铂。

[0044] 可选的,所述金属中还掺入了钨和/或钼。

[0045] 可选的,该方法还包括将所述MOS晶体管的源区与一位线相连的步骤,以及将所述MOS晶体管的栅区与一字线相连的步骤。

[0046] 本发明由于采用上述技术方案,使之与现有技术相比,具有以下的优点和积极效果:

[0047] I)通过在半导体层与多晶半导体层之间加入金属半导体化合物薄膜,减小了半导体层与多晶半导体层之间的接触电阻,提高了其接触性能;

[0048] 2)通过在DRAM存储单元中的MOS晶体管器件的漏区与多晶半导体缓冲层之间加入金属半导体化合物薄膜,减小了漏区与多晶半导体缓冲层之间的接触电阻,提高了 DRAM存储单元的晶体管的读写速度;同时通过将所述金属半导体化合物薄膜的厚度控制在2〜5nm,避免了所述漏区与硅衬底之间的漏电流过度增大,防止了所述电容上存储的电荷过快流失,从而降低了 DRAM存储器的刷新频率;

[0049] 3)本发明提供的DRAM存储单元的制备方法形成的DRAM存储单元,其MOS晶体管器件的漏区与多晶半导体缓冲层之间形成有金属半导体化合物薄膜,且所述金属半导体化合物薄膜的厚度控制在2〜5nm,从而可提高DRAM存储单元的性能。

附图说明

[0050]图1为本发明实施例提供的半导体层与多晶半导体层接触的示意图;

[0051]图2为本发明实施例提供的DRAM存储单元的制备方法的步骤流程图。

具体实施方式

[0052]以下结合附图和具体实施例对本发明提出的一种金属半导体化合物薄膜和DRAM存储单元及其制备方法作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比率,仅用于方便、明晰地辅助说明本发明实施例的目的。

[0053] 本发明的核心思想在于,提供一种金属半导体化合物薄膜,形成于半导体层与多晶半导体层之间,所述金属半导体化合物薄膜的厚度为2〜5nm,从而改善所述半导体层与所述多晶半导体层之间的接触;同时,提供一种DRAM存储单元,所述DRAM存储单元中的MOS晶体管器件的漏区与多晶半导体缓冲层之间加入金属半导体化合物薄膜,且所述金属半导体化合物薄膜的厚度控制在2〜5nm,从而可在提高DRAM存储单元的晶体管的读写速度的同时,避免所述漏区与半导体衬底之间的漏电流过度增大;同时,还提供一种DRAM存储单元的制备方法,该方法形成的DRAM存储单元,其MOS晶体管器件的漏区与多晶半导体缓冲层之间形成有金属半导体化合物薄膜,且所述金属半导体化合物薄膜的厚度控制在2〜5nm,从而可提尚DRAM存储单兀的性能。

[0054] 请参考图1,图1为本发明实施例提供的半导体层与多晶半导体层接触的示意图,如图1所示,本发明实施例提供的金属半导体化合物薄膜300,形成于半导体层100与多晶半导体层200之间,用于改善所述半导体层100与所述多晶半导体层200之间的接触,所述金属半导体化合物薄膜300的厚度为2〜5nm。

[0055] 进一步地,所述半导体层100为硅或绝缘层上硅,所述多晶半导体层200为掺杂多晶硅,所述金属半导体化合物薄膜300为金属硅化物。

[0056] 进一步地,所述半导体层100为锗或绝缘层上锗,所述多晶半导体层200为掺杂多晶锗,所述金属半导体化合物薄膜300为金属锗化物。

[0057] 进一步地,所述金属半导体化合物薄膜300由金属与所述半导体层100反应生成,其中,所述金属为镍、钴、钛中的任一种,或镍、钴、钛中的任一种并掺入铂。

[0058] 进一步地,所述金属中还掺入了钨和/或钼。

[0059]同时,本发明实施例还提供了一种DRAM存储单元,包括半导体衬底、形成于所述半导体衬底上的MOS晶体管及电容,所述MOS晶体管的源区与一位线相连,其栅区与一字线相连,其漏区通过一缓冲层与所述电容相连,所述缓冲层的材料为多晶半导体,在所述漏区与所述缓冲层之间还包括金属半导体化合物薄膜,所述金属半导体化合物薄膜的厚度为2〜5nm0

[0060] 通过在所述DRAM存储单元中的MOS晶体管器件的漏区与所述缓冲层之间加入金属半导体化合物薄膜,且所述金属半导体化合物薄膜的厚度控制在2〜5nm,从而可在提高DRAM存储单元的晶体管的读写速度的同时,避免所述漏区与硅衬底之间的漏电流过度增大。

[0061] 进一步地,所述半导体衬底为硅或绝缘层上硅,所述多晶半导体为掺杂多晶硅,所述金属半导体化合物薄膜为金属硅化物。

[0062] 进一步地,所述半导体衬底为锗或绝缘层上锗,所述多晶半导体为掺杂多晶锗,所述金属半导体化合物薄膜为金属锗化物。

[0063] 进一步地,所述金属半导体化合物薄膜由金属与所述漏区的半导体层反应生成,其中,所述金属为镍、钴、钛中的任一种,或镍、钴、钛中的任一种并掺入铂。

[0064] 进一步地,所述金属中还掺入了钨和/或钼。

[0065] 请继续参考图2,图2为本发明实施例提供的DRAM存储单元的制备方法的步骤流程图,如图2所示,本发明实施例提供的DRAM存储单元的制备方法包括如下步骤:

[0066] S101、提供一半导体衬底,并在所述半导体衬底上形成MOS晶体管器件;具体地,在所述半导体衬底上形成MOS晶体管器件包括如下步骤:首先在所述半导体衬底上形成栅叠层,并经过光刻及刻蚀形成栅电极;然后通过离子注入掺杂分别形成源区与漏区;其中,所述栅叠层包括多晶硅,以及在所述多晶硅上依次形成的金属硅化物和绝缘层;

[0067] S102、在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜,所述金属半导体化合物薄膜的厚度为2〜5nm;

[0068] S103、在所述金属半导体化合物薄膜上形成缓冲层;具体地,所述缓冲层为多晶半导体层;

[0069] S104、在所述半导体衬底上形成电容,所述电容与所述缓冲层相连。具体地,所述电容为MIM电容。

[0070] 本发明提供的DRAM存储单元的制备方法,在MOS晶体管器件的漏区与所述缓冲层之间形成金属半导体化合物薄膜,且所述金属半导体化合物薄膜的厚度控制在2〜5nm,从而可在提高DRAM存储单元的晶体管的读写速度的同时,避免所述漏区与半导体衬底之间的漏电流过度增大。

[0071] 进一步地,在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜包括如下步骤:

[0072] 在所述MOS晶体管器件的漏区上沉积金属层,所述金属向所述漏区扩散;

[0073]去除所述漏区表面剩余的金属层;

[0074] 进行退火,在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜。

[0075]由于金属往半导体衬底中的扩散饱和度是一定的,因此,上述方法形成的金属半导体化合物薄膜的厚度是可控的(即最终形成的金属半导体化合物薄膜的厚度是一定的),并且厚度极薄,从而有利于提尚DRAM存储单兀的性能。

[0076] 进一步地,在所述半导体衬底上沉积金属层时的衬底温度为O〜300°C。

[0077] 进一步地,所述退火的温度为200〜900°C。

[0078] 进一步地,所述半导体衬底为硅或绝缘层上硅,所述多晶半导体为掺杂多晶硅,所述金属半导体化合物薄膜为金属硅化物。

[0079] 进一步地,所述半导体衬底为锗或绝缘层上锗,所述多晶半导体为掺杂多晶锗,所述金属半导体化合物薄膜为金属锗化物。

[0080] 进一步地,所述金属半导体化合物薄膜由金属与所述漏区的半导体层反应生成,其中,所述金属为镍、钴、钛中的任一种,或镍、钴、钛中的任一种并掺入铂;掺入铂是因为纯的一硅化镍在高温条件下稳定性差,或出现薄膜厚度变得不均匀并结块,或生成电阻率高的二硅化镍NiSi2,严重影响器件的性能,因此,为了减慢硅化镍的生长速度以及防止硅化镍薄层遇到高温时发生结块或形成二硅化镍,可以在镍中掺入一定比例的铂;其它金属中掺铂作类似解释。

[0081] 进一步地,所述金属中还掺入了钨和/或钼;以进一步控制硅化镍或掺铂硅化镍的生长和镍/铂的扩散,并增加硅化镍或掺铂硅化镍的稳定性;其它金属中掺钨和/或钼作类似解释。

[0082] 进一步地,该方法还包括将所述MOS晶体管的源区与一位线相连的步骤,以及将所述MOS晶体管的栅区与一字线相连的步骤。

[0083] 综上所述,本发明提供了一种金属半导体化合物薄膜,形成于半导体层与多晶半导体层之间,所述金属半导体化合物薄膜的厚度为2〜5nm,从而改善所述半导体层与所述多晶半导体层之间的接触;同时,提供了一种DRAM存储单元,所述DRAM存储单元中的MOS晶体管器件的漏区与多晶半导体缓冲层之间加入金属半导体化合物薄膜,且所述金属半导体化合物薄膜的厚度控制在2〜5nm,从而可在提高DRAM存储单元的晶体管的读写速度的同时,避免所述漏区与半导体衬底之间的漏电流过度增大;同时,还提供了一种DRAM存储单元的制备方法,该方法形成的DRAM存储单元,其MOS晶体管器件的漏区与多晶半导体缓冲层之间形成有金属半导体化合物薄膜,且所述金属半导体化合物薄膜的厚度控制在2〜5nm,从而可提尚DRAM存储单兀的性能。

[0084]显然,本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。

Claims (6)

1.一种DRAM存储单元,包括半导体衬底、形成于所述半导体衬底上的MOS晶体管及电容,所述MOS晶体管的源区与一位线相连,其栅区与一字线相连,其漏区通过一缓冲层与所述电容相连,所述缓冲层的材料为多晶半导体,其特征在于,在所述漏区与所述缓冲层之间还包括金属半导体化合物薄膜,其中所述金属半导体化合物薄膜为金属锗化物,所述金属为镍、钛中任一种,或镍、钛中的任一种并掺入铂,所述金属半导体化合物薄膜的厚度为2nm; 所述的DRAM存储单元的制备方法,包括如下步骤: 提供一半导体衬底,并在所述半导体衬底上形成MOS晶体管器件; 在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜,其中所述金属半导体化合物薄膜为金属锗化物,所述金属为镍、钛中任一种,或镍、钛中的任一种并掺入铂,所述金属半导体化合物薄膜的厚度为2nm; 在所述金属半导体化合物薄膜上形成缓冲层; 在所述半导体衬底上形成电容,所述电容与所述缓冲层相连; 其中,在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜进一步包括如下步骤: 在所述MOS晶体管器件的漏区上沉积金属层,所述金属向所述漏区扩散; 去除所述漏区表面剩余的金属层; 进行退火,在所述MOS晶体管器件的漏区形成金属半导体化合物薄膜;所述漏区上沉积金属层时的衬底温度为O〜300°C。
2.如权利要求1所述的DRAM存储单元,其特征在于,所述半导体衬底为锗或绝缘层上锗,所述多晶半导体为掺杂多晶锗。
3.如权利要求2所述的DRAM存储单元,其特征在于,所述金属半导体化合物薄膜由金属与所述漏区的半导体层反应生成。
4.如权利要求3所述的DRAM存储单元,其特征在于,所述金属中还掺入了钨和/或钼。
5.如权利要求1所述的DRAM存储单元,其特征在于,所述退火的温度为200〜900°C。
6.如权利要求1所述的DRAM存储单元,其特征在于,该方法还包括将所述MOS晶体管的源区与一位线相连的步骤,以及将所述MOS晶体管的栅区与一字线相连的步骤。
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