CN102163248A - Advanced synthesizing method for integrated circuit - Google Patents
Advanced synthesizing method for integrated circuit Download PDFInfo
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Abstract
The invention discloses an advanced synthesizing method for an integrated circuit. First intermediate language is generated through synthesis, and a corresponding reconfigurable operator executable file or a corresponding hardware description file is generated by the first intermediate language, so that an output has a multi-target characteristic, namely a system which is described by a high-level language input file can be downloaded to a reconfigurable operator array for implementation by generating a reconfigurable operator array executable file, and also can be downloaded to a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) for implementation by generating the hardware description file.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, relate in particular to a kind of higher synthesis method of integrated circuit.
Background technology
Fast development along with fields such as communication, computing machine, consumer electronics, the hardware system that carries these application is had higher requirement at aspects such as performance, power consumption, cost, Time To Market, dirigibility, extensibilities, traditional method for designing such as ASIC (Application Specific Intergrated Circuits, special IC), DSP (Digital Signal Processing, digital signal processor)/CPU and FPGA (Field Programmable Gate Array, field programmable gate array) be faced with some problems.
The complicacy and the scale of ASIC design constantly promote, and make the ASIC design cost increase, and the design cycle is elongated, owing to do not have a dirigibility, can not expand simultaneously, the quick listing of product and cheaply demand make ASIC design to have run into bottleneck.And that CPU/DSP relies on the method for complicated architecture and order set to obtain the required cost of paying of performance boost is increasing, and the processing power of single processor can not satisfy the needs of current application far away.FPGA is as parallel computation application early, its performance and can loss-rate between ASIC and DSP/CPU, have certain dirigibility, can programme repeatedly, can satisfy quick listing and application demand cheaply.But the direct mapping from the algorithm to hardware is not supported in the design of FPGA, and design needs algorithm personnel and hardware personnel's fellowship, and the abstraction hierarchy of hardware description language is lower, and the exploitation of application still exists very big complicacy.
The restructural operator array structure of Shenzhen Graduate School of Peking University integrated micro-system laboratory proposes a kind of unified shader based on parallel computing, Fig. 1 is the overall construction drawing of APU (Array Processing for UnificationArchitecture).This APU structure 1000 is made up of arithmetic class restructural operator 1001, class of paths restructural operator 1002, scheduling class restructural operator 1003, DSP class restructural operator 1004, storage class restructural operator 1005 and IO1006.Inside in APU structure 1000, arithmetic class restructural operator 1001, class of paths restructural operator 1002, scheduling class restructural operator 1003, DSP class restructural operator 1004, storage class restructural operator 1005 are according to certain ratio, according to type independently with the unit of classifying as, distributed cross arrangement.APU support mass data parallel/computing and the transmission demand of serial, and can support the needs that multiple application realizes.
APU Application Design descriptive language is a higher level lanquage, and abstraction hierarchy is higher, has shortened the application and development time.So must introduce corresponding higher synthesis method to practice.
Conventional higher synthesis method can only generate corresponding digital circuit information according to input file and unbound document, and the digital circuit information of generation can only implement or be converted to corresponding ASIC usually on FPGA.
Conventional higher synthesis method converts the language element of input file to CDFG (Control Data FlowGraph, the Data Control flow graph), distribute the time corresponding nodal information for each CDFG node, the emission process of output file converts CDFG time corresponding nodal information to the state machine information of digital circuit again.Because switching, the state of digital circuit state machine have certain hour at interval, so conventional higher synthesis method is equivalent to carry out efficient and dirigibility and all be difficult to expand by the described system of time marking scheduling input file.
Summary of the invention
The main technical problem to be solved in the present invention is, a kind of higher synthesis method of integrated circuit is provided, its output has multiple goal, and have flexibly, enforceability is high, carry out the high characteristics of efficient, its output simultaneously both can be implemented on restructural operator array, also can download to FPGA or ASIC and go up enforcement.
For solving the problems of the technologies described above, the technical solution used in the present invention is as follows:
A kind of higher synthesis method of integrated circuit comprises step:
The higher level lanquage input file of digital circuit is described in input, and carries out the comprehensive constraint setting;
Higher level lanquage input file and comprehensive constraint according to described digital circuit generate first intermediate language, and the annexation between a specific digital circuit structure and each digital circuit structure represented in each bar statement of described first intermediate language;
Described first intermediate language is converted to restructural operator executable file, and be downloaded in the described restructural operator array and implement, perhaps described first intermediate language is converted to the corresponding hardware description document, and generates the corresponding digital circuit according to described hardware description file.
Further, generate described first intermediate language and comprise step:
The described higher level lanquage input file and the comprehensive constraint of input are carried out in advance comprehensively, generate the 3rd intermediate language, the principal function that described the 3rd intermediate language is served as reasons and had the statement block of list interface or have the nested statement piece formation of list interface;
Described the 3rd intermediate language is carried out comprehensive front-end, the comprehensive abstract syntax tree that generates, described abstract syntax tree comprise interface message and the described digital circuitry IO interface of input file information between the described statement block information of described higher level lanquage input file, the statement block;
Travel through described abstract syntax tree, and be converted to second intermediate language according to predetermined comprehensive strategic, the functional module annexation of functional module and other modules therewith all represented in each bar statement of described second intermediate language;
Described second intermediate language is carried out comprehensive rear end, generate first intermediate language.
Further, described predetermined comprehensive strategic comprises hardware configuration, input file language format, the circuit resource usage policy of arithmetic speed, the power consumption of comprehensive back output system, the actual circuit area that uses, all kinds of circuit resource relative scale, target restructural operator array.
Further, described abstract syntax tree comprises root node; First node is used to store the input/output information of described higher level lanquage input file institute descriptive system; Section Point is used for storing the global variable of higher level lanquage input file or the claim information of array; The 3rd node is used for storing the information of all functions of higher level lanquage input file, and described first node, Section Point and the 3rd node all link to each other with described root node, then travels through described abstract syntax tree and generates described second intermediate language and comprise step:
Read each node of abstract syntax tree, obtain the information of each node;
Collect the relevant information of and function statement block in the abstract syntax tree, and storage;
According to described nodal information and function information, check whether described abstract syntax tree generates correct, in this way, then launch second intermediate language according to the nodal information that reads.
Further, described first intermediate language is carried out emulation and comprises step:
Configuration analogue system operational factor when analogue system starts comprises that input treats first intermediate language of emulation, input emulated data file, output emulated data file, analogue system working time etc.;
Read the system description file that first intermediate language of emulation is treated in input, each submodule of describing in the generation system description document;
Data in the input emulated data file are input in the data storage container of system, wait for that each submodule starts;
Read the system description file that emulation is treated in input, connect described all submodules that generate;
Start the operation of whole simulation, promptly start all submodule work;
Output data described in the output emulated data file is to specified file.
Further, described first intermediate language is converted to restructural operator executable file and comprises step:
On restructural operator array, carry out placement-and-routing according to described first intermediate language;
Restructural operator array after the placement-and-routing is carried out emulation and checking;
To be restructural operator executable file through the file conversion of the output after the checking.
Further, carry out placement-and-routing on the restructural operator array again according to described first intermediate language and comprise step:
Determine its enforcing location in restructural operator array according to the optional network specific digit circuit structure in every statement of described first intermediate language;
According to the annexation between each optional network specific digit circuit structure in each statement of described first intermediate language, determine to finish the circuit resource situation that annexation consumed between each specific digital circuit structure again.
Further, each bar statement of described first intermediate language comprises function information and link information, then described first intermediate language is converted to the relevant hardware description document and comprises step:
Mainly read the function information and the link information of described first intermediate language;
Search the hardware description language model bank according to described function information, obtain the relevant hardware descriptive language and describe;
In conjunction with described link information, generate relevant hardware descriptive language file.
The invention has the beneficial effects as follows: higher synthesis method of the present invention comprises and imports the higher level lanquage input file of describing digital circuit, and it is carried out the comprehensive constraint setting; According to the higher level lanquage input file and the comprehensive constraint of described digital circuit, generate first intermediate language again, the annexation between a specific digital circuit structure and each digital circuit structure represented in each bar statement of described first intermediate language; Then described first intermediate language is converted to restructural operator executable file, and be downloaded in the described restructural operator array and implement, perhaps described first intermediate language is converted to the corresponding hardware description document, and generates the corresponding digital circuit according to described hardware description file.Higher synthesis method of the present invention is by generating first intermediate language, generate restructural operator array executable file by this first intermediate language again, thereby the described system downloads of higher level lanquage input file is implemented to restructural operator array, perhaps generate the hardware description file according to this first intermediate language, thereby the described system downloads of higher level lanquage input file is gone up enforcement to FPGA or ASIC, the output that is higher synthesis method of the present invention has multiple goal, and dirigibility, enforceability height, carries out the efficient height.
On the other hand, higher synthesis method of the present invention, by senior input file being converted to the 3rd high intermediate language of abstraction hierarchy, be converted to the second lower intermediate language of abstraction hierarchy by the 3rd intermediate language again, this second intermediate language approaches modular digital circuit and describes, be converted to first intermediate language by this second intermediate language again, directly be converted to hardware description language or restructural operator array by this first intermediate language at last.The present invention adopts first intermediate language, second intermediate language and the 3rd intermediate language of the modularization idea intermediate representation form as transfer process, and description has the characteristic of certain functional module and the annexation and the correspondence of intermodule emphatically.This higher synthesis process is dispatched the described system of higher level lanquage input file by the annexation of modular character, intermodule and the communication mechanism of intermodule, thereby the restructural operator array configurations information that generates or digital circuit information is flexible, enforceability is high, and carry out the efficient height.
Description of drawings
Fig. 1 is a kind of structural representation of restructural operator array;
Fig. 2 is the process flow diagram of a kind of embodiment of the higher synthesis method of integrated circuit of the present invention;
Fig. 3 is the process flow diagram that generates a kind of embodiment of first intermediate language in the higher synthesis method of integrated circuit of the present invention;
Fig. 4 is the synoptic diagram of a kind of embodiment of the language construction of the 3rd intermediate language that generates in the higher synthesis method of integrated circuit of the present invention;
Fig. 5 is the synoptic diagram of a kind of embodiment of the composition structure of the statement block of the 3rd intermediate language that generates in the higher synthesis method of integrated circuit of the present invention;
Fig. 6 a and Fig. 6 b are respectively a kind of embodiment of higher level lanquage input file of the present invention and by a kind of embodiment of corresponding the 3rd intermediate language that generates of higher level lanquage input file;
Fig. 7 is the process flow diagram that the higher level lanquage input file is carried out pre-comprehensive a kind of embodiment of the present invention;
Fig. 8 is the synoptic diagram of a kind of embodiment of the general construction of the abstract syntax tree that generates in the higher synthesis method of integrated circuit of the present invention;
The synoptic diagram of a kind of embodiment of the composition structure of the child node of the 3rd node that generates in the higher synthesis method of Fig. 9 for figure integrated circuit of the present invention;
Figure 10 is the process flow diagram that generates a kind of embodiment of second intermediate language in the higher synthesis method of integrated circuit of the present invention;
Figure 11 is the structural representation of a kind of specific embodiment of the abstract syntax tree that generates in the higher synthesis method of integrated circuit of the present invention;
Figure 12 is for carrying out the process flow diagram of a kind of embodiment of emulation to first intermediate language that generates in the higher synthesis method of integrated circuit of the present invention;
Figure 13 a and Figure 13 b are respectively a kind of embodiment of the second intermediate language description document that generates in the higher synthesis method of integrated circuit of the present invention and a kind of embodiment of the first intermediate language description document that generated by this second intermediate language description document;
Figure 14 is for carrying out the process flow diagram of a kind of embodiment of emulation to first intermediate language that generates in the higher synthesis method of integrated circuit of the present invention;
Figure 15 is the process flow diagram that generates a kind of embodiment of restructural operator array executable file in the higher synthesis method of integrated circuit of the present invention;
Figure 16 is the process flow diagram that generates a kind of embodiment of hardware description language file in the higher synthesis method of integrated circuit of the present invention;
Figure 17 a and Figure 17 b are respectively a kind of embodiment of the first intermediate language description document that the higher synthesis method of integrated circuit of the present invention generates and are converted to a kind of embodiment of hardware description file by this first intermediate language description document.
Embodiment
In conjunction with the accompanying drawings the present invention is described in further detail below by embodiment.
Please refer to Fig. 2, the higher synthesis method of the integrated circuit of present embodiment comprises step:
S1, the higher level lanquage input file of digital circuit is described in input.
Higher level lanquage input file in the present embodiment is for describing the input file of digital circuit situation, and it can be C language or other higher level lanquages, as Java, and C++, Matlab etc.
S2 carries out the comprehensive constraint setting.
Comprehensive constraint in the present embodiment is realized with man-machine interfaces such as file input or keyboard inputs.
Present embodiment has retrained hardware configuration, input file language format, the circuit resource usage policy of arithmetic speed, the power consumption of system design output, the actual circuit area that uses, all kinds of circuit resource relative scale, target restructural operator array by comprehensive constraint setting.Wherein, the circuit resource usage policy is meant to be realized under the situation of said function, the selection strategy in multiple different circuit resource operational version, and the ratio between circuit module type of using between different schemes and the different circuit module type is all different.
S3, higher level lanquage input file and comprehensive constraint according to digital circuit generate first intermediate language.
The annexation between a specific digital circuit structure and each digital circuit structure represented in each bar statement of first intermediate language in this enforcement side.
Please refer to Fig. 3, in the present embodiment, generate first intermediate language by the higher level lanquage input file among the step S3 and comprise step:
S31 carries out higher level lanquage input file and the comprehensive constraint of importing in advance comprehensively, generates the 3rd intermediate language.Being about to the higher level lanquage input file is converted to by the statement block that has list interface or has the principal function that the nested statement piece of list interface constitutes, i.e. the 3rd intermediate language.
Abstract syntax tree in the present embodiment is the data store organisation of a tree type, and it comprises interface message and the described digital circuitry IO interface of input file information between the described statement block information of higher level lanquage input file, statement block of digital circuit situation.
Please refer to Fig. 4, be the language construction figure of the 3rd intermediate language of present embodiment, the description of top layer is a principal function piece 301, and principal function 301 has been finished the description to higher level lanquage input file institute descriptive system.Comprised each substatement piece 302 in this principal function 301, high-rise statement block 302 can be made up of the statement block 302 of bottom, and wherein, bottom substatement piece 302 is made up of each statement 303 or all kinds of control structure 304.
Certainly, also can be nested against one another between the statement block 302 in the present embodiment, as shown in Figure 5.
In a kind of specific embodiment of the 3rd intermediate language of present embodiment:
" const2=4 wherein; " be constant assignment statement 303; " op1=ip3+ip4; " be computing assignment statement 303.
Please refer to Fig. 4, the control structure 304 in the present embodiment is divided into: branched structure, loop structure and multiplexing structure.Wherein branched structure is realized by the if statement block, and loop structure realizes that by the while statement piece multiplexing structure is realized by function.This control structure 304 mainly comprises the key word of control structure, the execution body of control structure, and this carries out the function of volume description control structure, and list interface 305, and list interface 305 is made up of with certain set variable or array.Please refer to Fig. 5, the list interface 305 in the present embodiment is used for the interface message between descriptive statement piece and the statement block, communicates by this list interface 305 between the statement block.
In a kind of specific embodiment of loop structure in the present embodiment by the realization of the 3rd intermediate language:
Wherein, while is a key word, the representative circulation; " { a=b+i; I=i+c_1; " be the execution body of this control structure 304, the function of this control structure 304 has been described; " #info (a, i; B, const; Const; I) " be the list interface of this control structure 304.
Please refer to Fig. 6 a, be the selected parts of a kind of embodiment of input higher level lanquage input file, op1 wherein, op2, op3, wr_tmp1, variablees such as wr_tmp2 are global variable, array a_ar[], b_ar[] be overall array.Please refer to Fig. 7, the input higher level lanquage file shown in Fig. 6 a is carried out in advance comprehensively, thereby a kind of specific embodiment that is converted to the 3rd intermediate language comprise step:
S701, detect this higher level lanquage input file.
S702, after detecting above-mentioned subfunction testFun, detect the array that is read among this subfunction testFun, promptly appear at the array on the right of "=", and according to first element a_ar of the corresponding generation list interface of this array.
S703 detects the array that is written among this subfunction testFun, promptly appears at "=" array on the left side, and generate second element b_ar of list interface according to these data.
S704 detects the variable of the rreturn value that is endowed subfunction testFun, and generates the 3rd element op1 of list interface according to this variable.
S705 detects among this subfunction testFun, finishes the variable that writes or read array manipulation, and generates the 4th element wr_tmp1 of corresponding list interface, wr_tmp2, x, y according to this variable.
S706 generates the 3rd corresponding intermediate language description document, shown in Fig. 6 b
S32 carries out comprehensive front-end with the 3rd intermediate language that generates, and comprehensively generates abstract syntax tree.
Please refer to Fig. 8, be the general construction of the abstract syntax tree AST in the present embodiment, comprise the root node program801 of whole procedure; The child node of first node 802 has been stored the input/output information of the middle-and-high-ranking language input file of step S1 institute descriptive system; Section Point 803 has been stored the global variable in the middle-and-high-ranking language input file of step S1 or the claim information of array, and global variable or array are meant in all functions all effectively variable or array; The 3rd node 804 has been stored the information of all functions in the middle-and-high-ranking language input file of step S1.
Please refer to Fig. 9, wherein the 3rd node 804 is made up of a plurality of nodes 901, first child node 902 of node 901 has comprised the type information of function return value, second child node 903 has comprised function name information, the 3rd child node 904 has comprised function shape ginseng information, the 4th child node 905 and the 6th child node 907 have comprised this function statement piece and other statement block interface messages, and the 5th child node 906 has comprised the information of function body statement block.
S33 travels through above-mentioned abstract syntax tree, and according to predetermined comprehensive strategic, this abstract syntax tree is converted to second intermediate language.
Predetermined comprehensive strategic in the present embodiment comprises hardware configuration, input file language format, the circuit resource usage policy of arithmetic speed, the power consumption of comprehensive back output system, the actual circuit area that uses, all kinds of circuit resource relative scale, target restructural operator array.
The functional module annexation of functional module and other modules therewith all represented in each bar statement of second intermediate language in the present embodiment.
Please refer to Figure 10, step S33 comprises step in the present embodiment:
S331 reads each node of AST tree, thereby obtains the information of each node.
S332 collects the relevant information of and function statement block among the AST, and stores.
S333 according to the function information of nodal information that reads and collection, checks that whether AST generates correct, in this way, then carry out step S334, otherwise system stops, the abnormality warnings of dishing out user.
S334 launches second intermediate language according to the nodal information that reads.
S335 exports second intermediate language.
In the present embodiment nodal information correspondence of the same type fixed transmission certain part of one or several second intermediate language or one second intermediate language.
Please refer to Figure 11, be converted in a kind of specific embodiment of the second corresponding intermediate language by AST in the present embodiment, node 1301 correspondences " SUB8 " of AST, node 1302 correspondences " port8@205 ", node 1303 correspondences " port8@177 ", node 1304 correspondences " port8@238 ", so the statement of second intermediate language of emission is:
M33：SUBB?port8@177，port8@238。
In the present embodiment because the language description abstraction hierarchy height of the 3rd intermediate language, being similar to higher level lanquage describes, and the language description abstraction hierarchy of second intermediate language is lower, more approaching modular digital circuit describes, and the functional module annexation of functional module and other modules therewith all represented in each bar statement of second intermediate language, therefore by the 3rd intermediate language is converted to the abstraction hierarchy that second intermediate language reduces system input file, so that system input file is converted to corresponding restructural operator array executable file in the back or relevant hardware is described.
S34 carries out comprehensive rear end with second intermediate language, generates first intermediate language, and carries out emulation.The description abstraction hierarchy of second intermediate language in the present embodiment though be lower than the 3rd intermediate language that is similar to higher level lanquage, can not be directly changed into hardware description language or restructural operator array executable file.Present embodiment promptly pass through to reduce the abstraction hierarchy of second intermediate language, thereby first intermediate language can be directly changed into hardware description language or restructural operator array by second intermediate language is converted to first intermediate language.
Please refer to Figure 12, present embodiment second intermediate language is carried out comprehensive rear end, generate first intermediate language and comprise step:
S341, the computing granularity of decomposing second intermediate language is to lower level.
S342 changes in second intermediate language functional module to first intermediate language, and function equivalent.
S343 inserts opposite communication unit.
In the present embodiment, because the abstraction hierarchy of describing in second intermediate language is higher, the communication mechanism that part of module connects can't directly be realized on hardware, therefore needs to add certain communication unit.
S344, the numbering of connection signal between modified module.
In the present embodiment, owing to added new communication unit, the form of second intermediate language can not be directly applied mechanically in the connection between each functional module, therefore, need the signal of being responsible for connecting between functional module be renumberd.
Please refer to Figure 13 a, among a kind of embodiment for this enforcement side, by traversal abstract syntax tree, the second intermediate language description document of generation.Please refer to Figure 13 b, for the second intermediate language description document to Figure 13 a is carried out comprehensive rear end, the 3rd intermediate language description document that obtains.Wherein, 16 add statement (promptly two sixteen bits are counted addition) in the second intermediate language description document of Figure 13 a: M1:AND 16port32@1, port32@2, port32@3 is through reducing its granularity, conversion is respectively for two 8 add statement in the description of the 3rd intermediate language: M1:AND port@1_1, port@2_1, port@3_1, M1:AND port@1_2, port@2_2, port@3_2; Wherein, because the statement in this second intermediate language description document: M3:-8CONU-16 port8@5, port6@6 can not directly split, it is carried out function equivalent is converted to the statement that the 3rd intermediate language describes and is: M3:BRD port@5_1, port@5_5, port@5_6, M3:OR port@5_5, port@6_3, port@6_1, M3:MOVI 127, port@6_4; Wherein, statement during the 3rd intermediate language is described: M4:BRD port@9_1, port@9_3 is the communication unit that inserts, thereby the port8@9 signal broadcasting in original second intermediate language has been become 2 signals, the data among the port8@9 can be used by multimode more.Please refer to Figure 13 a and Figure 13 b, certain variation has taken place in the signal numbering in the 3rd intermediate language of generation.
The annexation between a specific digital circuit structure and each digital circuit structure all represented in each bar statement in first intermediate language in the present embodiment.This specific digital circuit structure both can download on the restructural operator array by step S4a and step S5a and implement, perhaps by converting concrete digital circuit behind step S4b and the S5b to.
Please refer in Figure 14 embodiment and first intermediate language that generates to be carried out emulation comprise step:
S341, configuration analogue system operational factor when analogue system starts comprises that input treats the system description file of emulation, input emulated data file, output emulated data file, analogue system working time etc.
The system description file for the treatment of emulation in the present embodiment is by the first language description document.
S342 reads the system description file that emulation is treated in input, each submodule of describing in the generation system description document.
S343 is input to the data in the input emulated data file in the data storage container of system, waits for that each submodule starts, and these data promptly are released.
S344 is by reading the system description file that emulation is treated in input, all submodules that generated among the Connection Step S342.
S345 starts the operation of whole simulation, promptly starts all submodule work.
Output data described in the S346, output emulated data file is to specified file.
S4a is converted to restructural operator executable file with this first intermediate language, and execution in step S5a.
Please refer to Figure 15, the step S4a of present embodiment comprises step:
S4a1 carries out placement-and-routing according to first intermediate language on restructural operator array.
Carry out placement-and-routing in the present embodiment and comprise step:
S4a11 determines its enforcing location in restructural operator array according to the optional network specific digit circuit structure in every statement of this first intermediate language.
S4a12 again according to the annexation between each optional network specific digit circuit structure in each statement of first intermediate language, determines to finish the circuit resource situation that annexation consumed between each specific digital circuit structure.
Circuit resource in the present embodiment mainly refers to the hardware interconnection resources.
S4a2 carries out emulation and checking to the restructural operator array after the placement-and-routing;
S4a3 will be restructural operator executable file through the file conversion of the output after the checking, and download and implement.
S4b is converted to corresponding hardware description document, execution in step S5b with first intermediate language.
Each bar statement of first intermediate language in the present embodiment comprises function information and link information.
Please refer to Figure 16, present embodiment is converted to the hardware description file with first intermediate language and comprises step:
S4b1, converting system mainly reads two parts information from the input file of being described by first intermediate language.A part is the function information of each bar statement in first intermediate language; Another part is the link information of each bar statement in first intermediate language, i.e. the information of exchanges data path between statement.
S4b2 after reading function information, searches the hardware description language model bank, and the hardware description language that obtains corresponding function information is described.
S4b3, again in conjunction with link information, the hardware description language that can generate total system is described.
S5a, debugging restructural operator array, and execution in step S6.
S5b generates the corresponding digital circuit according to this hardware description file.
S6, the output result.
Please refer to Figure 17 a, among a kind of embodiment for present embodiment, by the comprehensive rear end of second intermediate language process, the selected parts of the first intermediate language description document of generation.Please refer to Figure 17 b, for first intermediate language shown in Figure 17 a being converted to the verilog behind the hardware description file.Wherein corresponding first intermediate language ADD module of functional module alu_operator u_alu_1 in the hardware description file and alu_operator u_alu_2 and NOT module, annexation in first intermediate language has been converted into reg signal and wire signal (seeing the beginning part of verilog program) in the hardware description file, finish the realization that is equal to the different hardware function of describing in the middle of first by two modules are imported different signals in the hardware description file.
Higher synthesis method of the present invention is by comprehensive first intermediate language that generates, generate corresponding restructural operator executable file or hardware description file by first intermediate language again, thereby output has multiobject characteristic, promptly both can to restructural operator array, implement the described system downloads of higher level lanquage input file, can go up enforcement to the described system downloads of input file to FPGA or ASIC by generating the hardware description file again by generating restructural operator array executable file.
On the other hand, higher synthesis method of the present invention, by senior input file being converted to the 3rd high intermediate language of abstraction hierarchy, be converted to the second lower intermediate language of abstraction hierarchy by the 3rd intermediate language again, this second intermediate language approaches modular digital circuit and describes, be converted to first intermediate language by this second intermediate language again, directly be converted to hardware description language or restructural operator array by this first intermediate language at last.The present invention adopts first intermediate language, second intermediate language and the 3rd intermediate language of the modularization idea intermediate representation form as transfer process, and description has the characteristic of certain functional module and the annexation and the correspondence of intermodule emphatically.This higher synthesis process is dispatched the described system of higher level lanquage input file by the annexation of modular character, intermodule and the communication mechanism of intermodule, thereby the restructural operator array configurations information that generates or digital circuit information is flexible, enforceability is high, and carry out the efficient height.
Above content be in conjunction with concrete embodiment to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (8)
1. the higher synthesis method of an integrated circuit is characterized in that, comprises step:
The higher level lanquage input file of digital circuit is described in input, and carries out the comprehensive constraint setting;
Higher level lanquage input file and comprehensive constraint according to described digital circuit generate first intermediate language, and the annexation between a specific digital circuit structure and each digital circuit structure represented in each bar statement of described first intermediate language;
Described first intermediate language is converted to restructural operator executable file, and be downloaded in the described restructural operator array and implement, perhaps described first intermediate language is converted to the corresponding hardware description document, and generates the corresponding digital circuit according to described hardware description file.
2. the method for claim 1 is characterized in that, generates described first intermediate language and comprises step:
The described higher level lanquage input file and the comprehensive constraint of input are carried out in advance comprehensively, generate the 3rd intermediate language, the principal function that described the 3rd intermediate language is served as reasons and had the statement block of list interface or have the nested statement piece formation of list interface;
Described the 3rd intermediate language is carried out comprehensive front-end, the comprehensive abstract syntax tree that generates, described abstract syntax tree comprise interface message and the described digital circuitry IO interface of input file information between the described statement block information of described higher level lanquage input file, the statement block;
Travel through described abstract syntax tree, and be converted to second intermediate language according to predetermined comprehensive strategic, the functional module annexation of functional module and other modules therewith all represented in each bar statement of described second intermediate language;
Described second intermediate language is carried out comprehensive rear end, generate first intermediate language, and carry out emulation.
3. method as claimed in claim 2, it is characterized in that described predetermined comprehensive strategic comprises hardware configuration, input file language format, the circuit resource usage policy of arithmetic speed, the power consumption of comprehensive back output system, the actual circuit area that uses, all kinds of circuit resource relative scale, target restructural operator array.
4. method as claimed in claim 2 is characterized in that described abstract syntax tree comprises root node; First node is used to store the input/output information of described higher level lanquage input file institute descriptive system; Section Point is used for storing the global variable of higher level lanquage input file or the claim information of array; The 3rd node is used for storing the information of all functions of higher level lanquage input file, and described first node, Section Point and the 3rd node all link to each other with described root node, then travels through described abstract syntax tree and generates described second intermediate language and comprise step:
Read each node of abstract syntax tree, obtain the information of each node;
Collect the relevant information of and function statement block in the abstract syntax tree, and storage;
According to described nodal information and function information, check whether described abstract syntax tree generates correct, in this way, then launch second intermediate language according to the nodal information that reads.
5. method as claimed in claim 2 is characterized in that, described first intermediate language is carried out emulation comprise step:
Configuration analogue system operational factor when analogue system starts comprises that input treats first intermediate language of emulation, input emulated data file, output emulated data file, analogue system working time etc.;
Read the system description file that first intermediate language of emulation is treated in input, each submodule of describing in the generation system description document;
Data in the input emulated data file are input in the data storage container of system, wait for that each submodule starts;
Read the system description file that emulation is treated in input, connect described all submodules that generate;
Start the operation of whole simulation, promptly start all submodule work;
Output data described in the output emulated data file is to specified file.
6. the method for claim 1 is characterized in that, described first intermediate language is converted to restructural operator executable file comprises step:
On restructural operator array, carry out placement-and-routing according to described first intermediate language;
Restructural operator array after the placement-and-routing is carried out emulation and checking;
To be restructural operator executable file through the file conversion of the output after the checking.
7. method as claimed in claim 6 is characterized in that, carries out placement-and-routing on the restructural operator array again according to described first intermediate language and comprises step:
Determine its enforcing location in restructural operator array according to the optional network specific digit circuit structure in every statement of described first intermediate language;
According to the annexation between each optional network specific digit circuit structure in each statement of described first intermediate language, determine to finish the circuit resource situation that annexation consumed between each specific digital circuit structure again.
8. the method for claim 1 is characterized in that, each bar statement of described first intermediate language comprises function information and link information, then described first intermediate language is converted to the relevant hardware description document and comprises step:
Mainly read the function information and the link information of described first intermediate language;
Search the hardware description language model bank according to described function information, obtain the relevant hardware descriptive language and describe;
In conjunction with described link information, generate relevant hardware descriptive language file.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106462431A (en) * | 2014-06-02 | 2017-02-22 | 赛灵思公司 | Extracting system architecture in high level synthesis |
| CN106775905A (en) * | 2016-11-19 | 2017-05-31 | 天津大学 | Higher synthesis based on FPGA realizes the method that Quasi-Newton algorithm accelerates |
| CN107179932A (en) * | 2017-05-26 | 2017-09-19 | 福建师范大学 | The optimization method and its system instructed based on FPGA High Level Synthesis |
| CN111460747A (en) * | 2020-04-10 | 2020-07-28 | 重庆百瑞互联电子技术有限公司 | Standard unit tracking method for integrated circuit design |
| CN112035397A (en) * | 2019-06-04 | 2020-12-04 | 三星电子株式会社 | Electronic system including FPGA and method of operating the same |
| WO2023130464A1 (en) * | 2022-01-10 | 2023-07-13 | 华为技术有限公司 | Method for designing circuit, electronic device, computer-readable storage medium, and program product |
| CN116663463A (en) * | 2023-07-27 | 2023-08-29 | 北京开源芯片研究院 | Circuit verification method and device, electronic equipment and readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0981605A (en) * | 1995-09-08 | 1997-03-28 | Nippon Telegr & Teleph Corp <Ntt> | Calculation method for arithmetic cost in high level synthesis and scheduling method |
| CN1501293A (en) * | 2002-10-22 | 2004-06-02 | 松下电器产业株式会社 | Advertisement effect analyzing method and advertising system |
| DE10338964A1 (en) * | 2003-08-25 | 2005-04-07 | Kuratorium Offis E.V. | Circuit design method using high level synthesis, involves dividing the circuit diagram into a number of syntactic and semantic elements and assigning classes to each element from a hierarchical class structure |
| US20050289499A1 (en) * | 2004-06-25 | 2005-12-29 | Matsushita Electric Industrial Co., Ltd. | High level synthesis method for semiconductor integrated circuit |
-
2011
- 2011-04-02 CN CN 201110084177 patent/CN102163248B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0981605A (en) * | 1995-09-08 | 1997-03-28 | Nippon Telegr & Teleph Corp <Ntt> | Calculation method for arithmetic cost in high level synthesis and scheduling method |
| CN1501293A (en) * | 2002-10-22 | 2004-06-02 | 松下电器产业株式会社 | Advertisement effect analyzing method and advertising system |
| DE10338964A1 (en) * | 2003-08-25 | 2005-04-07 | Kuratorium Offis E.V. | Circuit design method using high level synthesis, involves dividing the circuit diagram into a number of syntactic and semantic elements and assigning classes to each element from a hierarchical class structure |
| US20050289499A1 (en) * | 2004-06-25 | 2005-12-29 | Matsushita Electric Industrial Co., Ltd. | High level synthesis method for semiconductor integrated circuit |
Non-Patent Citations (1)
| Title |
|---|
| 《中国博士学位论文全文数据库(信息科技辑)》 20070915 沈英哲 可重构计算系统中软硬件代码划分技术研究 正文第9,32页、图1-8（a） 1 , * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106462431A (en) * | 2014-06-02 | 2017-02-22 | 赛灵思公司 | Extracting system architecture in high level synthesis |
| CN106775905A (en) * | 2016-11-19 | 2017-05-31 | 天津大学 | Higher synthesis based on FPGA realizes the method that Quasi-Newton algorithm accelerates |
| CN107179932A (en) * | 2017-05-26 | 2017-09-19 | 福建师范大学 | The optimization method and its system instructed based on FPGA High Level Synthesis |
| CN112035397A (en) * | 2019-06-04 | 2020-12-04 | 三星电子株式会社 | Electronic system including FPGA and method of operating the same |
| CN111460747A (en) * | 2020-04-10 | 2020-07-28 | 重庆百瑞互联电子技术有限公司 | Standard unit tracking method for integrated circuit design |
| CN111460747B (en) * | 2020-04-10 | 2023-03-31 | 重庆百瑞互联电子技术有限公司 | Standard unit tracking method for integrated circuit design |
| WO2023130464A1 (en) * | 2022-01-10 | 2023-07-13 | 华为技术有限公司 | Method for designing circuit, electronic device, computer-readable storage medium, and program product |
| CN116663463A (en) * | 2023-07-27 | 2023-08-29 | 北京开源芯片研究院 | Circuit verification method and device, electronic equipment and readable storage medium |
| CN116663463B (en) * | 2023-07-27 | 2023-11-10 | 北京开源芯片研究院 | Circuit verification method and device, electronic equipment and readable storage medium |
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