CN102158691A - System and method for monitoring by combining radio frequency identification with video shooting - Google Patents
System and method for monitoring by combining radio frequency identification with video shooting Download PDFInfo
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- CN102158691A CN102158691A CN2011101432850A CN201110143285A CN102158691A CN 102158691 A CN102158691 A CN 102158691A CN 2011101432850 A CN2011101432850 A CN 2011101432850A CN 201110143285 A CN201110143285 A CN 201110143285A CN 102158691 A CN102158691 A CN 102158691A
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Abstract
The invention belongs to the technique of intelligent monitoring device and discloses a system for monitoring by combining radio frequency identification with video shooting. The system comprises a radio frequency signal collector, a DSP (digital signal processor) processor, a storage, a camera, an A/D (analog to digital) conversion circuit, an ARM (advanced RISC machine) processor and a network chip, wherein the radio frequency signal collector is connected to the DSP processor, the ARM processor and the storage in turn; the camera is connected to the A/D conversion circuit, the ARM processor and the storage in turn; the DSP processor is singly arranged in the ARM processor; and the ARM processor is connected to the network chip. The invention also discloses a method for monitoring by combining radio frequency identification with video shooting. A complete real-time network monitoring system is formed by the highly integrated multimedia DSP processor and ARM processor. The device has two system functions of the radio frequency identification scanning system and video image monitoring system.
Description
Technical field
The present invention relates to the intelligent monitoring device technology, relate in particular to a kind of supervisory control system and method for supervising in conjunction with radio-frequency (RF) identification and video camera.
Background technology
Also there is not a kind of equipment in the prior art at present with radio RF recognition technology and intelligent video monitoring technology one, though REID and video camera technology play an important role in field separately respectively, and along with the continuous maturation of technology, the function of product is more and more perfect, and stability and accuracy rate are also all very high.But radio frequency identification can only be carried the electronic tag with unique identification coding to object and be carried out detailed scanning, and the electronic tag information of carrying out is read or writes; Under the situation of no image information display, apart from too far away or when having barrier to block, may cause and to read or to write label information, the just data message that radio frequency identification obtains and can't understand at that time field condition intuitively.Video monitoring system can be effectively capturing visual in real time, preserve image information captured for a long time, and monitoring image information carried out intellectual analysis and processing, but can't satisfy the high-accuracy characteristic of radio frequency identification.
Radio frequency identification of the prior art and intelligent video monitoring, the equipment that does not all have specific implementation two aspect technology to be integrated, in the scheme that both combine, RF acquisition equipment separates with video capture device, set up module separately, and independent operating in the different equipment of packing into, there is not contact each other, be actually the physical bond of radio frequency monitor system and video monitoring system.The weak point of this combination is that equipment cost is too high, and the project installation difficulty is bigger, and circuit is also complicated.
Summary of the invention
At the supervisory control system that the radio-frequency (RF) identification that exists in the prior art and video camera combine, two systems of radio-frequency (RF) identification and video camera are loaded into independent operating in the different equipment.This supervisory control system cost is too high, and has increased the installation difficulty of engineering and the complexity of circuit.
The invention discloses a kind of supervisory control system, comprise radiofrequency signal collector, dsp processor, memory, camera, A/D change-over circuit, arm processor, network chip in conjunction with radio-frequency (RF) identification and video camera; Described radiofrequency signal collector connects dsp processor, arm processor, memory in regular turn, described camera connects A/D change-over circuit, arm processor, memory in regular turn, built-in dsp processor is set separately in the described arm processor, and described arm processor connects network chip.
Preferably, above-mentioned radiofrequency signal collector is the radio-frequency (RF) tag scanner.
Preferably, above-mentioned radiofrequency signal collector is a card reader.
Preferably, above-mentioned memory comprises the memory DDR of stored video data and rf data, the memory SD of storage buffered data, the memory FLASH of storage control program.
Preferably, linking format modular converter between above-mentioned A/D change-over circuit and the arm processor.
Preferably, increase at least one buffer circuit between above-mentioned camera and the A/D change-over circuit, described camera connects buffer circuit, A/D change-over circuit in regular turn, at least increase a buffer circuit between described radiofrequency signal harvester and the dsp processor, this radiofrequency signal harvester connects buffer circuit, dsp processor in regular turn.
Preferably, above-mentioned DDR memory is two.
Preferably, in the above-mentioned built-in dsp processor double buffering buffer is set.
The invention also discloses a kind of method for supervising in conjunction with radio-frequency (RF) identification and video camera, it specifically comprises following steps: camera collection to picture signal decode through sending arm processor to behind the A/D change-over circuit, arm processor is decoded into 8 bit data, and decoded data are with byte form write memory line by line; Meanwhile, the radiofrequency signal collector sends the label information that scans to dsp processor, and the information after dsp processor will be handled is passed to arm processor and handled, and deposits information in memory after arm processor is handled; Arm processor is used for from the memory reading of data, data non-NULL in the memory is promptly read, export from interface by network chip with the code check of setting separately respectively after video data of reading and the rf data subpackage, according to data separation video packets of data and radio-frequency information bag, carry out the subpackage transmission in the transmission course.
Preferably, built-in dsp processor is set in the above-mentioned arm processor, the job step of described built-in dsp processor is as follows: begin to carry out the transmission of enhancement mode direct memory access after receiving the interrupt signal that arm processor sends, triggering the enhancement mode direct memory access after transmission is finished interrupts, in the break in service function, trigger soft interruption, in soft break in service function, carry out the compression of view data.
Preferably, in the above-mentioned built-in dsp processor double buffering buffer is set, carry out when being used to realize view data and information gathering, compression, transmission, at a buffer images acquired signal with when gathering radio-frequency information, dsp processor can compress the data in another buffer.
Preferably, above-mentioned radiofrequency signal and vision signal adopt alternant way to transmit.
Beneficial effect of the present invention is: adopt highly integrated multimedia dsp processor+arm processor to constitute complete real-time network monitoring system, this equipment has radio-frequency (RF) identification scanning and video frequency graphic monitoring two big systemic-functions, video that it has and radio frequency interface have been realized and Video Decoder and the seamless link of radio frequency decoder, circuit is stable, succinctly, low consumption, by in conjunction with two big systemic-functions, perfection of the present invention has remedied the intuitive difference and the low shortcoming of video frequency graphic monitoring warning accuracy rate of image in the radio-frequency (RF) identification scanning.
Description of drawings
Fig. 1 is the supervisory control system in conjunction with radio-frequency (RF) identification and video camera.
Fig. 2 is the specific implementation of ping-pong structure.
Fig. 3 is the workflow of dsp processor.
Fig. 4 adopts the load mode that transmits of mutual load mode for radiofrequency signal and vision signal.
Embodiment
Below in conjunction with Figure of description, describe the specific embodiment of the present invention in detail.
The supervisory control system in conjunction with radio-frequency (RF) identification and video camera of the present invention as shown in Figure 1, comprise radiofrequency signal collector, dsp processor, memory, camera, A/D change-over circuit, arm processor, network chip, above-mentioned radiofrequency signal collector connects dsp processor, arm processor, memory in regular turn, above-mentioned camera connects A/D change-over circuit, arm processor, memory in regular turn, dsp processor is set separately in the above-mentioned arm processor, and the back connects network chip.Above-mentioned radiofrequency signal collector is given dsp processor with the radio signal transmission that collects, and dsp processor is handled the radiofrequency signal that receives, and passes to arm processor after handling, and deposits information in memory after arm processor is handled.The image information that above-mentioned video signal collective device collects at first can become digital signal with analog signal conversion by the A/D change-over circuit, is transferred to arm processor then and decodes, and decoded data deposit memory in byte mode.
Camera collection to picture signal decode through sending arm processor to behind the A/D change-over circuit, arm processor can be decoded into 8 bit data, decoded data are with byte form write memory line by line, also can adopt the mode of efficient XML data parsing and metadata cache to import data, sending frame by arm processor control behind every partial data full frame interrupts to the built-in dsp processor that is provided with in the arm processor, built-in dsp processor starts internal electron buffer memory EDMA and reads in every frame data, is written to memory continuously after employing JPEG2000 mode is encoded.Meanwhile, above-mentioned radiofrequency signal collector, send the label information that scans to dsp processor as radio-frequency (RF) tag scanner or card reader etc., the information after dsp processor will be handled is passed to arm processor and is handled, and deposits information in memory after arm processor is handled.Above-mentioned memory comprises the memory DDR of stored video data and rf data, the memory SD of storage buffered data, the memory FLASH of storage control program.Wherein divide different address stored video data and rf data among the memory DDR respectively.
Arm processor is responsible for reading of data from memory, data non-NULL in the memory is promptly read, the buffer memory accumulation can not surpass 1 frame data, export from interface by network chip with the code check of setting separately respectively after video data of reading and the rf data subpackage, according to data separation video packets of data and radio-frequency information bag, carry out the subpackage transmission then in the transmission course.In the system, rf data bag code check is that the video packets of data code check is determined by factors such as audio stream, picture quality, maximum code stream and code stream quality by the decay of tag read distance correspondence decision.
Linking format modular converter between above-mentioned A/D change-over circuit and the arm processor, the LVDS conversion of signals that above-mentioned format converting module is used for video acquisition device output is the LVTTL standard signal, and the digital format signal with standard sends digital signal processor to then.
The electronic tag that has the unique identification coding is sent out primary information at regular intervals, the antenna scanning that has attenuator is passed to radio-frequency (RF) identification chip after this information, radio-frequency (RF) identification chip is amplified signal, down-conversion, filtering and decoding, by SPI decoded digital signal is sent to built-in dsp processor then, pass to built-in dsp processor by RS-232 again after dsp processor is handled information and carry out the breakpoint packing, spread out of by network chip then.
In IMAQ and radio frequency messages collection processing system implementing, the compression algorithm of built-in dsp processor is often unfixing on the realization time, but the acquisition module of front end is at the uniform velocity gathered image, can bring temporal asynchronous like this, asynchronous on the life period like this, the integrality of losing and influence frame data that might cause view data, in addition radio frequency reading to information time on may not conform to video information yet.For this reason, increase at least one buffer circuit between above-mentioned camera and the A/D change-over circuit, above-mentioned camera connects buffer circuit, A/D change-over circuit in regular turn, increase at least one buffer circuit between above-mentioned radiofrequency signal harvester and the dsp processor, above-mentioned radiofrequency signal harvester connects buffer circuit, dsp processor in regular turn, above-mentioned DDR memory is two, adopts ping-pong structure to realize the storage of vision signal and radiofrequency signal.The problem such as asynchronous that is increasing between the compression module that one or more buffer circuits can be on settling time.
Because ping-pong structure can use relatively cheap high-speed high capacity DDR memory, can realize the continuity of data simultaneously, so equipment adopts the buffering of the two DDR of ping-pong structure as video data and radio-frequency information.After the data of 1 two field picture all having been stored or a radio-frequency information bag finishes receiving, dsp processor utilizes the very short time directly 1 frame image data to be read in the memory feature again, and equipment is adopted the information that in the same way radio frequency is scanned and handled.So both can guarantee not lose pixel data and message source, and can reserve the how vacant time for dsp processor again, for carrying out image and information processing provides possibility in the back; Also can guarantee simultaneously the per 1 frame pixel data of dsp processor continuous acquisition and an ID radio-frequency information.Integrality for the ID message of the Frame realizing receiving and radio frequency reading, must guarantee that the priority of read data frame and message will be higher than the priority of write data frame, so the data input-output unit of equipment switches according to data and Message Processing flow process.
The specific implementation of ping-pong structure at first is divided into according to function as shown in Figure 2: S0, S1,4 transition statuses of S2, S3.Wherein, the S0 state is init state (all signals all is in init state), system power-up or reset after enter this state.The S1 state mainly is responsible for cannot carrying out read operation to the writing of DDR0 to DDR1 under this state.The S2 state mainly is responsible for DDR1 is carried out write operation, and DDR0 is carried out read operation; If DDR1 has write, and DDR0 does not run through, and then keeps this state, treats the S3 that gets the hang of after DDR0 runs through.State S3 mainly is responsible for DDR0 is carried out write operation, and DDR1 is carried out read operation; If DDR0 has write, and DDR1 does not run through, and then keeps this state, treats the S2 that gets the hang of after DDR1 runs through.
The work of built-in dsp processor specifically comprises following step as shown in Figure 3:
1.DSP external communication register and EDMA(enhancement mode direct memory access) related register carries out initialization;
2. begin to carry out the EDMA transmission after receiving the interrupt signal that arm processor sends, transmission is finished the back and is triggered EDMA and interrupt, and the compression of view data is carried out in 1 soft interruption of triggering in soft break in service function in the break in service function.Response down trigger EDMA transmission after external equipment and the initialization of EDMA related register are finished, native system transmits by interrupting rising edge triggering EDMA, about the process need 10ms of whole EDMA transmission.In the workflow of dsp processor, if carry out when will realize view data and information gathering, compression, transmission, dsp processor needs a double buffering buffer; When being certain buffer images acquired signal and collection radio-frequency information, dsp processor can compress the data in another buffer.
Can realize this function by EDMA ping pong mode.In dsp processor, use hEdmaPing and hEdmaPong binary channels EDMA and set up the Ping buffer and two data memory blocks of Pong buffer.When having write a two field picture and having received a radio-frequency information bag, ARM sends interrupt signal startup hEdmaPing data and information is moved the Ping buffer, simultaneously passage is linked to hEdmaPong.When next interrupt event takes place data and information are moved in the Pong buffer, CPU finishes link hEdmaPing passage in the interrupt service routine at the hEdmaPong passage.And so forth, making system data and information move and handle continuously carries out.
Among the present invention, radiofrequency signal and vision signal adopt alternant way to transmit, its particular content as shown in Figure 4, VD is a frame synchronizing signal, level mode, high level is effective; HD is a line synchronizing signal, pulse mode, and rising edge is effective; PCLK is the pixel synchronised clock, pulse mode; DATA is the 10bit view data, releases at the trailing edge of PCLK, and receiving terminal is gathered at the PCLK rising edge, and PCLK is a regular operation mode.FD is the radio frequency acquisition of information, and high level is effective, when the frame synchronizing signal of certain number of times occurring, the FD signal occurs one time, finishes in the cycle at one time to guarantee FD signal and VD signal.480 HD useful signals are arranged in each VD term of validity, when the 0th ~ 478 HD is effective, there are 600 effective view data each HD valid period, when the 479th HD (being last 1 row of every frame) is effective, preceding 600 DATA are effective view data, the FD data also are effective information simultaneously, reserve 6 byte output image relevant informations and radio frequency relevant information behind 600 DATA, and promptly the D600 ~ D605 is a reserved byte.
The present invention is not limited to aforesaid embodiment.The present invention can expand to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.
Claims (10)
1. the supervisory control system in conjunction with radio-frequency (RF) identification and video camera is characterized in that comprising radiofrequency signal collector, dsp processor, memory, camera, A/D change-over circuit, arm processor, network chip; Described radiofrequency signal collector connects dsp processor, arm processor, memory in regular turn, described camera connects A/D change-over circuit, arm processor, memory in regular turn, built-in dsp processor is set separately in the described arm processor, and described arm processor connects network chip.
2. supervisory control system as claimed in claim 1 is characterized in that described memory comprises the memory DDR of stored video data and rf data, the memory SD of storage buffered data, the memory FLASH of storage control program.
3. supervisory control system as claimed in claim 2 is characterized in that linking format modular converter between described A/D change-over circuit and the arm processor.
4. supervisory control system as claimed in claim 3, it is characterized in that increasing between described camera and the A/D change-over circuit at least one buffer circuit, described camera connects buffer circuit, A/D change-over circuit in regular turn, at least increase a buffer circuit between described radiofrequency signal harvester and the dsp processor, this radiofrequency signal harvester connects buffer circuit, dsp processor in regular turn.
5. supervisory control system as claimed in claim 4 is characterized in that described DDR memory is two.
6. supervisory control system as claimed in claim 5 is characterized in that in the described built-in dsp processor double buffering buffer being set.
7. method for supervising in conjunction with radio-frequency (RF) identification and video camera, it specifically comprises following steps: camera collection to picture signal decode through sending arm processor to behind the A/D change-over circuit, arm processor is decoded into 8 bit data, and decoded data are with byte form write memory line by line; Meanwhile, the radiofrequency signal collector sends the label information that scans to dsp processor, and the information after dsp processor will be handled is passed to arm processor and handled, and deposits information in memory after arm processor is handled; Arm processor is used for from the memory reading of data, data non-NULL in the memory is promptly read, export from interface by network chip with the code check of setting separately respectively after video data of reading and the rf data subpackage, according to data separation video packets of data and radio-frequency information bag, carry out the subpackage transmission in the transmission course.
8. method for supervising as claimed in claim 7, it is characterized in that being provided with in the described arm processor built-in dsp processor, the job step of described built-in dsp processor is as follows: begin to carry out the transmission of enhancement mode direct memory access after receiving the interrupt signal that arm processor sends, triggering the enhancement mode direct memory access after transmission is finished interrupts, in the break in service function, trigger soft interruption, in soft break in service function, carry out the compression of view data.
9. method for supervising as claimed in claim 8, its special this is in the described built-in dsp processor double buffering buffer to be set, carry out when being used to realize view data and information gathering, compression, transmission, at a buffer images acquired signal with when gathering radio-frequency information, dsp processor compresses the data in another buffer.
10. method for supervising as claimed in claim 9 is characterized in that described radiofrequency signal and vision signal adopt alternant way to transmit.
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