CN102157383A - Manufacturing method of SOI (Silicon On Insulator) nLDMOS (n Laterally Diffused Metal Oxide Semiconductor) device unit with P buried layer - Google Patents
Manufacturing method of SOI (Silicon On Insulator) nLDMOS (n Laterally Diffused Metal Oxide Semiconductor) device unit with P buried layer Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 63
- 239000010703 silicon Substances 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000012212 insulator Substances 0.000 title abstract description 4
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000001259 photo etching Methods 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 40
- 229920005591 polysilicon Polymers 0.000 claims description 40
- 239000003518 caustics Substances 0.000 claims description 36
- 239000000243 solution Substances 0.000 claims description 36
- 230000003647 oxidation Effects 0.000 claims description 22
- 238000007254 oxidation reaction Methods 0.000 claims description 22
- 150000002500 ions Chemical class 0.000 claims description 21
- 230000003139 buffering effect Effects 0.000 claims description 20
- 229910000679 solder Inorganic materials 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 17
- 238000002347 injection Methods 0.000 claims description 17
- 239000007924 injection Substances 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 238000004151 rapid thermal annealing Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000012190 activator Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 238000001771 vacuum deposition Methods 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- -1 phosphonium ion Chemical class 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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Abstract
The invention relates to a manufacturing method of an SOI (Silicon On Insulator) nLDMOS (n Laterally Diffused Metal Oxide Semiconductor) device unit with a P buried layer. An SOI nLDMOS device manufactured by the traditional method seriously influences the voltage withstanding property of the SOI nLDMOS device and influences the heat radiation of the SOI nLDMOS device. The SOI nLDMOS device with the P buried layer is manufactured by carrying out photoetching on an SOI thick film material with the P buried layer for nine times. The manufactured SOI nLDMOS device bears the vast majority of withstand voltages through a depletion layer formed by a reverse biased PN junction positioned between an N type top silicon film and a P type buried layer when the voltages of a blocking-state drain electrode are increased, thereby enhancing the longitudinal voltage withstanding property of the SOI nLDMOS device and breaking the bottleneck of limiting the improvement of horizontal withstand voltages due to over-low longitudinal withstand voltages; and in addition, the thin buried oxide layer is beneficial to the heat radiation of the SOI nLDMOS device, thereby effectively reducing the self-heating effect. The manufacturing method ensures that electrical and thermal properties of the SOI nLDMOS device integrating power and radio frequency are remarkably improved, and is beneficial to saving of the resources and the energy and protecting of the environment.
Description
Technical field
The invention belongs to technical field of semiconductors, relate to a kind of SOI(semiconductor on insulator of the P of having buried regions) the laterally two metal-oxide semiconductor fieldeffect transistors that inject of nLDMOS(n type) the SOI(semiconductor on insulator of device cell) the CMOS(complementary metal-oxide-semiconductor) the VLSI(very lagre scale integrated circuit (VLSIC)) and integrated manufacturing method.
Background technology
SOI nLDMOS device is because its smaller volume and weight, very high operating frequency, higher working temperature and stronger anti-irradiation ability, lower cost and higher reliability, has extensive use as contactless power electronic switching, analog line driver or RF power amplifying transistor in intelligent electric power electronics, hot environment power electronics, space power electronics, vehicles power electronics, military affairs and technical field such as communicate by letter.SOI CMOS VLSI technology because its technical maturity height, dielectric isolation performance are good, isolation technology is simple, be convenient to three-dimensional integrated, be convenient to micro photo-electro-mechanical and power and radio frequency monolithic system integrated, be convenient to improve advantages such as integration density and integrated performance, make at VLSI, SOC(monolithic integrated system) make, the SPIC(smart-power IC) make and TDIS(three-dimensional integrated system) field such as manufacturing has extensive use.Do not have P buried regions district between existing SOI nLDMOS device light dope drift region and the buried oxidation layer, device can pass through SOI CMOS VLSI fabrication techniques, and its process is as follows:
1. choose polished SOI disk as original material, this SOI disk is isolated into two semiconductor regions fully by buried insulating barrier, in two semiconductor regions thick one be the P type as substrate, thin one is used to make device and circuit for the N type as top silicon surface;
2. the upper surface with exposed top silicon surface carries out the oxidation first time, and oxidated layer thickness is 50～100nm, adopts caustic solution to carry out the etching first time, and the oxide layer of removing the top silicon surface surface is to eliminate mechanical damage, cleaning, drying; Exposed silicon face is carried out the oxidation second time, and thickness is the oxide layer of 300～500nm, utilizes the active area mask of design to carry out the photoetching first time, adopts caustic solution to remove exposed oxide layer; Exposed top silicon surface is carried out oxidation for the third time, and the partial oxidation layer will be as gate dielectric layer;
3. adopt chemical vapor deposition (CVD) method to carry out the polysilicon deposit and form polysilicon gate, polysilicon is carried out the heavy doping of N type, carry out high annealing, foreign ion is evenly distributed in polysilicon by ion injection method; Utilize the polysilicon gate mask of design to carry out the photoetching second time, adopt caustic solution to remove exposed polysilicon;
4. the upper surface to top silicon surface adopts spin coating tetraethyl orthosilicate (TEOS) method to carry out the 4th oxidation, adopts the P trap doping mask of design to carry out photoetching for the third time, adopts caustic solution to remove exposed oxide layer and forms P trap doping window; Adopt ion injection method to carry out the doping of P trap and form semiconductor region---P well region opposite with the top silicon surface doping type and that doping content is more much higher than top silicon surface impurity concentration; Adopt caustic solution to remove photoresist then, clean oven dry;
5. utilize the buffering area doping mask of design that exposed oxide layer is carried out the 4th photoetching then, carve and remove exposed oxide layer, form buffering area doping window, mix N type impurity by ion injection method in buffering area doping window, the top silicon surface of the N type that the mixes impurity in the buffering area doping window is as buffering area; The top silicon surface surface oxide layer is all removed, cleaned oven dry;
6. the P trap ohmic contact doping mask of employing design is carried out the 5th photoetching to the upper surface of top silicon surface, in the P well region, form P trap ohmic contact doping window, adopt ion injection method to mix p type impurity then and form the heavy doping P trap ohmic contact regions identical with P trap doping type, adopt caustic solution to remove photoresist, clean oven dry; Carry out high annealing then to recover the perfection of lattice and the activator impurity atom of P well region and P trap ohmic contact regions;
7. the source region of employing design and drain region doping mask are carried out the 6th photoetching to the upper surface of top silicon surface, adopt caustic solution to remove exposed oxide layer and in P well region and N type resilient coating, form source region and drain region doping window respectively, adopt ion injection method to carry out source region N type heavy doping, adopt caustic solution to remove photoresist, carry out rapid thermal annealing (RTA) then and form N type heavy doping source region;
8. the contact conductor contact hole mask of employing design is carried out the 7th photoetching to the upper surface of top silicon surface, heavily doped polysilicon gate regions trench wall and above form grid and grid field field plate electrode window, form source electrode and source field plate electrode window at N type heavy doping source region and P trap ohmic contact regions and according to reducing the field oxide upper surface that the surface field rule covers next-door neighbour P trap ohmic contact regions, above heavily doped drain region and according to reducing the field oxide upper surface that the surface field rule covers next-door neighbour's heavily doped drain region, form drain electrode and leak the field plate electrode window; Adopt vacuum coating method to carry out the metallic film deposit then on the surface of whole silicon wafer, and adopt contact conductor, metal field plate, metal interconnecting wires and the metal crimp solder joint mask of design to carry out the 8th photoetching, adopt caustic solution to remove exposed metal and form metal electrode lead-in wire, metal field plate, metal interconnecting wires and metal crimp solder joint;
9. at upper surface deposit insulating passivation layer, adopt the metal crimp solder joint contact mask of design to carry out the 9th photoetching, carve and remove exposed insulating passivation layer, remove photoresist, clean oven dry, above the metal crimp solder joint, etch metal crimp solder joint window, be used to carry out pin pressure welding and encapsulation.
The SOI nLDMOS device that this method is made is when drain electrode adds high voltage; since buried oxidation layer to exist substrate not participate in withstand voltage; had a strong impact on the withstand voltage properties of device; and thick oxygen buried layer has influenced the heat radiation of device; the device inefficiency; easily heating is unfavorable for improving device and system reliability, the saving energy and protection environment.
Summary of the invention
The object of the invention is at the deficiencies in the prior art, provide a kind of and adopt advanced SOI CMOS technology to have the manufacture method of the SOI nLDMOS device cell of P buried regions, thereby help to realize having the SOI nLDMOS device of P buried regions in conjunction with New type of S OI material with P buried regions.
The inventive method concrete steps are:
1. choose polished thick film SOI disk as original material, this thick film SOI disk order from the bottom to top comprises P type semiconductor substrate, thin buried oxidation layer, p type buried layer district and N type top silicon surface, isolate P type semiconductor substrate and p type buried layer district fully by thin buried insulating barrier, thin one is covered on the p type buried layer district for N type top layer silicon, is used to make device and circuit;
2. the upper surface with exposed top silicon surface carries out the oxidation first time, and oxidated layer thickness is 50～100nm, adopts caustic solution to carry out the etching first time, and the oxide layer of removing the top silicon surface surface is to eliminate mechanical damage, cleaning, drying; Exposed silicon face is carried out the oxidation second time, and oxidated layer thickness is 300～500nm;
3. utilize the buffering area doping mask of design that exposed oxide layer is carried out the photoetching first time, form buffering area doping window, in buffering area doping window, mix N type impurity by high energy phosphonium ion method for implanting, and high annealing, the N type district that formation is higher than top silicon surface concentration, the N type top silicon surface zone that concentration is higher in the buffering area doping window is as buffering area;
4. utilize the active area mask of design to carry out the photoetching second time, adopt caustic solution to remove exposed oxide layer, the oxide layer that remains is as field oxide; Exposed top silicon surface is carried out oxidation for the third time; Adopt chemical vapor deposition (CVD) method to carry out the polysilicon deposit and form polysilicon gate and grid field plate, polysilicon is carried out the heavy doping of N type, carry out high annealing, foreign ion is evenly distributed in polysilicon by ion injection method; Utilize the polysilicon gate and the grid field plate mask of design to carry out photoetching for the third time, adopt caustic solution to remove the exposed polysilicon and the silicon dioxide of active area successively, the polysilicon layer that remains is as polysilicon gate and grid field plate, and the thin oxide layer district that polysilicon gate and grid field plate cover is that gate oxide, thick oxide layer are the part of field oxide;
5. the upper surface to top silicon surface adopts spin coating tetraethyl orthosilicate (TEOS) method to carry out the 4th oxidation, adopt the P trap doping mask of design to carry out the 4th photoetching, adopt caustic solution to remove the abutment wall oxide layer that exposed oxide layer forms P trap doping window and covers polysilicon gate and grid field plate; Adopt ion injection method to carry out the doping of P trap and form semiconductor region-P well region opposite with the top silicon surface doping type and that doping content is more much higher than top silicon surface impurity concentration; Adopt caustic solution to remove photoresist then, clean oven dry;
6. the P trap ohmic contact doping mask of employing design is carried out the 5th photoetching to the upper surface of top silicon surface, in the P well region, form P trap ohmic contact doping window, adopt ion injection method to mix p type impurity then and form the heavy doping P trap ohmic contact regions identical with P trap doping type, adopt caustic solution to remove photoresist, clean oven dry; Carry out high annealing then to recover the perfection of lattice and the activator impurity atom of P well region and P trap ohmic contact regions;
7. the source region of employing design and drain region doping mask are carried out the 6th photoetching to the upper surface of top silicon surface, adopt caustic solution to remove exposed oxide layer and in P well region and N type resilient coating, form source region and drain region doping window respectively, adopt ion injection method to carry out source region and drain region N type heavy doping, adopt caustic solution to remove photoresist, carry out rapid thermal annealing (RTA) then and form N type heavy doping source region and drain region;
8. the contact conductor contact hole mask of employing design is carried out the 7th photoetching to the upper surface of top silicon surface, above the heavily doped polysilicon gate regions, form grid and grid field field plate electrode window, form the source electrode window through ray in N type heavy doping source region and P trap ohmic contact regions upper surface, above heavy doping N type drain region and according to the field oxide upper surface that reduces surface field rule covering next-door neighbour heavily doped drain region, form drain electrode and leak the field plate electrode window; Adopt vacuum coating method to carry out the metallic film deposit then on the surface of whole silicon wafer, and adopt contact conductor, metal field plate, metal interconnecting wires and the metal crimp solder joint mask of design to carry out the 8th photoetching, adopt caustic solution to remove exposed metal and form metal electrode lead-in wire, metal field plate, metal interconnecting wires and metal crimp solder joint;
9. at upper surface deposit insulating passivation layer, adopt the metal crimp solder joint contact mask of design to carry out the 9th photoetching, carve and remove exposed insulating passivation layer, remove photoresist, clean oven dry, above the metal crimp solder joint, etch metal crimp solder joint window, be used to carry out pin pressure welding and encapsulation.
The inventive method is convenient to adopt existing SOI CMOS VLSI technology to realize having the integrated power and the radio frequency SOI NLDMOS device of excellent electricity and thermal property, has slightly at process complexity and technology cost the electricity and the thermal property of integrated power and radio frequency SOI nLDMOS device are significantly improved.
The SOI nLDMOS device cell with P buried regions that the inventive method is made is when drain electrode adds high voltage, the formed depletion layer of reverse bias PN junction between N type top silicon surface and the p type buried layer will bear most longitudinal voliages, thereby improved vertical withstand voltage properties of device, for further improving the laterally withstand voltage space of having expanded greatly of device; Bao oxygen buried layer helps the heat radiation of device simultaneously, has effectively alleviated self-heating effect, has improved the operating efficiency of device, thermoelectric reliability and the operating ambient temperature upper limit.This device architecture helps improving the Performance And Reliability of device, circuit and system, helps saving resource, the energy and protection environment.
Embodiment
Have the manufacture method of the SOI nLDMOS device cell of P buried regions, specifically may further comprise the steps:
1. choose polished thick film SOI disk as original material, this thick film SOI disk order from the bottom to top comprises P type semiconductor substrate, thin buried oxidation layer, p type buried layer district and N type top silicon surface, isolate P type semiconductor substrate and p type buried layer district fully by thin buried insulating barrier, thin one is covered on the p type buried layer district for N type top layer silicon, is used to make device and circuit;
2. the upper surface with exposed top silicon surface carries out the oxidation first time, and oxidated layer thickness is 50～100nm, adopts caustic solution to carry out the etching first time, and the oxide layer of removing the top silicon surface surface is to eliminate mechanical damage, cleaning, drying; Exposed silicon face is carried out the oxidation second time, and oxidated layer thickness is 300～500nm;
3. utilize the buffering area doping mask of design that exposed oxide layer is carried out the photoetching first time, form buffering area doping window, in buffering area doping window, mix N type impurity by high energy phosphonium ion method for implanting, and high annealing, the N type district that formation is higher than top silicon surface concentration, the N type top silicon surface zone that concentration is higher in the buffering area doping window is as buffering area;
4. utilize the active area mask of design to carry out the photoetching second time, adopt caustic solution to remove exposed oxide layer, the oxide layer that remains is as field oxide; Exposed top silicon surface is carried out oxidation for the third time; Adopt chemical vapor deposition (CVD) method to carry out the polysilicon deposit and form polysilicon gate and grid field plate, polysilicon is carried out the heavy doping of N type, carry out high annealing, foreign ion is evenly distributed in polysilicon by ion injection method; Utilize the polysilicon gate and the grid field plate mask of design to carry out photoetching for the third time, adopt caustic solution to remove the exposed polysilicon and the silicon dioxide of active area successively, the polysilicon layer that remains is as polysilicon gate and grid field plate, and the thin oxide layer district that polysilicon gate and grid field plate cover is that gate oxide, thick oxide layer are the part of field oxide;
5. the upper surface to top silicon surface adopts spin coating tetraethyl orthosilicate (TEOS) method to carry out the 4th oxidation, adopt the P trap doping mask of design to carry out the 4th photoetching, adopt caustic solution to remove the abutment wall oxide layer that exposed oxide layer forms P trap doping window and covers polysilicon gate and grid field plate; Adopt ion injection method to carry out the doping of P trap and form semiconductor region-P well region opposite with the top silicon surface doping type and that doping content is more much higher than top silicon surface impurity concentration; Adopt caustic solution to remove photoresist then, clean oven dry;
6. the P trap ohmic contact doping mask of employing design is carried out the 5th photoetching to the upper surface of top silicon surface, in the P well region, form P trap ohmic contact doping window, adopt ion injection method to mix p type impurity then and form the heavy doping P trap ohmic contact regions identical with P trap doping type, adopt caustic solution to remove photoresist, clean oven dry; Carry out high annealing then to recover the perfection of lattice and the activator impurity atom of P well region and P trap ohmic contact regions;
7. the source region of employing design and drain region doping mask are carried out the 6th photoetching to the upper surface of top silicon surface, adopt caustic solution to remove exposed oxide layer and in P well region and N type resilient coating, form source region and drain region doping window respectively, adopt ion injection method to carry out source region and drain region N type heavy doping, adopt caustic solution to remove photoresist, carry out rapid thermal annealing (RTA) then and form N type heavy doping source region and drain region;
8. the contact conductor contact hole mask of employing design is carried out the 7th photoetching to the upper surface of top silicon surface, above the heavily doped polysilicon gate regions, form grid and grid field field plate electrode window, form the source electrode window through ray in N type heavy doping source region and P trap ohmic contact regions upper surface, above heavy doping N type drain region and according to the field oxide upper surface that reduces surface field rule covering next-door neighbour heavily doped drain region, form drain electrode and leak the field plate electrode window; Adopt vacuum coating method to carry out the metallic film deposit then on the surface of whole silicon wafer, and adopt contact conductor, metal field plate, metal interconnecting wires and the metal crimp solder joint mask of design to carry out the 8th photoetching, adopt caustic solution to remove exposed metal and form metal electrode lead-in wire, metal field plate, metal interconnecting wires and metal crimp solder joint;
9. at upper surface deposit insulating passivation layer, adopt the metal crimp solder joint contact mask of design to carry out the 9th photoetching, carve and remove exposed insulating passivation layer, remove photoresist, clean oven dry, above the metal crimp solder joint, etch metal crimp solder joint window, be used to carry out pin pressure welding and encapsulation.
Claims (1)
1. have the manufacture method of the SOI nLDMOS device cell of P buried regions, it is characterized in that the concrete steps of this method are:
Step (1) is chosen polished thick film SOI disk as original material, this thick film SOI disk order from the bottom to top comprises P type semiconductor substrate, thin buried oxidation layer, p type buried layer district and N type top silicon surface, isolate P type semiconductor substrate and p type buried layer district fully by thin buried insulating barrier, thin one is covered on the p type buried layer district for N type top layer silicon, is used to make device and circuit;
Step (2) is carried out the oxidation first time with the upper surface of exposed top silicon surface, and oxidated layer thickness is 50～100nm, adopts caustic solution to carry out the etching first time, and the oxide layer of removing the top silicon surface surface is to eliminate mechanical damage, cleaning, drying; Exposed silicon face is carried out the oxidation second time, and oxidated layer thickness is 300～500nm;
Step (3) utilizes the buffering area doping mask of design that exposed oxide layer is carried out the photoetching first time, form buffering area doping window, in buffering area doping window, mix N type impurity by high energy phosphonium ion method for implanting, and high annealing, the N type district that formation is higher than top silicon surface concentration, the N type top silicon surface zone that concentration is higher in the buffering area doping window is as buffering area;
Step (4) utilizes the active area mask of design to carry out the photoetching second time, adopts caustic solution to remove exposed oxide layer, and the oxide layer that remains is as field oxide; Exposed top silicon surface is carried out oxidation for the third time; Adopt chemical gas-phase deposition method to carry out the polysilicon deposit and form polysilicon gate and grid field plate, polysilicon is carried out the heavy doping of N type, carry out high annealing, foreign ion is evenly distributed in polysilicon by ion injection method; Utilize the polysilicon gate and the grid field plate mask of design to carry out photoetching for the third time, adopt caustic solution to remove the exposed polysilicon and the silicon dioxide of active area successively, the polysilicon layer that remains is as polysilicon gate and grid field plate, and the thin oxide layer district that polysilicon gate and grid field plate cover is that gate oxide, thick oxide layer are the part of field oxide;
Step (5) adopts spin coating tetraethyl orthosilicate method to carry out the 4th oxidation to the upper surface of top silicon surface, adopt the P trap doping mask of design to carry out the 4th photoetching, adopt caustic solution to remove the abutment wall oxide layer that exposed oxide layer forms P trap doping window and covers polysilicon gate and grid field plate; Adopt ion injection method to carry out the doping of P trap and form semiconductor region-P well region opposite with the top silicon surface doping type and that doping content is more much higher than top silicon surface impurity concentration; Adopt caustic solution to remove photoresist then, clean oven dry;
The P trap ohmic contact doping mask of step (6) employing design is carried out the 5th photoetching to the upper surface of top silicon surface, in the P well region, form P trap ohmic contact doping window, adopt ion injection method to mix p type impurity then and form the heavy doping P trap ohmic contact regions identical with P trap doping type, adopt caustic solution to remove photoresist, clean oven dry; Carry out high annealing then to recover the perfection of lattice and the activator impurity atom of P well region and P trap ohmic contact regions;
The source region of step (7) employing design and drain region doping mask are carried out the 6th photoetching to the upper surface of top silicon surface, adopt caustic solution to remove exposed oxide layer and in P well region and N type resilient coating, form source region and drain region doping window respectively, adopt ion injection method to carry out source region and drain region N type heavy doping, adopt caustic solution to remove photoresist, carry out rapid thermal annealing then and form N type heavy doping source region and drain region;
The contact conductor contact hole mask of step (8) employing design is carried out the 7th photoetching to the upper surface of top silicon surface, above the heavily doped polysilicon gate regions, form grid and grid field field plate electrode window, form the source electrode window through ray in N type heavy doping source region and P trap ohmic contact regions upper surface, above heavy doping N type drain region and according to the field oxide upper surface that reduces surface field rule covering next-door neighbour heavily doped drain region, form drain electrode and leak the field plate electrode window; Adopt vacuum coating method to carry out the metallic film deposit then on the surface of whole silicon wafer, and adopt contact conductor, metal field plate, metal interconnecting wires and the metal crimp solder joint mask of design to carry out the 8th photoetching, adopt caustic solution to remove exposed metal and form metal electrode lead-in wire, metal field plate, metal interconnecting wires and metal crimp solder joint;
Step (9) adopts the metal crimp solder joint contact mask of design to carry out the 9th photoetching at upper surface deposit insulating passivation layer, carves and removes exposed insulating passivation layer, remove photoresist, clean oven dry, above the metal crimp solder joint, etch metal crimp solder joint window, be used to carry out pin pressure welding and encapsulation.
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| CN201110056312A CN102157383B (en) | 2011-03-10 | 2011-03-10 | Manufacturing method of SOI (Silicon On Insulator) nLDMOS (n Laterally Diffused Metal Oxide Semiconductor) device unit with P buried layer |
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| CN201110056312A CN102157383B (en) | 2011-03-10 | 2011-03-10 | Manufacturing method of SOI (Silicon On Insulator) nLDMOS (n Laterally Diffused Metal Oxide Semiconductor) device unit with P buried layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
| CN101964344A (en) * | 2009-06-19 | 2011-02-02 | 东南大学 | Panel display driving chip based on silicon on insulator (SOI) and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
| CN101964344A (en) * | 2009-06-19 | 2011-02-02 | 东南大学 | Panel display driving chip based on silicon on insulator (SOI) and preparation method thereof |
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