CN102136837B

CN102136837B - LVDS (Low Voltage Differential Signaling) driver

Info

Publication number: CN102136837B
Application number: CN2010105999095A
Authority: CN
Inventors: 蔡化; 岑远军; 朱志勇; 张克林
Original assignee: CHENGDU SINO MICROELECTRONICS TECHNOLOGY Co Ltd
Current assignee: Chengdu Hua Microelectronics Technology Co.,Ltd.
Priority date: 2010-12-22
Filing date: 2010-12-22
Publication date: 2012-11-21
Anticipated expiration: 2030-12-22
Also published as: CN102136837A

Abstract

The invention relates to an LVDS (Low Voltage Differential Signaling) driver, relating to electronic technologies. The LVDS driver comprises an input cache unit and a drive unit. The LVDS driver is characterized by also comprising a charge and discharge control unit, wherein the charge and discharge control unit comprises a voltage difference/current difference converting unit, a current comparing unit, a control logic unit and a charging and discharging unit; the current comparing unit is connected with the input cache unit through the voltage difference/current difference converting unit; the control logic unit is connected with the current comparing unit and is also connected with the control end of the charging and discharging unit; and the output end of the charging and discharging unit is connected with the output end of the input cache unit. The invention has the advantages of reducing the grid voltage deviation of a driving circuit and realizing dynamic stabilization.

Description

Lvds driver

Technical field

The present invention relates to electronic technology, particularly integrated circuit technique.

Background technology

Prior art is as shown in Figure 1, and when D1 is " low ", when D1b was " height ", N3 turn-offed, the N4 conducting; Switch S 2 is broken off, and the S1 closure is received on the grid of P1 Buffer output Vb2, makes P1 be in normal operating conditions, its grid voltage Vb2=Vb.And because the effect of Co, the last grid voltage of P2 is that VC turn-offs P2.The 3.5mA electric current will flow through the LVDS signal that terminal resistance Rt produces standard like this, and the grid voltage VCM that output common mode voltage is adjusted Ns by common mode feedback circuit reaches stable, and its value is about 1.2V.When D1 is " height ", opposite with above-mentioned situation when D1b is " low ", N3 and the conducting of P2 pipe make the current reversal that flows through Rt.

But under high frequency situations, when switch P 2 converted conducting into by shutoff, S1 broke off, and the S2 closure makes P2 be in the normal bias state, this moment the P2 grid voltage will change Vb2 immediately into by VC.Because Buffer has certain setting up the response time, can not in time respond this instantaneous conversion; In addition, switch S 1/S2 goes up in the raceway groove unnecessary electric charge and will inject the Buffer output its output is changed.Operating frequency is high more; The influence of above-mentioned effect is obvious more, and the last voltage of D2/D2b will constantly rise, because the P1/P2 grid voltage is directly proportional with the square root of its drain current; Then the change by grid voltage can produce bigger peak current, and this electric current will make output produce obvious deformation through terminal resistance Rt.

Summary of the invention

Technical problem to be solved by this invention is that a kind of lvds driver that can reduce the grid voltage deviation is provided.

The technical scheme that the present invention solve the technical problem employing is; Lvds driver; Comprise input-buffer unit and driver element; It is characterized in that, also comprise discharging and recharging control unit that the said control unit that discharges and recharges comprises voltage difference/difference between current converting unit, electric current comparing unit, control logic unit and charge/discharge unit; The electric current comparing unit is connected with the input-buffer unit through voltage difference/difference between current converting unit; The control logic unit is connected with the electric current comparing unit, and is connected with the control end of charge/discharge unit; The output of charge/discharge unit is connected with the output of input-buffer unit.

Said charge/discharge unit comprises first capacitive branch and second capacitive branch that is parallel between charge/discharge unit output and the ground level; First capacitive branch comprises first switch, first electric capacity that is connected; First electric capacity, one end ground connection, the tie point of first switch and first electric capacity is through the 3rd switch ground connection; Second capacitive branch comprises second switch, second electric capacity that is connected, second electric capacity, one end ground connection, and the tie point of the second switch and second electric capacity is through the 4th switch ground connection; The control end of first switch, second switch, the 3rd switch, the 4th switch is connected with the control logic unit.

The invention has the beneficial effects as follows, reduced the grid voltage deviation of drive circuit, realized dynamic stability.

Below in conjunction with accompanying drawing and embodiment the present invention is further described.

Description of drawings

Fig. 1 is the circuit diagram of prior art.

Fig. 2 is a circuit diagram of the present invention.

Fig. 3 is control logic element circuit figure of the present invention.

Fig. 4 is that current ratio of the present invention is than logical circuitry.

Fig. 5 is the curve chart that Vb2 changes with control signal Ф 3 and Ф 3b state among the embodiment.

Embodiment

Referring to Fig. 2.

Lvds driver of the present invention comprises input-buffer unit and driver element, also comprises discharging and recharging control unit, and the said control unit that discharges and recharges comprises voltage difference/difference between current converting unit, electric current comparing unit, control logic unit and charge/discharge unit; The electric current comparing unit is connected with the input-buffer unit through voltage difference/difference between current converting unit; The control logic unit is connected with the electric current comparing unit, and is connected with the control end of charge/discharge unit; The output of charge/discharge unit is connected with the output of input-buffer unit.Said charge/discharge unit comprises first capacitive branch and second capacitive branch that is parallel between charge/discharge unit output and the ground level; First capacitive branch comprises first K switch 1, first capacitor C 1 that is connected; First capacitor C, 1 one end ground connection, the tie point of first K switch 1 and first capacitor C 1 is through the 3rd K switch 3 ground connection; Second capacitive branch comprises second switch K2, second capacitor C, 2, the second capacitor C, the 2 one end ground connection that are connected, and the tie point of the second switch K2 and second capacitor C 2 is through the 4th K switch 4 ground connection; The control end of first K switch 1, second switch K2, the 3rd K switch 3, the 4th K switch 4 is connected with the control logic unit.

First K switch 1 and the 4th K switch 4 are controlled by signal Ф 3, and second switch K2 and the 3rd K switch 3 are controlled by signal Ф 3b, and Ф 3 and Ф 3b are two output signals of control logic unit.

Simultaneously referring to Fig. 5.As D1 during by " height " change " low ", D1b is by " low " change " height ", and at this moment P1 will convert normal operating conditions into by shutoff, and its instantaneous grid voltage VC is greater than Vb2, and unnecessary electric charge will inject buffer in the S1 raceway groove simultaneously, so all can make the Vb2 rising.Because make open-loop gain that buffer itself is limited and settling time Vb2 not dragged down at each switch switching cycle.Add an extra control loop for this reason and guaranteed bias point A dynamic stability.Because Vb2 is greater than reference voltage V b; The voltage difference of Vb and Vb2 converts the electric current difference into through tail current mirror image pipe; CL Compare Logic will be sampled to this difference, and produce triggering signal, and this signal is handled the control clock Ф 3 and Ф 3b that produces a pair of complementation through control logic; Capacitor C 1 that (control logic is as shown in Figure 3, mainly is made up of reverser, NAND gate, trigger) makes or C2 are inserted A point and all equivalent capacitys of A point to carry out electric charge and heavily distributes.Because capacitor C 1/C2 initial charge is 0, will drag down A point current potential inserting moment.Because A point voltage Vb2 is higher than Vb, and is as shown in Figure 4 then according to comparative result, control logic can make Ф 3 and Ф 3b continue upset (T2 time period), and Vb2 can be dragged down (the U point is to the G point) gradually like this; And if A point voltage Vb2 is when being lower than Vb, control logic can make Ф 3 and Ф 3b stop upset (T1 time period), and C1 or C2 are continued to charge A point voltage Vb2 lifting (the K point is to the U point).It is thus clear that because there is certain delay in this control loop, can there be certain stability range in the voltage of Vb2, the more little Vb2 deviation of loop delay is also just more little.Fig. 4 shows that under the operating frequency 1.1GHz situation, Vb2 deviation maximum is merely 0.1V.Reached the purpose of dynamic stability.

Fig. 4 is that current ratio among Fig. 3 is than logical circuitry.Specification has been made principle of the present invention and necessary details and has been proved absolutely that those of ordinary skill can be implemented fully.Embodiment is unintelligible to be the restriction to interest field of the present invention, all belongs within the interest field of the present invention based on any distortion of the principle of the invention.

Claims

1.LVDS driver comprises input-buffer unit and driver element, it is characterized in that, also comprises discharging and recharging control unit, the said control unit that discharges and recharges comprises voltage difference/difference between current converting unit, electric current comparing unit, control logic unit and charge/discharge unit; The electric current comparing unit is connected with the input-buffer unit through voltage difference/difference between current converting unit; The control logic unit is connected with the electric current comparing unit, and is connected with the control end of charge/discharge unit; The output of charge/discharge unit is connected with the output of input-buffer unit; Said charge/discharge unit comprises first capacitive branch and second capacitive branch that is parallel between charge/discharge unit output and the ground level; First capacitive branch comprises first switch (K1), first electric capacity (C1) that is connected; First electric capacity (C1) end ground connection, the tie point of first switch (K1) and first electric capacity (C1) is through the 3rd switch (K3) ground connection; Second capacitive branch comprises second switch (K2), second electric capacity (C2) that is connected, second electric capacity (C2) end ground connection, and the tie point of second switch (K2) and second electric capacity (C2) is through the 4th switch (K4) ground connection; The control end of first switch (K1), second switch (K2), the 3rd switch (K3), the 4th switch (K4) is connected with the control logic unit.