CN102122964B - Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA) - Google Patents

Abstract

The invention discloses an implementation method of a high-speed reed-solomon (RS) codec based on a field programmable gate array (FPGA), comprising FPGA implementation of a high-speed RS (244, 212) coder and FPGA implementation of a high-speed RS (244, 212) decoder. In the invention, the high-speed RS coder is a circuit based on polynomial division, and the high-speed RS decoder is based on three-level pipeline architecture, and dual-clock driving based on clock i_clk and reverse clock i_clk180 is adopted; In addition, based on a common Galois field (GF) multiplying unit, three basic computing units, including a constant coefficient GF multiply-add fused unit, a constant coefficient GF multiplying unit and a dual-clock period controlled GF multiplying unit are provided, thereby greatly improving the computing speed and reducing hardware complexity. The implementation method has the advantages of high supporting throughput rate and strong capacity of correcting burst errors and can be applied to many aspects.

Description

A kind of High-Speed RS coder implementation method based on FPGA

Technical field

The invention belongs to channel decoding device field in communication, particularly a kind of High-Speed RS based on FPGA (244,212) coder implementation method that can be used for the processing of satellite high speed signal.

Background technology

RS code, constructed in nineteen sixty by Reed and Solomon application Mattson-Solomon (MS) multinomial, it is the multi-system BCH code that a class has very strong error correcting capability, it can correct random error can correct again burst error, and this good characteristic is specially adapted in communication system that channel disturbance is very complicated it.The situation that so-called Complex Channel is disturbed, just refers to that the type of error occurring in channel may be at a time that burst error may be also random error, but can only have the mistake of a type in a certain definite moment.RS code is not only a kind of code of good correction random error, is again a kind of code of the correction burst error that approaches the best.RS code is widely used among engineering reality, in digital transmission system, if power limited and communication quality require high (as deep space communication, diving communication, mobile communication etc.), generally all adopt the cascaded code take RS code as outer code, in survey of deep space, often need to transmit telemetry and the project data of a large amount of preciousnesses, or need to transmit in real time dynamic image data clearly, use meets the RS error-correcting code technique of CCSDS standard, can guarantee the reliability of transmitted data.

The coding of RS is realized comparatively simple, and on RS coding rate, Zhigang Ren proposes a kind of improvement, selects the Cyclone III (EP3C25Q240C8) of altera corp, and maximum encoded clock frequency is 262.26MHz.

And in the decode procedure of RS code, due to solving of key equation in interpretation method, adopt the repeatedly method of iteration, itself realizes with regard to more complicated, again because the Project Realization of interpretation method is also more difficult, thereby causes its Project Realization cost higher, and be difficult to the decoding speed that reaches desirable, so whether a kind of RS code can be applied in practice, depend on to a great extent whether decoding algorithm can be simple, quick, economical.Before this, Xilinx company and French MATRA MARCONI company produced and met (255 of CCSDS standard, 223) coding chip of RS code, wherein, the time interval between two input code blocks of the coding chip of Xilinx company is not less than 405 clock cycle, the maximum data percent of pass of the coding chip that MATRA MARCON company of France produces is also no more than 100Mbits/s, in addition, a kind of High-Speed RS coding chip of the CCSDS of meeting standard is proposed in patent CN100384116C, adopt the xcv600e-6hq240c of Xilinx company as realizing chip, its data pass rate is greater than 400Mbit/s, resource is used and is less than 180,000 system doors, so, the interval timer cycle reducing between input code block is an urgent demand that Near Future Project is realized with the data pass rate that improves decoder part.

Summary of the invention

The object of the invention is to overcome the deficiency of above-mentioned prior art, propose a kind of High-Speed RS coder implementation method based on FPGA, with improve its versatility with and the data throughput supported, meet the communication requirement of different scenes.

To achieve these goals, technical scheme of the present invention is as follows:

The know-why of the inventive method comprises RS coding principle and RS decoding principle.

1.RS coding principle

Making α is galois field GF (2 ^m) in primitive element, the generator polynomial form that can entangle t wrong RS code is:

$g\left(x\right)=\underset{j=b}{\overset{b+2t-1}{\mathrm{\Π}}}(x-{\mathrm{\α}}^{\mathrm{sj}})=\underset{i=0}{\overset{32}{\mathrm{\Σ}}}{g}_i{x}^i---\left(1\right)$

Wherein b is called side-play amount, and s is called the stepping factor.

Note: because generator polynomial and the true form of shorten cyclic codes are identical, so this does not affect the form of generator polynomial.

Take RS systematic code (n, k) as example, wherein, the front k position of code word is information bit, and k+1 is check bit to n position, and

C(x)＝m(x)x ^n-k+r(x) (2)

First, order needs the sequence of coding to be:

m＝(m _k-1，m _k-2，Lm ₁，m ₀，) (3)

So, coding multinomial is:

m(x)＝m _k-1x ^k-1+m _k-2x ^k-2+L+m ₁x+m ₀ (4)

Wherein k=n-2t.

Under systematic code form, 2t check digit is just message polynomial x ^2tresidue r (x)=r that m (x) obtains after divided by generator polynomial g (x) _2t-1x ^2t-1+ r _2t-2x ^2t-2+ L+r ₁x+r ₀coefficient.That is:

m(x)x ^2t＝q(x)g(x)+r(x) (5)

Now, the codeword polynome of encoder output is:

C(x)＝m(x)x ^2t+r(x)＝q(x)g(x) (6)

Therefore, the encoded question of RS code is exactly the division problem take g (x) as mould.

In addition, the present invention realizes related RS (244, the 212) code of example, and every group code word comprises 244 code elements, and wherein first 212 is information code element { m ₁, m ₂, L, m ₂₁₂, latter 32 is verification code element { p ₁, p ₂, L, p ₃₂.

Wherein primitive polynomial adopts:

F(x)＝x ⁸+x ⁷+x ²+x+1 (7)

Generator polynomial:

$G\left(x\right)=\underset{j=112}{\overset{143}{\mathrm{\Π}}}(x-{\mathrm{\α}}^{11j})=\underset{i=0}{\overset{32}{\mathrm{\Σ}}}{g}_i{x}^i$

$=x^{32}+g_1{x}^{31}+g_2{x}^{30}+g_3{x}^{29}+g_4{x}^{28}+g_5{x}^{27}+g_6{x}^{26}+g_7{x}^{25}+g_8{x}^{24}$

$+g_9{x}^{23}+g_{10}{x}^{22}+g_{11}{x}^{21}+g_{12}{x}^{20}+g_{13}{x}^{19}+g_{14}{x}^{18}+g_{15}{x}^{17}+g_{16}{x}^{16}+g_{15}{x}^{15}$

$+g_{14}{x}^{14}+g_{13}{x}^{13}+g_{12}{x}^{12}+g_{11}{x}^{11}+g_{10}{x}^{10}+g_9{x}^9+g_8{x}^8+g_7{x}^7+g_6{x}^6---\left(8\right)$

$+g_5{x}^5+g_4{x}^4+g_3{x}^3+g_2{x}^2+g_{1}x+1$

$=x^{32}+91x^{31}+127x^{30}+86x^{29}+16x^{28}+30x^{27}+13x^{26}+235x^{25}+97x^{24}$

$+165x^{23}+8x^{22}+42x^{21}+54x^{20}+86x^{19}+171x^{18}+32x^{17}+113x^{16}+32x^{15}$

$+171x^{14}+86x^{13}+54x^{12}+42x^{11}+8x^{10}+165x^9+97x^8+235x^7+13x^6$

$+{30x}^5+{16x}^4+{86x}^3+{127x}^2+91x+1$

2.RS decoding principle

First, make the codeword polynome of transmitting terminal transmission be:

C(x)＝c _n-1x ^n-1+c _n-2x ^n-2L+c ₁x+c ₀ (9)

Make the receiving sequence multinomial of receiving terminal be:

R(x)＝r _n-1x ^n-1+r _n-2x ^n-2L+r ₁x+r ₀ (10)

Make error patterns multinomial be:

$E\left(x\right)=e_v{x}^{l_v}+e_{v-1}{x}^{l_{v1}}L+e_2{x}^{l_2}+e_1{x}^{l_1}---\left(11\right)$

Wherein

for errors present number, the improper value of this position is e _i.

So:

R(x)＝C(x)+E(x) (12)

The traditional decoding of RS code is identical with general linear code, is divided into following three steps:

1) calculate syndrome S (x) by the code word R receiving (x).

2) determine error pattern E (x) by syndrome S (x).

3) calculate R (x)-E (x)=C (x), obtain decoder output codons C (x); If decoder can not obtain E (x), decoding failure, now decoder is pointed out in R (x) wrongly, but can not correct.

Wherein the 2nd) step can be divided into again and asks error location polynomial σ (x) and improper value multinomial ω (x) two steps.Between syndrome S (x) and σ (x) and ω (x), should meet key equation:

S(x)σ(x)＝ω(x)modx ^2t (13)

The structure of decoder specifically comprises that the calculating of associated polynomial, calculating, money search and the improper value of error location polynomial calculate four modules, associated polynomial computing module generator polynomial S (x), it can be used for key equation solving module and solves key polynomial S (x) σ (x)=ω (x) modx ^2t, wherein, we can carry out solving key equation with ME algorithm or BM algorithm, obtain error location polynomial σ (x) and improper value multinomial ω (x).Then,, by money search module and Forney algoritic module, these two multinomials can be used to obtain errors present and corresponding improper value, carry out error correction at the output of decoder.In addition, FIFO memory is to carry out buffer memory according to the time delay of these modules to receive signal.Wherein, the principal element of decision decoder complexity is to solve key polynomial.

3. technical scheme

For realizing high speed object, a kind of High-Speed RS coder implementation method based on FPGA of the present invention comprises High-Speed RS (244,212) FPGA of encoder realizes with the FPGA of High-Speed RS (244,212) decoder and realizing, and adopts doubleclocking to drive to realize.

The FPGA method that realizes High-Speed RS (244,212) encoder is as follows:

High-Speed RS (244,212) encoder adopts the work of doubleclocking drive pattern, improved clock utilization, thereby improved coding rate, and resource consumption is lower.To 212 of every group of serial input information code element { m ₁, m ₂, L, m ₂₁₂encoding obtains 32 verification code element { p ₁, p ₂, L, p ₃₂, concrete methods of realizing comprises the steps:

(1) K switch 1 connects a mouth, Closing Switch K2, and under the driving of clock i_clk, k information code element m of input _kinput coding device under the control of enable signal, carries out GF territory sum operation with register D0 and obtains S _md, k represents code element sequence number, is initially 1, meanwhile, encoder is by input message code element m _kdirectly output;

(2) under the driving of clock i_clk180, S _mdcarry out constant coefficient GF territory multiply-add operation with register D1, result store is to register D0;

(3) under the driving of clock i_clk, S _mdcarry out constant coefficient GF territory multiply-add operation with register D2～D31, result is stored to respectively register D1～D30 simultaneously, and by S _mdbe stored in register D31;

(4) judge information code element whether input complete, if so, execution step (5), otherwise, input k+1 information code element m _k+1to encoder, return to step (1);

(5) after all information code elements have calculated, cut-off switch K2, K1 connects b mouth, and under the driving of clock i_clk, the value of serial output register D0～D31 is as check code element, and this group information code element coding is complete;

In the present invention, described High-Speed RS (244,212) the FPGA method of encoder adopts the circuit based on polynomial division, 32 constant coefficient GF territory adder and multipliers are called, control one of them constant coefficient GF territory adder and multiplier by anti-phase driving clock i_clk180, make it reach the effect of high spped coding.

The FPGA method that realizes High-Speed RS (244,212) decoder is as follows:

High-Speed RS (244 of the present invention, 212) the FPGA method of decoder adopts doubleclocking to drive, there is three class pipeline structure, comprise syndrome computing module, solve key equation module, improper value acquisition module (comprises money search, improper value calculates, can error correction judgement), information storage FIFO, improper value storage FIFO and the circuit of correcting a mistake, the data after decoding are exported by the circuit of correcting a mistake.

Described doubleclocking drives, and in the flow process of common RS decoding, hardware is realized to more complicated submodule, adopts reverse clock to drive, and when making it reach high-speed computation, has also reduced the complexity of hardware circuit.

Described three class pipeline structure, wherein the first order is for following computing module, and the second level is for solving key equation module, and the third level is improper value acquisition module and the circuit etc. of correcting a mistake, it has improved decoding speed to a great extent, has reduced the interval timer cycle between two input code blocks.

Described syndrome computing module, by every group of 244 data symbols { c ₁, c ₂, L, c ₂₄₄serial input, calculate the coefficient { s of associated polynomial ₁, S ₂, L, S ₃₂, be always divided into 32 submodules, the coefficient of respectively corresponding 32 associated polynomials, the parallel input of its result solves key equation module, for solving the polynomial coefficient of error location polynomial and improper value.

The described key equation module that solves, according to inputted associated polynomial coefficient { S ₁, S ₂, L, S ₃₂and RiBM algorithm carry out interative computation, by the coefficient { σ of the error location polynomial obtaining ₁, σ ₂, L, σ ₃₂and the polynomial coefficient { ω of improper value ₁, ω ₂, L, ω ₃₂, and error code number, parallel input error value acquisition module, for judging whether decoding correctly and mistake in computation position and improper value, is wherein serial output between two groups of polynomial coefficients.

Described improper value acquisition module, comprises money search module: the root x that money search method is obtained to error location polynomial _i, and the corresponding polynomial value of improper value of this root in improper value calculating

calculating, be incorporated among a module, obtain the root x of error location polynomial simultaneously _i, the polynomial value of improper value and the constant term factor

do not affecting under the prerequisite of speed, greatly reducing the needed hardware resource of improper value computing module and clock cycle; Improper value computing module: the analog value that adopts money search module to obtain calculates improper value.Improper value acquisition module, by the improper value calculating, is exported in improper value storage FIFO and is stored simultaneously.In addition, money search module is also exported judgement enable information, for controlling the circuit of correcting a mistake.

Described information storage FIFO, for the data symbols of input being stored sequentially into the cell fifo of fpga chip, after improper value acquisition module has calculated, outputs to data successively and corrects a mistake in circuit according to error situation;

Described improper value storage FIFO, be used for the output data of improper value acquisition module, store into sequentially in the cell fifo of fpga chip, after obtaining improper value module and having calculated, according to error situation, calculated improper value is outputed to successively and corrected a mistake in circuit;

The described circuit of correcting a mistake, it is the judgement enable information that adopts the output of improper value acquisition module, control information storage FIFO and improper value storage FIFO, when judging that decoder is when correct decoding,, by both canned data Sequential outputs, carry out GF territory sum operation, using result as decoding word output, otherwise the information of directly information being stored to FIFO is as output.

In the present invention, described constant coefficient GF territory multiplier, on the basis of common GF territory multiplier, is determined the value of one of them variable, meanwhile, for this definite variable, multiplier is improved, greatly reduce the complexity of its basic processing unit, thereby improved arithmetic speed.

In the present invention, described constant coefficient GF territory adder and multiplier carries out GF territory multiplication and the add operation of GF territory simultaneously, and only in the structure of constant coefficient GF territory multiplier, has increased an XOR, is highly susceptible to hardware and realizes, and has also greatly improved arithmetic speed simultaneously.

In the present invention, the two described clock cycle are controlled GF territory multiplier, and common GF territory multiplier architecture is divided into two minor structures, and computing is carried out in segmentation, has obtained the raising of speed with the time delay of a clock.

Compared with prior art, the invention has the beneficial effects as follows:

1, adopt doubleclocking to drive, the data pass rate of High-Speed RS coder is high, as the xc4vlx160-12ff1148 chip with Xilinx company carries out comprehensive simulating and static timing analysis, wherein, the highest clock that works in 560MHz of encoder, its data throughout is about 4.48Gbit/s, the highest clock that works in 370MHz of decoder, and its data throughout is about 2.96Gbit/s.In addition, its data resource utilization rate is not high yet, as shown in the following chart.

2, High-Speed RS decoder adopts three class pipeline structure, has reduced the interval timer cycle between input code block, simultaneously by the part calculations incorporated of money search and improper value in a module, improved the efficiency of pipeline organization.

3, three kinds of basic processing units are proposed, constant coefficient GF territory adder and multiplier, constant coefficient GF territory multiplier, and the GF territory multiplier of two clock cycle control, several multipliers, in conjunction with utilization, have not only improved arithmetic speed greatly, have also reduced hardware complexity.

4, whole coding and decoding process all realizes in a slice fpga chip, and stable and reliable working performance can easily be transplanted simultaneously.

5,, for different practical application request, internal circuit design can be revised neatly in the situation that keeping external interface constant, so that be connected with different equipment.

6, not only can correct random error, and there is the function of very strong correction burst error.

The present invention is directed to varying environment and all can apply, there is very strong selectivity, adopt positive and negative doubleclocking to drive, very on large program, improving data throughout, and avoiding again the excessive shortcoming of consumption of natural resource, hard-wired complexity is significantly reduced.In addition due in hardware is realized, all adopt the simplest hardware cell, be highly susceptible to hardware and realize.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of realizing of Implem entation of R S Code of the present invention;

Fig. 2 is the three class pipeline structural representation of High-Speed RS decoder of the present invention;

Fig. 3 is the syndrome calculating sub module schematic diagram that the present invention adopts;

Fig. 4 is the schematic flow sheet of the RiBM algorithm that adopts of the present invention;

Fig. 5 is that the money that the present invention adopts is searched for the structured flowchart of calculating;

Fig. 6 is the circuit structure signal of the constant coefficient GF territory adder and multiplier that proposes of the present invention;

Fig. 7 is the circuit structure signal of the constant coefficient GF territory multiplier that proposes of the present invention;

Fig. 8 is the emulation sequential chart of the Implem entation of R S Code that proposes of the present invention;

Fig. 9 is the emulation sequential chart of the High-Speed RS decoder that proposes of the present invention.

Embodiment:

Be easy to understand understanding in order to make technological means of the present invention, creation characteristic and to reach object, further set forth the present invention below in conjunction with specific embodiment.

A kind of High-Speed RS coder implementation method based on FPGA of the present invention comprises that the FPGA of High-Speed RS (244,212) encoder realizes and the FPGA of High-Speed RS (244,212) decoder realizes, and adopts reverse clock to realize.

The FPGA method that realizes High-Speed RS (244,212) encoder is as follows:

Described High-Speed RS (244,212) encoder adopts the work of doubleclocking drive pattern, to 212 of every group of serial input information code element { m ₁, m ₂, L, m ₂₁₂encoding obtains 32 verification code element { p ₁, p ₂, L, p ₃₂, in the situation that not increasing hardware complexity, improved clock utilization, thereby improved coding rate, and resource consumption is lower, as Fig. 1, concrete methods of realizing comprises the steps:

(1) K switch 1 connects a mouth, Closing Switch K2, and under the driving of clock i clk, k information code element m of input _kinput coding device under the control of enable signal, carries out GF territory sum operation with register D0 and obtains S _md, k represents code element sequence number, is initially 1, meanwhile, encoder is by input message code element m _kdirectly output;

(2) under the driving of clock i_clk180, S _mdcarry out constant coefficient GF territory multiply-add operation with register D1, result store is to register D0;

(3) under the driving of clock i_clk, S _mdcarry out constant coefficient GF territory multiply-add operation with register D2～D31, result is stored to respectively register D1～D30 simultaneously, and by S _mdbe stored in register D31;

(4) judge information code element whether input complete, if so, execution step (5), otherwise, input k+1 information code element m _k+1to encoder, return to step (1);

(5) after all information code elements have calculated, cut-off switch K2, K1 connects b mouth, and under the driving of clock i_clk, the value of serial output register D0～D31 is as check code element, and this group information code element coding is complete;

Wherein, described High-Speed RS (244,212) the FPGA method of encoder adopts the circuit based on polynomial division, 32 constant coefficient GF territory adder and multipliers are called, the effect of being controlled one of them constant coefficient GF territory adder and multiplier and made to reach high spped coding by anti-phase driving clock i_clk180, its specific coding sequential analogous diagram as shown in Figure 7.

The FPGA method that realizes High-Speed RS (244,212) decoder is as follows:

High-Speed RS (244 of the present invention, 212) the FPGA method of decoder adopts doubleclocking to drive, there is three class pipeline structured flowchart as shown in Figure 2, comprise syndrome computing module, solve key equation module, improper value acquisition module (comprises money search, improper value calculates, can error correction judgement), information storage FIFO, improper value storage FIFO and the circuit of correcting a mistake, data after decoding are by the circuit output of correcting a mistake, and its concrete decoding sequential analogous diagram as shown in Figure 9.

Described doubleclocking drives, and in the flow process of common RS decoding, hardware is realized to more complicated submodule, adopts reverse clock to drive, and when making it reach high-speed computation, has also reduced the complexity of hardware circuit.

Described three class pipeline structure, wherein the first order is for following computing module, and the second level is for solving key equation module, and the third level is improper value acquisition module and the circuit etc. of correcting a mistake, it has improved decoding speed to a great extent, has reduced the interval timer cycle between two input code blocks.

Described syndrome computing module, by every group of 244 data symbols { c ₁, c ₂, L, c ₂₄₄serial input, calculate the coefficient { S of associated polynomial ₁, S ₂, L, S ₃₂, be always divided into 32 submodules, the coefficient of respectively corresponding 32 associated polynomials, the parallel input of its result solves key equation module, for solving the polynomial coefficient of error location polynomial and improper value.

The described key equation module that solves, according to inputted associated polynomial coefficient { S ₁, S ₂, L, S ₃₂and RiBM algorithm carry out interative computation, by the coefficient { σ of the error location polynomial obtaining ₁, σ ₂, L, σ ₃₂and the polynomial coefficient { ω of improper value ₁, ω ₂, L, ω ₃₂, and error code number, parallel input error value acquisition module, for judging whether decoding correctly and mistake in computation position and improper value, is wherein serial output between two groups of polynomial coefficients, referring to Fig. 4.

Described improper value acquisition module, comprises money search module: the root x that money search method is obtained to error location polynomial _i, and the corresponding polynomial value of improper value of this root in improper value calculating

calculating, be incorporated among a module, obtain the root x of error location polynomial simultaneously _i, the polynomial value of improper value

and the constant term factor

do not affecting under the prerequisite of speed, greatly reducing the needed hardware resource of improper value computing module and clock cycle; Improper value computing module: the analog value that adopts money search module to obtain calculates improper value.Improper value acquisition module, by the improper value calculating, is exported in improper value storage FIFO and is stored simultaneously.In addition, money search module is also exported judgement enable information, for controlling the circuit of correcting a mistake.

Described information storage FIFO, for the data symbols of input being stored sequentially into the cell fifo of fpga chip, after improper value acquisition module has calculated, outputs to data successively and corrects a mistake in circuit according to error situation;

Described improper value storage FIFO, be used for the output data of improper value acquisition module, store into sequentially in the cell fifo of fpga chip, after obtaining improper value module and having calculated, according to error situation, calculated improper value is outputed to successively and corrected a mistake in circuit;

The described circuit of correcting a mistake, it is the judgement enable information that adopts the output of improper value acquisition module, control information storage FIFO and improper value storage FIFO, when judging that decoder is when correct decoding,, by both canned data Sequential outputs, carry out GF territory sum operation, using result as decoding word output, otherwise the information of directly information being stored to FIFO is as output.

Wherein, described constant coefficient GF territory multiplier, on the basis of common GF territory multiplier, is determined the value of one of them variable,, for this definite variable, multiplier is improved, as shown in Figure 7 meanwhile.

Wherein, described constant coefficient GF territory adder and multiplier carries out GF territory multiplication and GF territory addition simultaneously, only on the basis of constant coefficient GF territory multiplier architecture, has increased an XOR, as shown in Figure 6.

Wherein, the GF territory multiplier that the two described clock cycle are controlled, is divided into two minor structures by common GF territory multiplier architecture, and computing is carried out in segmentation.

In above-mentioned technical scheme, in the equal finite field of each several part computing circuit, carry out, the complexity of RS coding and decoding depends on basic processing unit to a great extent, in traditional RS code coder, multiplier is very complicated, need two multinomials to multiply each other, again divided by primitive polynomial delivery, its multiplying is not that speed is exactly too complicated slowly, in the present invention, most of module all adopts constant coefficient to design multiplier, or improve the constant coefficient GF territory adder and multiplier that forms, GF territory multiplication and addition are carried out simultaneously, all only need to carry out a small amount of XOR, greatly reduce the complexity that multiplier is realized.For the module that cannot adopt constant coefficient GF territory multiplier, for raising speed, can adopt multiple clocks by common GF territory multiplier piecemeal processing, adopt two clocks herein, GF territory multiplier is divided into two to be processed, only increase the time delay that has gone up a clock, just reached good effect.

The present invention adopts doubleclocking to drive, the data pass rate of High-Speed RS coder is high, as the xc4vlx160-12ff1148 chip with Xilinx company carries out comprehensive simulating and static timing analysis, wherein, the highest clock that works in 560MHz of encoder, its data throughout is about 4.48Gbit/s, the highest clock that works in 370MHz of decoder, and its data throughout is about 2.96Gbit/s; High-Speed RS decoder adopts three class pipeline structure, has reduced the interval timer cycle between input code block, simultaneously by the part calculations incorporated of money search and improper value in a module, improved the efficiency of pipeline organization; Three kinds of basic processing units are proposed, constant coefficient GF territory adder and multiplier, constant coefficient GF territory multiplier, and the GF territory multiplier of two clock cycle control, several multipliers, in conjunction with utilization, have not only improved arithmetic speed greatly, have also reduced hardware complexity; Whole coding and decoding process all realizes in a slice fpga chip, and stable and reliable working performance can easily be transplanted simultaneously; For different practical application request, internal circuit design can be revised neatly in the situation that keeping external interface constant, so that be connected with different equipment; Not only can correct random error, and there is the function of very strong correction burst error.

The present invention is directed to varying environment and all can apply, have very strong selectivity, its purposes is very extensive, adopt positive and negative doubleclocking to drive, very on large program, improving data throughout, and avoiding again the excessive shortcoming of consumption of natural resource, hard-wired complexity is significantly reduced; In addition due in hardware is realized, all adopt the simplest hardware cell, be highly susceptible to hardware and realize.

(1) as shown in Figure 1, be the block diagram of realizing of the Implem entation of R S Code that proposes of the present invention, wherein, Mg ₁～Mg ₁₆corresponding to respectively constant coefficient is the constant coefficient GF territory adder and multiplier CMS (Constant Multiply and Sum) of g1～g16,212 information code element { m of serial input ₁, m ₂, L, m ₂₁₂, K switch 1 connects a mouth, Closing Switch K2, and under the driving of clock i_clk, k information code element m of input _kinput coding device under the control of enable signal, carries out GF territory sum operation with register D0 and obtains S _md, k represents code element sequence number, is initially 1, meanwhile, encoder is by input message code element m _kdirectly output; Under the driving of clock i_clk180, S _mdcarry out constant coefficient GF territory multiply-add operation with register D1, result store is to register D0; Under the driving of clock i_clk, S _mdcarry out constant coefficient GF territory multiply-add operation with register D2～D31, result is stored to respectively register D1～D30 simultaneously, and by S _mdbe stored in register D31; Judge information code element whether input complete, if so, cut-off switch K2, K1 connects b mouth, under the driving of clock i_clk, the value of serial output register D0～D31 is as check code element, this group information code element coding is complete, otherwise, input k+1 information code element m _k+1to encoder, continue encoding operation;

(2) as shown in Figure 2, it is the three class pipeline structured flowchart of the High-Speed RS decoder that proposes of the present invention, the first order is syndrome computing module, syndrome calculating sub module composition as shown in Figure 3, the second level is for asking key equation module, its particular flow sheet as shown in Figure 4, the third level is improper value acquisition module, wherein improper value acquisition module is divided into money search module, as Fig. 5 and Forney mistake in computation value module, wherein, Csi is the coefficient of the constant coefficient GF territory multiplier CM (Constant Multiplier) that in associated polynomial module, i submodule used, Cc ₁～Cc ₁₆the coefficient of the constant coefficient GF territory multiplier of using for money search module, in addition, all adders in Fig. 5 are all driven by clock i_clk, and all CM are driven by clock i_clk180, in the time that enable signal is high level, signal { σ ₁, σ ₂, L, σ ₃₂input, switch is placed in a end simultaneously, and in the time that enable signal is low level, switch is placed in b end simultaneously.

(3) as shown in Figure 6, for saving resource amount and reduction complexity, the constant coefficient GF territory adder and multiplier adopting in the present invention, figure is depicted as the constant coefficient GF territory adder and multiplier that constant coefficient is g1, be illustrated in figure 7 the constant coefficient GF territory multiplier that in the inventive example, the constant coefficient that adopts is 21, wherein d0～d7 corresponds to eight Bit datas that will carry out multiplying, and a0～a7 corresponds to eight Bit datas that will carry out add operation, eight Bit datas that n0～n7 is obtained result.As seen from the figure, what adopt is the simplest XOR gate, and complexity is very low.

(4) as shown in Figure 8 and Figure 9, for the typical sequential analogous diagram of Implem entation of R S Code and High-Speed RS decoder, the coding and decoding mode of visible its streamline, wherein i_clk is forward clock, and i_clk180 is reverse clock, the reset signal that i_rst is this module, i_data_ena is effective enable signal of data input, iv_data is the data symbols of input, and ov_data is the data symbols of output, and o_data_ena is effective enable signal of data output.

Described basic processing unit all carries out in GF territory.

Above-mentioned steps has been described preferred embodiment of the present invention, and obviously those skilled in the art can make various modifications and replacement to the present invention by reference to preferred embodiment of the present invention and accompanying drawing, within these modifications and replacement all should fall into protection scope of the present invention.

Claims (4)

1. the High-Speed RS coder implementation method based on FPGA, the method comprises that the FPGA of High-Speed RS (244,212) encoder realizes and the FPGA of High-Speed RS (244,212) decoder realizes, and it is characterized in that:

The FPGA implementation method of described High-Speed RS (244,212) encoder, to 212 of every group of serial input information code element { m ₁, m ₂..., m ₂₁₂encoding obtains 32 verification code element { p ₁, p ₂..., p ₃₂, concrete steps are: (1) K switch 1 connects a mouth, Closing Switch K2, and under the driving of clock i_clk, k information code element m of input _kinput coding device under the control of enable signal, carries out GF territory sum operation with register D0 and obtains S _md, k represents code element sequence number, is initially 1, meanwhile, encoder is by input message code element m _kdirectly output; (2) under the driving of clock i_clk180, S _mdcarry out constant coefficient GF territory multiply-add operation with register D1, result store is to register D0; (3) under the driving of clock i_clk, S _mdcarry out constant coefficient GF territory multiply-add operation with register D2～D31, result is stored to respectively register D1～D30 simultaneously, and by S _mdbe stored in register D31; (4) judge information code element whether input complete, if so, execution step (5), otherwise, input k+1 information code element m _k+1to encoder, return to step (1); (5) after all information code elements have calculated, cut-off switch K2, K1 connects b mouth, and under the driving of clock i_clk, the value of serial output register D0～D31 is as check code element, and this group information code element coding is complete;

Described High-Speed RS (244,212) the FPGA implementation method of decoder, adopt doubleclocking to drive and three class pipeline structure, comprise syndrome computing module, solve key equation module, improper value acquisition module, information storage FIFO, improper value storage FIFO and the circuit of correcting a mistake, the data after decoding are by the described circuit output of correcting a mistake;

Described doubleclocking drives, and the part of module that hardware is realized to more complicated adopts reverse clock to drive, and makes it reach realization of High Speed object;

Described three class pipeline structure, wherein the first order is for following computing module, and the second level is for solving key equation module, and the third level is improper value acquisition module and the circuit of correcting a mistake;

Described syndrome computing module, by every group of 244 data symbols { c ₁, c ₂..., c ₂₄₄serial input, calculate the coefficient { S of associated polynomial ₁, S ₂..., S ₃₂, be always divided into 32 submodules, the coefficient of respectively corresponding 32 associated polynomials, the parallel input of its result solves key equation module, for solving the polynomial coefficient of error location polynomial and improper value;

The described key equation module that solves, according to inputted associated polynomial coefficient { S ₁, S ₂..., S ₃₂and RiBM algorithm carry out interative computation, by the coefficient { σ that asks error location polynomial obtaining ₁, σ ₂..., σ ₃₂and the polynomial coefficient { ω of improper value ₁, ω ₂..., ω ₃₂, and error code number, parallel input error value acquisition module, for judging whether decoding correctly and mistake in computation position and improper value;

Described improper value acquisition module, comprises money search module: the root x that money search method is obtained to error location polynomial _i, and the corresponding polynomial value of improper value of this root in improper value calculating calculating, be incorporated among a module, obtain the root x of error location polynomial simultaneously _i, the polynomial value of improper value

and the constant term factor

wherein i represents the sequence number of the root of error location polynomial, is initially 1; Improper value computing module: the analog value that must adopt money search module to obtain calculates improper value; Improper value acquisition module, by the improper value calculating, is exported in improper value storage FIFO and is stored simultaneously; In addition, money search module is also exported judgement enable information, for controlling the circuit of correcting a mistake;

Described information storage FIFO, for the data symbols of input being stored sequentially into the cell fifo of fpga chip, after improper value acquisition module has calculated, outputs to data successively and corrects a mistake in circuit according to error situation;

Described improper value storage FIFO, be used for the output data of improper value acquisition module, store into sequentially in the cell fifo of fpga chip, after obtaining improper value module and having calculated, according to error situation, calculated improper value is outputed to successively and corrected a mistake in circuit;

The described circuit of correcting a mistake, it is the judgement enable information that adopts the output of improper value acquisition module, control information storage FIFO and improper value storage FIFO, when judging that decoder is when correct decoding,, by both canned data Sequential outputs, carry out GF territory sum operation, using result as decoding word output, otherwise the information of directly information being stored to FIFO is as output.

2. a kind of High-Speed RS coder implementation method based on FPGA according to claim 1, it is characterized in that: described constant coefficient GF territory multiply-add operation is on the basis of common GF territory multiplier, determine the value of one of them variable, simultaneously, for this definite variable, multiplier is improved.

3. a kind of High-Speed RS coder implementation method based on FPGA according to claim 1, it is characterized in that: described constant coefficient GF territory multiply-add operation carries out GF territory multiplication and GF territory addition simultaneously, and only in the structure of constant coefficient GF territory multiplier, has increased an XOR.

4. a kind of High-Speed RS coder implementation method based on FPGA according to claim 1, is characterized in that: the described constant coefficient GF territory multiply-add operation that two clock cycle were controlled, common GF territory multiplier architecture is divided into two minor structures, and computing is carried out in segmentation.

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