CN102117656A - Memory method for nanocrystalline floating gate structure-based multi-value nonvolatile memory - Google Patents
Memory method for nanocrystalline floating gate structure-based multi-value nonvolatile memory Download PDFInfo
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Abstract
The invention relates to a memory method for a nanocrystalline floating gate structure-based multi-value nonvolatile memory, and belongs to the technical field of memories. In the memory method, hot electron injection is used as a programming mode, Fowler-Nordheim (FN) tunneling is used as an erasing mode, and four memory states of 00, 01, 10 and 11 are differentiated according to amplitude of read current, so that multi-value memory can be realized under the condition of the same area to double memory capacity. In the method, the new programming mode is adopted to simultaneously program at a source end and a drain end, and the multi-value memory is formed, so that the programming efficiency is greatly improved, a memory window is also increased, memory of more points is realized, and the memory capacity which is twice the conventional memory capacity is realized on a memory unit of the same size; in addition, a manufacturing process is not changed while the advantage is realized, and the cost is greatly reduced.
Description
Technical field
The present invention relates to the memory technology field, relate in particular to a kind of storage means of the many-valued non-volatility memorizer based on nanocrystalline floating gate structure.
Background technology
In recent years, the growth rate of storer has surpassed logical circuit in the integrated circuit, the ratio that storer accounts for chip area by 1999 20% increase to 2005 71%, logical circuit then by 1999 66% drop to 2005 16%.In memory product, the market demand is fastest-rising to be non-volatility memorizer.Flash memory (Flash Memory) has been widely used in the multiple hand-held mobile storage electronic products such as USB flash disk, MP3 player and mobile phone at present as the typical device of non-volatility memorizer.Yet at present extensively by flash memory device structure that industry member adopted in the nanometer feature sizes development, be faced with stern challenge at aspects such as storage time and power consumptions.
Based on nanocrystalline floating gate non-vaporability memory employing is a kind of discrete memory mechanism, electric charge is stored in independently on the nanocrystal, separated by dielectric layer between the nanocrystal, avoided like this having strengthened the electric charge hold facility because the defective on the tunnel layer causes the situation of entire device dropout.
Fig. 1 is the schematic cross-section of prior art nanocrystalline floating gate memory, and with reference to Fig. 1, nanocrystalline floating gate memory comprises: the non-uniform doping Semiconductor substrate; The deposit tunnel oxide, the brilliant particle of LPCVD depositing nano, deposit control oxide layer and polysilicon gate; In Semiconductor substrate, mix and form source electrode and drain electrode, lightly doped drain; Interconnect metal, silicon substrate are the substrate in p type low resistance (100) crystal orientation, and (100) are the crystal orientation direction, are the common crystal orientation directions of silicon crystal, at the substrate of this direction, can realize the surface state minimum number, and be minimum to the electric property influence of device.On this substrate, form the required stack layer of this mechanism by accumulation and growth." this mechanism " is structure shown in Figure 1, i.e. the one-piece construction of nanocrystalline nonvolatile memory.SiO wherein
2/ Nano Si/SiO
2Silicon dioxide tunnel layer, nanometer crystal layer and control oxide layer 3 layer stack structures for key.Lightly doped drain (LDD) plays the effect of organizing hot carrier below this stack layer, thereby guarantees the safety of device.Source end and drain terminal at lightly doped drain (LDD) two ends, provide raceway groove required electronics respectively.The grid that will have the storage unit of said structure is linked to be delegation's (word line), again source end and drain terminal are linked to be row (bit line) respectively, just formed an array structure, making alive on word line and bit line respectively, just can realize storer programming, wipe or read operation.Fig. 2 a is the array structure synoptic diagram of prior art nanocrystalline floating gate memory, wherein WL
1~ WLn is a word line, BL
1~ BLn is a bit line, SL
1~ SLn is the source end line, and two ends, the left and right sides are respectively two reference units, provides the reference voltage when reading to distinguish " 0 " and " 1 ", and E-ref and P-ref are respectively the breakpoints of reference voltage input.Fig. 2 b is the operation table of prior art nanocrystalline floating gate memory, Vbl wherein, and Vsl, Vwl, Vsub are respectively the voltage that adds to bit line, source end line, word line and substrate.As can be seen, because nanocrystalline separation storage characteristics, so traditional mode of operation can only be injected electronics at drain terminal, electronics also mostly is stored in drain terminal, and this has just limited the effect of nano-crystal memory high-level efficiency programming greatly and has read mode.
Summary of the invention
In order to solve above-mentioned technical matters, a kind of storage means of the many-valued non-volatility memorizer based on nanocrystalline floating gate structure is provided, its purpose is, improves the memory space based on the storer of nanocrystalline floating gate structure, reduces the cost of making based on the storer of nanocrystalline floating gate structure.
The invention provides a kind of storage means of the many-valued non-volatility memorizer based on nanocrystalline floating gate structure, comprising:
Apply the 4th voltage at word line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply tertiary voltage at bit line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply first voltage at source end line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, with stores binary data 10 in the storer of choosing;
Apply the 4th voltage at word line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply first voltage at bit line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply tertiary voltage at source end line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, with stores binary data 01 in the storer of choosing;
Earlier apply the 4th voltage at word line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply tertiary voltage at bit line, and apply first voltage at source end line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure; Apply the 4th voltage at word line then based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply first voltage at bit line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply tertiary voltage at source end line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, with stores binary data 00 in the storer of choosing; Or
Apply the 5th voltage at word line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply first voltage at bit line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply first voltage at source end line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, with stores binary data 11 in the storer of choosing.
First voltage is 0V, and tertiary voltage is 3.5V, and the 4th voltage is 6V, and the 5th voltage changes successively according to following magnitude of voltage :-10V ,-12V and-14V.
The invention provides a kind of data storing method that reads,
Apply tertiary voltage at word line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply second voltage at bit line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply first voltage at source end line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, to read the binary data 00,01,10 or 11 of use based on the storage means storage of the many-valued non-volatility memorizer of nanocrystalline floating gate structure.
Second voltage is 0.8V.
The invention provides a kind of storage means of the metal-oxide-semiconductor field effect transistor based on nanocrystalline floating gate structure, comprising:
Apply the 4th voltage at grid based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply tertiary voltage in drain electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply first voltage at source electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, with stores binary data 10 in based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure;
Apply the 4th voltage at grid based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply first voltage in drain electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply tertiary voltage at source electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, with stores binary data 01 in based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure;
Earlier apply the 4th voltage at grid based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply tertiary voltage in drain electrode, and apply first voltage at source electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure; Apply the 4th voltage at grid then based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply first voltage in drain electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply tertiary voltage at source electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, with stores binary data 00 in based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure; Or
Apply the 5th voltage at grid based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply first voltage in drain electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply first voltage at source electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, with stores binary data 11 in based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure.
First voltage is 0V, and tertiary voltage is 3.5V, and the 4th voltage is 6V, and the 5th voltage changes successively according to following magnitude of voltage :-10V ,-12V and-14V.
The invention provides a kind of data storing method that reads,
Apply tertiary voltage at grid based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, apply second voltage in drain electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and apply first voltage at source electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, to read the binary data 00,01,10 or 11 of use based on the storage means storage of the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure.
Second voltage is 0.8V.
Beneficial effect: the present invention adopts new programming mode, leak two ends programming operation simultaneously in the source, and form many-valued storage, improved programming efficiency widely, increased memory window simultaneously, realize the more storage of multiple spot, and the memory space before having realized on the onesize storage unit doubling; In addition, when realizing this advantage, do not change manufacturing process, greatly reduce cost.
Description of drawings
Fig. 1 is the schematic cross-section of prior art nanocrystalline floating gate memory;
Fig. 2 a is the array structure synoptic diagram of prior art nanocrystalline floating gate memory;
Fig. 2 b is the nanocrystalline floating operation table of deleting storer of prior art;
Fig. 3 is the programming mode synoptic diagram of embodiment of the invention nano-crystal floating gate multivalued storage from " 11 " to " 10 ";
Fig. 4 is the programming mode synoptic diagram of embodiment of the invention nano-crystal floating gate multivalued storage from " 10 " to " 01 ";
Fig. 5 is the erase mode synoptic diagram of embodiment of the invention nano-crystal floating gate multivalued storage;
Fig. 6 is the mode that the reads synoptic diagram of embodiment of the invention nano-crystal floating gate multivalued storage;
Fig. 7 is the experimental result of the nanocrystalline multivalued storage of the embodiment of the invention;
Fig. 8 is the threshold distribution of the nanocrystalline multivalued storage of the embodiment of the invention.
Embodiment
The embodiment of the invention has proposed a kind of new method of operating on the basis of traditional structure, utilize the characteristic of nanocrystalline separation storage, has realized many-valued storage, has improved operating efficiency.
The embodiment of the invention provides a kind of storage means of the many-valued non-volatility memorizer based on nanocrystalline floating gate structure, this method can realize the four kinds of store statuss in " 00 " " 01 " " 10 " " 11 ", thereby under same area, realize many-valued storage, make memory space increase twice.
Separation storage characteristics based on the many-valued non-volatility memorizer applying nano crystalline substance of nanocrystalline floating gate structure realizes many-valued storage.Many-valued non-volatility memorizer source end and drain terminal based on nanocrystalline floating gate structure are programmed respectively, based on nanocrystalline separation storage to electronics, and realize reading of different conditions.Nanocrystal can be the nano heterogeneous crystal grain that forms of metal nano-crystalline particle (as W, Ti, Ni, Au, Co or Pt etc.), semiconductor nano crystal grain (as silicon, germanium or cadmium sulfide etc.) and different materials (as the nano heterogeneous crystal grain of germanium/silicon etc.).Many-valued non-volatility memorizer based on nanocrystalline floating gate structure has the array processing structure, realizes many-valued storage in array.
Describe the storage means of the non-volatile floating-gate multivalued storage of the brilliant floating gate structure of embodiment of the invention multi-layer nano below with reference to accompanying drawings in detail.
Because nanocrystalline separation storage characteristics makes hot electron programming can only inject electronics to drain terminal, thereby causes the asymmetric of read operation.As shown in Figure 1, when carrying out the thermoelectron injection programming, electronics quickens to become thermoelectron through raceway groove, stride across the oxide layer potential well at drain terminal and enter nanocrystalline zone, because nanocrystalline separation storage characteristics, electronics can't flow to other zones of floating boom at drain terminal as Flash, and just gathers drain terminal.When reading, because the voltage that adds of drain terminal can make PN junction towards the expansion of source end, some nanocrystallinely just is not included in channel part when reading like this, so read current is less relatively, the programming mode of " 10 " is arrived in " 11 " promptly shown in Figure 3.Adopt this moment the grid end to add high pressure 6V to produce longitudinal electric field, drain terminal adds 3.5V with the generation transverse electric field and for thermionic generation provides energy, and this operates in the time frame of 10us, and the read current of this moment is " 10 " state as shown in Figure 7.The FN tunnelling is the Fowler-Nordheim tunnelling, when voltage is added in silicon dioxide layer, gets band curvature during owing to effect of electric field, thereby realization electronics direct Tunneling is crossed silicon dioxide layer.
Similarly, if the source end of changing into adds 3.5V voltage, as shown in Figure 4, thermoelectron injects and will accumulate in the source end so, and at this moment when the voltage that drain terminal adds 0.8V carries out read operation, because the expansion of PN junction can not comprise nanocrystalline injection zone, so be not subjected to the influence of effect discussed above this moment.Effect herein as previously mentioned because nanocrystalline separation storage characteristics, electronics can't flow to other zones of floating boom at drain terminal as Flash, and just gathers drain terminal.When reading, because the voltage that adds of drain terminal can make PN junction towards the expansion of source end, some nanocrystallinely just is not included in channel part when reading like this, so read current is less relatively.But in such cases, because the voltage that reads is added in the source end, not disconnected in leakage, so all nanocrystalline being included in the raceway groove, read current is unaffected.The electric current that read this moment will be littler than the electric current under " 10 " state, and threshold voltage also is improved, " 01 " promptly shown in Figure 7 state.Dui Ying operation as shown in Figure 4 adopts the grid end to add high pressure 6V producing longitudinal electric field, and the source end adds 3.5V producing transverse electric field and for thermionic generation provides energy, and such operation is exactly that " 10 " arrive the programming mode of " 01 ".
And the process of repetition Fig. 3 and Fig. 4, just add high pressure 6V to produce longitudinal electric field at the grid end, successively adding 3.5V at source end and drain terminal (adds the 3.5V drain terminal with the source end and adds 0V promptly earlier, add 0V with the source end again, the disconnected 3.5V that adds of leakage) voltage is implemented in these two ends thermoelectron successively and injects, and the injected electrons number will further improve so, and threshold voltage will be higher, the mode of operation that Here it is " 00 ", the read current of this moment is " 00 " state as shown in Figure 7.Transverse axis is a grid voltage among Fig. 7, and the longitudinal axis is the drain terminal electric current, the variation of ID-VG curve representation device inside store electrons number when operation.
Erase operation as shown in Figure 5, add negative pressure at the grid end, mode by F N tunnelling is tunneling to electronics in the raceway groove from nanocrystalline, this process probably needs the 10ms magnitude, and be implemented in conversion between " 01 " " 10 " " 11 " by regulating Verase, the grid voltage Verase that is used for wiping that adds on the grid end increases gradually, also " 11 " state during this is nanocrystalline from being programmed, warp-10V and-12V is erased to " 01 " " 10 " state gradually, after-14V is erased to last " 11 " state.
Reading state adds 3.5V voltage at the grid end as shown in Figure 6, adds the bias voltage of 0.8V at drain terminal, when device during at " 00 " state, as shown in Figure 8, because the threshold voltage of nano-crystal memory is greater than 3.5V, this moment, device was in off state, and read current is very little, in the pA magnitude; And if when the state of " 01 " " 10 " " 11 ", device is opened, electric current is in the uA rank, but because noted earlier, size of current can be variant, as shown in Figure 8, when grid voltage is 3.5V, the electric current difference is very big, and read circuit by the periphery and distinguish " 00 " " 01 " " 10 " " 11 " one of four states this moment, successfully realizes many-valued storage
As shown in Figure 8, be 00 " the threshold voltage distribution curve synoptic diagram that reads respectively under the one of four states of " 01 " " 10 " " 11 ", transverse axis is a threshold voltage, the longitudinal axis is the statistics probability that this threshold voltage distributes down.This curve is to sweep grid voltage from 0V to 6V, and adds 0.8V voltage at drain terminal, as can be seen, by the operation of Fig. 3, can successfully realize moving to right of curve, just the increase of threshold voltage to Fig. 5, and the erase operation by Fig. 6 can realize that curve moves to left, and threshold voltage reduces.Thereby realize threshold voltage distribution as shown in Figure 8, threshold voltage is distinguished from each other well and comes as can be seen, thereby realizes the many-valued storage of nanocrystalline floating gate memory.
This novel multivalued storage is compatible with traditional handicraft fully based on traditional logic technology.This structure is separated storage characteristics based on nanocrystalline electronics and is realized many-valued storage.Storer adopts thermoelectron to be injected to programming mode, is erase mode with the FN tunnelling, distinguishes the four kinds of store statuss in " 00 " " 01 " " 10 " " 11 " with the read current size, thereby can realize many-valued storage under same area, makes memory space increase twice.It is minimum to have a chip area based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure, and the technology simple and flexible, read-write voltage is low, the programming time is short, memory window is big, storage time is long and plurality of advantages such as integration density height.Many-valued structure substitutes the nano-crystal memory of traditional monodrome storage, under the condition of fixed-area technique for fixing, realizes many-valued storage by adjusting mode of operation, thereby under same area, memory space is doubled, and has saved cost greatly.
Those skilled in the art can also carry out various modifications to above content under the condition that does not break away from the definite the spirit and scope of the present invention of claims.Therefore scope of the present invention is not limited in above explanation, but determine by the scope of claims.
Claims (8)
1. the storage means based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure is characterized in that, described method comprises:
Apply the 4th voltage, tertiary voltage and first voltage respectively at word line, bit line and source end line, with stores binary data 10 in the storer of choosing based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure;
Apply the 4th voltage, first voltage and tertiary voltage respectively at word line, bit line and source end line, with stores binary data 01 in the storer of choosing based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure;
Earlier apply the 4th voltage, tertiary voltage and first voltage respectively at word line, bit line and source end line based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure; Apply the 4th voltage, first voltage and tertiary voltage respectively at word line, bit line and source end line then, with stores binary data 00 in the storer of choosing based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure; Or
Apply the 5th voltage, first voltage and first voltage respectively at word line, bit line and source end line, with stores binary data 11 in the storer of choosing based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure.
2. the storage means of the many-valued non-volatility memorizer based on nanocrystalline floating gate structure as claimed in claim 1, it is characterized in that: described first voltage is 0V, tertiary voltage is 3.5V, and the 4th voltage is 6V, and the 5th voltage changes successively according to following magnitude of voltage :-10V ,-12V and-14V.
3. one kind is read data storing method, it is characterized in that, described method comprises:
Apply tertiary voltage, second voltage and first voltage respectively at word line, bit line and source end line, to read the binary data 10,01,10 or 11 of the storage means storage of using the many-valued non-volatility memorizer based on nanocrystalline floating gate structure as claimed in claim 1 or 2 based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure.
4. the data storing method that reads as claimed in claim 3 is characterized in that described second voltage is 0.8V.
5. the storage means based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure is characterized in that, comprising:
Apply the 4th voltage, tertiary voltage and first voltage respectively at grid, drain electrode and source electrode, with stores binary data 10 in based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure;
Apply the 4th voltage, first voltage and tertiary voltage respectively at grid, drain electrode and source electrode, with stores binary data 01 in based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure;
Earlier apply the 4th voltage, tertiary voltage and first voltage respectively at grid, drain electrode and source electrode based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure; Apply the 4th voltage, first voltage and tertiary voltage respectively at grid, drain electrode and source electrode then, with stores binary data 00 in based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure; Or
Apply the 5th voltage, first voltage and first voltage respectively at grid, drain electrode and source electrode, with stores binary data 11 in based on the metal-oxide-semiconductor field effect transistor of nanocrystalline floating gate structure based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure.
6. the storage means of the metal-oxide-semiconductor field effect transistor based on nanocrystalline floating gate structure as claimed in claim 5, it is characterized in that: first voltage is 0V, tertiary voltage is 3.5V, and the 4th voltage is 6V, and the 5th voltage changes successively according to following magnitude of voltage :-10V ,-12V and-14V.
7. one kind is read data storing method, it is characterized in that,
Apply tertiary voltage, second voltage and first voltage respectively at grid, drain electrode and source electrode, use as binary data 00,01,10 or 11 that the storage means of claim 5 or 6 described metal-oxide-semiconductor field effect transistors based on nanocrystalline floating gate structure is stored to read based on the many-valued non-volatility memorizer of nanocrystalline floating gate structure.
8. the data storing method that reads as claimed in claim 7 is characterized in that second voltage is 0.8V.
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