CN102111074A - Method and device for reducing switching loss of phase-shifting full-bridge converter - Google Patents

Method and device for reducing switching loss of phase-shifting full-bridge converter Download PDF

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CN102111074A
CN102111074A CN 201110078847 CN201110078847A CN102111074A CN 102111074 A CN102111074 A CN 102111074A CN 201110078847 CN201110078847 CN 201110078847 CN 201110078847 A CN201110078847 A CN 201110078847A CN 102111074 A CN102111074 A CN 102111074A
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resistor
operational amplifier
terminal
end
inverting
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CN 201110078847
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CN102111074B (en )
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丘东元
何文志
张桂东
张波
戴钰
林仕立
段振涛
肖文勋
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华南理工大学
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion
    • Y02B70/14Reduction of losses in power supplies
    • Y02B70/1416Converters benefiting from a resonance, e.g. resonant or quasi-resonant converters
    • Y02B70/1433Converters benefiting from a resonance, e.g. resonant or quasi-resonant converters in galvanically isolated DC/DC converters
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion
    • Y02B70/14Reduction of losses in power supplies
    • Y02B70/1491Other technologies for reduction of losses, e.g. non-dissipative snubbers, diode reverse recovery losses minimisation, zero voltage switching [ZVS], zero current switching [ZCS] or soft switching converters

Abstract

The invention provides a method and a device for reducing the switching loss of a phase-shifting full-bridge converter. The device comprises a resonant capacitor voltage detection unit, a judgment unit, a control arithmetic unit and a signal production unit, wherein the signal production unit comprises a phase-shifting signal production unit, a dead zone signal production unit and a phase-shifting trigger pulse production unit. The method comprises the following steps of: detecting resonant capacitor voltage signals by the resonant capacitor voltage detection unit; judging the size of the voltage signals by the judgment unit; calculating the optimum dead zone time of an upper switching tube and a lower switching tube of the same bridge arm in two bridge arms by the control arithmetic unit; and producing phase-shifting trigger pulse signals by the signal production unit to ensure that the withstand voltage is the lowest when the switching tubes are switched on, so the aim of reducing the switching loss is achieved. A phase-shifting control technique which is fixed relative to the dead zone time can provide the optimum dead zone time, and according to the technique, the switching loss is reduced to the lowest, the soft switching range is enlarged, and the working efficiency of the converter is improved; and the phase-shifting control technique is particularly suitable for high-power phase-shifting full-bridge converters.

Description

降低移相全桥变换器开关损耗的方法及装置 The method of reducing the full-bridge converter switching losses and shifting means

技术领域 FIELD

[0001] 本发明涉及直流DC-DC变换器变换技术领域,特别是涉及降低移相全桥变换器开关损耗的方法及装置。 [0001] The present invention relates to the technical field current converted DC-DC converter, particularly to a method and apparatus for full-bridge converter switching loss reduction shift.

背景技术 Background technique

[0002] 随着全桥ZVS移相技术的推出,该技术在大功率领域中得到了广泛的应用。 [0002] With the introduction of the phase-shifted ZVS full-bridge technology, this technology has been widely applied in the field of power. 通过在移相全桥变换器中引入谐振电感和死区时间,使开关管实现了零电压开通,但开关管在轻载时很难实现零电压开通,仍然存在较大的开关损耗,不适用于负载和电源电压波动范围较大的场合。 By introducing resonant inductor and dead time in the phase-shifted full bridge converter, so that switch achieve ZVS, the switch is difficult to achieve ZVS at light loads, switching loss is still large, NA the load and the supply voltage a larger range of applications.

[0003] 轻载情况下的变换器滞后臂很难实现ZVS,这与谐振电感、谐振电容大小和开关管触发脉冲的死区时间有关系,而超前臂很容易实现ZVS,这是因为超前臂上开关管关断时, 输出滤波器也参于谐振,有足够的大的电流完成对超前臂漏上两个谐振电容的充放电。 [0003] converter under light load conditions is difficult to achieve the ZVS lagging arm, this dead time associated with the resonant inductor, resonant capacitor and the transistor size of the trigger pulse, and the ZVS-leg easily achieved, since the ultra forearm switch off the tube, but also participate in the resonant output filter, there is a large enough current to complete the charging and discharging of the two-leg drain resonant capacitor.

[0004] 导致这种问题的根本原因是PSFB-ZVS变换器拓扑结构本身的缺陷,存在软开关实现的负载范围和占空比丢失等问题,影响这些问题的因素是谐振电感和谐振电容。 Root cause [0004] The cause of this problem is PSFB-ZVS converter topology of the defect itself, and there is a load range of the duty cycle to achieve soft switching loss and other problems, these problems are factors resonant inductor and resonant capacitor. 通常采用的死区时间是固定的,当谐振参数发生变化时,变换器滞后臂管在轻载甚至重载时也不能完成零电压开通。 Usually dead time is fixed, when the resonant parameters change, the converter in light load arm pipe lagging heavy load can not be completed even ZVS.

发明内容 SUMMARY

[0005] 本发明的目的在于克服现有技术存在的上述不足,提供降低移相全桥变换器开关损耗的方法及装置,具体技术方案如下。 [0005] The object of the present invention is to overcome the above disadvantages of the prior art, provides a method and apparatus for reducing the full-bridge converter switching losses shifting, specific technical solutions as follows.

[0006] 降低移相全桥变换器开关损耗的装置,其包括:顺次连接的谐振电容电压检测单元、判断单元、控制运算单元和信号发生单元,信号发生单元包括移相信号发生单元、死区信号发生单元和移相触发脉冲发生单元;谐振电容电压检测单元检测谐振电容电压信号并转化此信号送至判断单元;判断单元判断谐振电容电压检测单元转换的信号所属类型;控制运算单元根据判断单元判断信号类型计算出最佳死区时间;信号发生单元输出控制运算单元所计算出的移相全桥两桥臂上下管开关的死区时间的移相触发脉冲。 [0006] means to reduce shifting full bridge converter switching losses phases, comprising: a resonant capacitor connected to the voltage detection means sequentially, determination unit, a control arithmetic unit and a signal generating unit, signal generating means comprises a shift signal generation unit, dead area signal generating unit and a phase shift trigger pulse generating means; means for detecting the resonant capacitor voltage detecting the resonant capacitor voltage signal and converts the signal to the determination unit; determining unit determines the type of signal belongs resonant capacitor voltage detecting unit conversion; control arithmetic unit according to the judgment a signal type determination unit calculates the optimum dead time; a signal generation control unit outputs the calculated phase arithmetic unit shift dead-time phase shift full bridge two bridge arm switch trigger pulse tube.

[0007] 上述的降低移相全桥变换器开关损耗的装置中,所述谐振电容电压检测单元包括与移相全桥两桥臂下管两个谐振电容并联的第一串联电阻和第二串联电阻,两个电平转换电路和采样存储单元;第一串联电阻包括串联的第一分压电阻和第二分压电阻,第二串联电阻包括串联的第三分压电阻和第四分压电阻;第一分压电阻一端接地,另一端与第二分压电阻一端连接;所述第三分压电阻一端接地,另一端与第四分压电阻一端连接。 Means [0007] The reduction in phase-shifted full bridge converter switching losses in the resonant capacitor voltage detecting means comprises a phase shifter and a first series resistance of the tube two parallel resonant capacitor lower arms full bridge two bridges and second series resistance, two level conversion circuits and the sample storage unit; a first series resistor comprises a first voltage dividing resistor and the second dividing resistor connected in series, second series resistor comprises a third and a fourth voltage dividing resistor voltage dividing resistor connected in series ; first voltage dividing resistor connected to ground, and the other end connected to one end of a second voltage dividing resistor; said third voltage dividing resistor connected to ground, and the other end connected to one end of the fourth voltage dividing resistor.

[0008] 上述的降低移相全桥变换器开关损耗的装置中,所述的电平转换电路包括两个级联运放电路:第一级联运放电路和第二级联运放电路;其中第一级联运放电路包括第一运放、第二运放、第一运放反相端输入电阻、第一运放正相端输入电阻、第一反馈可调电阻、第一运放反相端落地电阻、第二运放反相端输入电阻、第二运放正相端输入电阻、第二反馈电阻和第二运放反相端落地电路;所述第二级联运放电路包括第三运放、第四运放、第三运放反相端输入电阻、第三运放正相端输入电阻、第三反馈可调电阻、第三运放反相端落地电路、第四运放反相端输入电阻、第四运放正相端输入电阻、第四反馈电阻和第四运放反相端接地电阻。 [0008] The reduction in phase shifting full bridge converter device switching losses, the level conversion circuit includes a two-stage amplifier circuit transport: a first stage and a second stage amplifier circuit intermodal transport amplifier circuit; wherein the discharge circuit includes a first stage transport the first operational amplifier, a second operational amplifier, a first operational amplifier inverting input terminal of a resistor, a first terminal of the op amp with an input resistor, a first feedback variable resistor, the first operational amplifier floor inverting terminal resistor, a second terminal of the inverting operational amplifier input resistor, a second positive input of op-resistor, a second feedback resistor and the inverting terminal of the second operational amplifier circuit ground; the second stage amplifier circuit intermodal It includes a third operational amplifier, a fourth operational amplifier, the inverting terminal of the third operational amplifier input resistor, a third operational amplifier inverting terminal input resistor, the third feedback variable resistor, a third ground terminal of the inverting operational amplifier circuit, a fourth operational amplifier inverting input terminal of a resistor, the fourth operational amplifier inverting terminal input resistor, a feedback resistor and a fourth op amp inverting the fourth end of the resistor.

[0009] 上述的降低移相全桥变换器开关损耗的装置中,第一级联运放电路中,第一运放反相端输入电阻一端、第一分压电阻一端和第二分压电阻一端连接,第一运放反相端输入电阻另一端、第一反馈可调电阻一端和第一运放的反相输入端连接,第一运放正相端输入电阻一端、第一运放反相端落地电阻一端和第一运放的正相输入端连接,第一运放反相端落地电阻另一端接地,第一运放正相端输入电阻另一端连接参考电压Vrefl,第二运放反相端输入电阻一端、第一运放的输出端与第一反馈可调电阻另一端连接,第二运放反相端输入电阻另一端、第二反馈电阻一端和第二运放的反相输入端连接,第二运放正相端输入电阻一端、第二运放反相端落地电路一端和第一运放的正相输入端连接,第二运放反相端落地电路另一端接地,第二运放正相端输入电阻另一端 Means [0009] The reduction in phase-shifted full bridge converter switching losses, the first-stage transport discharge circuit, the first operational amplifier negative input end of a resistor, a first voltage dividing resistor and the second dividing resistor end One end of the connection, a first operational amplifier inverting input terminal of the other end of the resistor, a first feedback resistor adjustable inverting input terminal and an end of the first operational amplifier is connected to a first input terminal of the op amp with one end of the resistor, the first operational amplifier trans floor-phase terminal end of a resistor and a first operational amplifier non-inverting input terminal connected to the ground terminal of the first operational amplifier inverting other end of the resistor, the first operational amplifier positive phase input terminal of the other end of the resistor connected to the reference voltage Vrefl, a second operational amplifier the negative input end of a resistor, the output terminal of the first operational amplifier and the other end of the first feedback variable resistor, the second operational amplifier inverting input terminal of the other end of the resistor, a second feedback resistor and an end of the second inverting operational amplifier input terminal, a second input terminal of the op amp with an end resistor, a second terminal of the inverting operational amplifier circuit ground at one end and the first operational amplifier non-inverting input terminal, a second terminal of the inverting operational amplifier circuit other end of the floor, a second operational amplifier positive input terminal of the other end of the resistor with 接另一参考电压Vref2,所述第二级联运放电路中,第三运放反相端输入电阻一端、第三分压电阻一端和第四分压电阻一端连接,第三运放反相端输入电阻另一端、第三反馈可调电阻一端和第三运放的反相输入端连接,第三运放正相端输入电阻一端、第三运放反相端落地电路一端和第三运放的正相输入端连接,第三运放反相端落地电路另一端接地,第一运放正相端输入电阻另一端连接参考电压Vrefl ',第四运放反相端输入电阻一端、第一运放的输出端与第三反馈可调电阻另一端连接,第四运放反相端输入电阻另一端、第四反馈电阻一端和第二运放的反相输入端连接, 第四运放正相端输入电阻另一端连接参考电压Vref2',第二反馈电阻另一端与第二运放的输出端连接,第四反馈电阻另一端与第四运放的输出端连接。 Then another reference voltage Vref2, the second transport stage amplifier circuit, a third operational amplifier negative input end of a resistor, a third end and a fourth voltage dividing resistor voltage dividing resistors connected at one end, a third inverting operational amplifier the other end of the resistor input terminal, an inverting input terminal of the third feedback variable resistor and one end of the third operational amplifier is connected to the third input terminal of the op amp with one end of a resistor, the inverting terminal of the third operational amplifier circuit and one end of the third transport floor amp positive input is connected to the inverting terminal of the third operational amplifier circuit other end of the floor, the first operational amplifier positive input terminal of the other end of the resistor with a reference voltage connected Vrefl ', the fourth operational amplifier negative input end of a resistor, a first an op amp's output terminal of the third feedback resistor connected to the other end of the adjustable, the fourth operational amplifier inverting input terminal of the other end of the resistor, and a fourth feedback resistor one end of the second operational amplifier inverting input terminal connected to a fourth operational amplifier positive phase input terminal of the other end of the resistor connected to the reference voltage Vref2 ', a second feedback resistor and the other end of the second operational amplifier connected to the output, and the fourth feedback resistor and the other end of the fourth operational amplifier connected to the output.

[0010] 上述的降低移相全桥变换器开关损耗的装置中,采用存储单元接收电平转换电路的信号进行存储,为判断单元提供数字信号,采用存储单元的一个接收端与第二运放的输出端连接,另一个接收端与第四运放的输出端连接。 Means [0010] The reduction in phase-shifted full bridge converter switching losses, the use of the reception signal level conversion circuit is a storage unit for storing, providing a digital signal for the determination unit, a storage unit employed in the receiving end of a second operational amplifier an output terminal connected to another receiving terminal connected to the output of the fourth operational amplifier.

[0011] 上述的降低移相全桥变换器开关损耗的装置中,采样存储单元和判断单元、控制运算单元和信号发生单元采用TI公司的TMS320F2812DSP实现。 Means [0011] The reduction in phase-shifted full bridge converter switching losses, the sampling determination unit and the storage unit, the control arithmetic unit and a signal generating unit using TI's TMS320F2812DSP achieved.

[0012] 利用上述装置降低移相全桥变换器开关损耗的方法,包括如下步骤: [0012] The method of reducing the full-bridge converter switching losses by using the shift means, comprising the steps of:

[0013] (1)谐振电容电压检测单元检测转换谐振电容电压信号后送至判断单元; [0013] (a) detecting means for detecting the resonant capacitor voltage converted signal to the resonant capacitor voltage determining means;

[0014] (2)利用判断单元判断由检测单元检测出来的移相全桥变换器中两桥臂下管谐振电容电压信号的类型; Phase full-bridge converter type tube resonant capacitor voltage signal in the two shift arm [0014] (2) using the determination unit determines that the detected by the detection unit;

[0015] (3)控制运算单元根据判断单元判断的类型分别实时计算两桥臂中同一桥臂上下两开关管的最佳死区时间;所述死区时间包括移相全桥的同一桥臂中超前臂和滞后臂上下两个开关管间的死区时间,两个桥臂的最佳死区时间独立产生; [0015] (3) respectively, the control arithmetic unit calculates in real time the optimal dead time two bridge arm at the same bridge arm of the two switch according to the type determining unit determines; dead time of the same bridge arm comprises a phase-shifted full bridge Super forearm and arm lower dead time lag between the two switches, the optimum dead time generating two separate arm;

[0016] (4)经信号发生单元产生的死区时间为最佳死区时间的移相触发脉冲使开关管开通时承受电压最小,从而降低开关管的开关损耗。 [0016] (4) by the dead time signal generating unit generates the optimum phase shift dead time so that the withstand voltage of the trigger pulse when the minimum opening switch, thereby reducing switching loss of the switch.

[0017] 上述的方法中,步骤O)中判断单元判断两桥臂下管谐振电容电压的大小,然后进行分类;步骤(3)中控制运算单元根据判断单元对两桥臂下管谐振电容电压大小的分类,实时计算出两桥臂中同一桥臂上下两开关管的最佳死区时间。 [0017] The above-described method, step O) determined size tube of the resonant capacitor voltage unit determines that two bridge arms, and then classified; Step (3) the control arithmetic unit resonant capacitor voltage according to the judgment unit of the two-arm tube size classification, calculated in real time the optimal dead time in the same two-arm bridge arm of the two-switch.

[0018] 上述的方法中,步骤中死区信号发生单元产生的死区信号是一系列死区时间为最佳死区时间的脉冲,通过将该系列脉冲注入到所述移相脉冲发生单元中,产生实时可调且死区时间最佳的移相脉冲信号。 [0018] In the above method, the step deadband signal generating unit generates a deadband signal is a series of pulses optimal dead time dead time, is injected into the phase shift pulse generating unit through the series of pulses generating in real time an adjustable dead time and the best phase shifting pulse signal.

[0019] 上述的方法中,步骤(4)移相脉冲发生单元通过协同控制,控制最佳死区时间可调和控制触发脉冲移相。 [0019] In the above-described method, step (4) the phase shift pulse generating means controlled by the cooperative control optimal dead time adjustable trigger pulse and phase shift control.

[0020] 上述的方法中,步骤(1)采样存储规律是,单周期内正常工作状态下,当超前臂开关管关断后,开始采样,并计时,直到同桥臂另一个开关管都开通,时长△ t,采样点数50 ; 开关单周期采样持续1/6个工频周期,即一个工频周期内共6次采样;一个工频周期存储数据全部更新一次。 [0020] In the above-described method, step (1) sample storage rule is, under normal operating conditions in a single cycle, when the ultra forearm switch turns off, start sampling, and time, with the arm until the other switches are opened , duration △ t, 50 sampling points; single switching cycle of the sampling frequency cycle duration 1/6, i.e., a total of six times the sampling frequency cycle; all of a frequency cycle data storing updated.

[0021] 上述的方法中,死区信号发生单元,采用TI公司的TMS320F2812DSP,死区信号发生单元根据谐振电容电压信号分类计算出大小为最佳死区时间、频率为开关频率的一系列脉冲。 [0021] The above-described method, the dead-signal generating unit, using TI's TMS320F2812DSP, dead signal generating unit calculates the optimum size of a series of pulses dead time, the switching frequency of the resonant capacitor voltage according to the signal classification.

[0022] 与现有技术相比,本发明根据开关管上电压变化趋势,通过实时调整超前桥臂和滞后桥臂的死区时间,无须过分关注谐振参数是否匹配问题,扩大软开关的实现范围,使开关管的开关损耗最小,达到降低开关管损耗目的,提高变换器的效率。 [0022] Compared with the prior art, the present invention according to the change of the voltage switch, by real-time adjustment of the dead time the leading leg and the lagging leg, without undue concern resonance parameters match, of widening the range of soft-switching to achieve the switch switching loss is minimized to reduce the switch loss purposes, to improve the efficiency of the converter. 本发明通过谐振电容电压检测单元检测的谐振电容电压信号,然后由判断单元来判断该电压信号的大小,再由控制运算单元计算同桥臂两开关管的最佳死区时间,经信号发生单元产生的最佳死区时间的触发脉冲使开关管开通时承受电压最小,从而达到降低开关损耗的目的。 The present invention is resonant capacitor voltage signal by the resonant capacitor voltage detection unit, and the determining means determines the magnitude of the voltage signal, and then the optimum deadtime with two bridge arm switch by the control arithmetic unit calculates, by the signal generating unit trigger pulse generating optimal dead time that the withstand voltage of the switch opened the minimum, so as to achieve the purpose of reducing the switching loss.

附图说明 BRIEF DESCRIPTION

[0023] 图1是本发明的控制方法的流程图。 [0023] FIG. 1 is a flowchart illustrating a control method of the present invention.

[0024] 图2是谐振电容电压检测单元的电路图。 [0024] FIG. 2 is a circuit diagram of the resonant capacitor voltage detection unit.

[0025] 图3是判断单元程序流程图。 [0025] FIG. 3 is a flowchart of a program determination unit.

[0026] 图如和图4b是超前臂开关管开关的最佳死区时间波形图。 [0026] As FIG. 4b is a timing and waveform diagram of the switch tube optimal dead-leg switching.

[0027] 图如和图4d是滞后臂开关管开关的最佳死区时间波形图。 [0027] As FIGS. 4d and FIG optimum dead time is a waveform diagram of the hysteresis switch arm switch.

[0028] 图5是固定死区时间时的驱动电压和滞后臂下管电压波形图。 [0028] FIG. 5 is a voltage waveform chart of driving voltage of the tube is fixed dead time and lag arm.

[0029] 图6是本发明采用死区时间实时调整后驱动电压和滞后臂下管电压波形图。 [0029] FIG. 6 is a waveform diagram of the present invention using the tube voltage lower driving voltage and the lagging arm dead time adjusted in real time.

具体实施方式 detailed description

[0030] 下面结合附图对本发明的实施做进一步说明,但本发明的实施和保护范围不限于此。 [0030] The following embodiments in conjunction with the accompanying drawings further illustrate the present invention, but the embodiment of the present invention and the scope is not limited thereto.

[0031] 如图1,降低移相全桥变换器开关损耗的装置,其包括:顺次连接的谐振电容电压检测单元、判断单元、控制运算单元和信号发生单元,信号发生单元包括移相信号发生单元、死区信号发生单元和移相触发脉冲发生单元;谐振电容电压检测单元检测谐振电容电压信号并转化此信号送至判断单元;判断单元判断谐振电容电压检测单元转换的信号所属类型;控制运算单元根据判断单元判断信号类型计算出最佳死区时间;信号发生单元输出控制运算单元所计算出的移相全桥两桥臂上下管开关的死区时间的移相触发脉冲。 [0031] FIG 1, full-bridge converter means to reduce the switching loss shift, comprising: a resonant capacitor connected to the voltage detection means sequentially, determination unit, a control arithmetic unit and a signal generating unit, signal generating means comprises a shift signal generating unit, signal generating means and dead phase trigger pulse generating means; means for detecting the resonant capacitor voltage detecting the resonant capacitor voltage signal and converts the signal to the determination unit; your judgment unit judges the type of the resonant capacitor voltage detecting signal conversion means; and a control computing means calculates the optimum dead time is determined according to the signal type judgment unit; generation control unit outputs the signal phase calculation means calculated shift dead-time phase shift full bridge two bridge arm switch trigger pulse tube.

[0032] 如图2,所述谐振电容电压检测单元包括与移相全桥两桥臂下管两个谐振电容(c3、C4)并联的第一串联电阻和第二串联电阻,两个电平转换电路和采样存储单元;第一串联电阻包括串联的第一分压电阻Rdl和第二分压电阻Rd2,第二串联电阻包括串联的第三分压电阻I^d3和第四分压电阻Rd4;第一分压电阻Rdl—端接地,另一端与第二分压电阻Rd2—端连接;所述第三分压电阻Rd3 —端接地,另一端与第四分压电阻Rd4 —端连接。 [0032] As shown in FIG 2, the resonant capacitor voltage detecting means comprises two tubular resonant capacitor (C3, C4) in parallel with the first series resistor and a second resistor connected in series with the two phase-shifted full bridge arm, two levels conversion circuit and sampling a storage unit; a first series resistor voltage dividing resistors comprising a first and second voltage dividing resistors Rdl Rd2 in series, second series resistor voltage dividing resistor comprises a third I ^ d3 and the fourth voltage dividing resistors connected in series Rd4 ; Rdl- a first voltage dividing resistor is grounded, and the other end to the second end of the dividing resistor Rd2-; said third voltage dividing resistor Rd3 - grounded, the other end of the fourth voltage-dividing resistor Rd4 - terminal.

[0033] 所述的电平转换电路包括两个级联运放电路:第一级联运放电路和第二级联运放电路;其中第一级联运放电路包括第一运放A1、第二运放A2、第一运放反相端输入电阻队、 第一运放正相端输入电阻&、第一反馈可调电阻R3、第一运放反相端落地电阻R4、第二运放反相端输入电阻&、第二运放正相端输入电阻&、第二反馈电阻R7和第二运放反相端落地电路述第二级联运放电路包括第三运放、第四运放、第三运放反相端输入电阻R/、第三运放正相端输入电阻IV、第三反馈可调电阻IV、第三运放反相端落地电路R/、第四运放反相端输入电阻IV、第四运放正相端输入电阻IV、第四反馈电阻R/和第四运放反相端接地电阻IV。 Level shifter circuit [0033] of the amplifier circuit comprises two transport stages: a first stage and a second stage amplifier circuit intermodal transport amplifier circuit; wherein the discharge circuit includes a first stage transport the first operational amplifier A1, The second operational amplifier A2, a first operational amplifier inverting input terminal of the resistance force, a first op-phase terminal & input resistor, a first adjustable feedback resistor R3, a ground terminal of the first operational amplifier inverting resistor R4, a second operation resistance & amp inverting input terminal, a second positive input of the op amp & resistor, a second feedback resistor R7 and the ground terminal of the second operational amplifier circuit inverting said second amplifier circuit comprises a third transport stage operational amplifier, a fourth operational amplifier, the inverting terminal of the third operational amplifier input resistor R /, the third input terminal of the op amp with resistive IV, IV third feedback variable resistor, the inverting terminal of the third operational amplifier circuits floor R /, the fourth operational amplifier inverting input terminal of resistor IV, the fourth operational amplifier inverting terminal input resistor IV, fourth feedback resistor R / inverting operational amplifier and a fourth end of the resistor IV.

[0034] 第一级联运放电路中,第一运放反相端输入电阻R1 —端、第一分压电阻Rdl —端和第二分压电阻Rd2 —端连接,第一运放反相端输入电阻R1另一端、第一反馈可调电阻R3 —端和第一运放A1的反相输入端连接,第一运放正相端输入电阻& 一端、第一运放反相端落地电阻R4 —端和第一运放A1的正相输入端连接,第一运放反相端落地电阻R4另一端接地,第一运放正相端输入电阻&另一端连接参考电压VMfl,第二运放反相端输入电阻& 一端、第一运放A1的输出端与第一反馈可调电阻R3另一端连接,第二运放反相端输入电阻R5另一端、第二反馈电阻R7 一端和第二运放A2的反相输入端连接,第二运放正相端输入电阻& 一端、第二运放反相端落地电路& 一端和第一运放A1的正相输入端连接,第二运放反相端落地电路&另一端接地,第二运放正相端输入电阻&另一端连接另一参 [0034] The first transport stage amplifier circuit, the first operational amplifier inverting input terminal of the resistor R1 - terminal, a first voltage dividing resistance Rdl - end and a second voltage dividing resistor Rd2 - terminal is connected, a first inverting operational amplifier the other end of the input end of the resistor R1, the first adjustable feedback resistor R3 - an inverting input terminal and the first operational amplifier A1 is connected to a first input terminal of the op amp with one end of a resistor &, the first operational amplifier inverting terminal landing resistor R4 - end and a first operational amplifier A1 is connected to the positive input terminal, a first operational amplifier inverting terminal floor to the other end of the resistor R4, a first operational amplifier inverting terminal input resistor connected to the reference voltage and the other end & VMfl, a second operation resistance & amp inverting input terminal at one end, the output of the first amplifier A1 and the operation of the first feedback resistor R3 is connected to the other end of the adjustable, a second operational amplifier inverting input terminal of the other end of the resistor R5, a second end and a second feedback resistor R7 two inverting input of operational amplifier A2 is connected to the second input terminal of the op amp with one end of a resistor &, the inverting terminal of the second operational amplifier and a first end of the ground circuit & operational amplifier A1 is connected to the positive input terminal, a second operation & amp inverting terminal of the other end to the ground circuit, a second input terminal of the op amp with another end connected to another resistor & parameter 电压Vref2,所述第二级联运放电路中,第三运放反相端输入电阻R/ —端、第三分压电阻I?d3 —端和第四分压电阻Rd4 —端连接,第三运放反相端输入电阻R1'另一端、第三反馈可调电阻IV —端和第三运放A3的反相输入端连接,第三运放正相端输入电阻IV —端、第三运放反相端落地电路R4' 一端和第三运放A3的正相输入端连接,第三运放反相端落地电路R/另一端接地,第一运放正相端输入电阻&另一端连接参考电压Vrefl',第四运放反相端输入电阻IV —端、第一运放A1的输出端与第三反馈可调电阻R/另一端连接,第四运放反相端输入电阻IV另一端、第四反馈电阻R/ —端和第二运放^的反相输入端连接,第四运放正相端输入电阻IV 另一端连接参考电压Vref2',第二反馈电阻R7另一端与第二运放的输出端连接,第四反馈电阻R/另一端与第四运放的输出端连接。 Voltage Vref2, the second transport stage amplifier circuit, the third terminal of the inverting operational amplifier input resistor R / - terminal, the third voltage-dividing resistor I d3 -? End and a fourth voltage dividing resistor Rd4 - end connection, the three terminal op amp inverting input resistor R1 'other end, the third feedback resistor adjustable IV - terminal and the third operational amplifier A3 is connected to an inverting input terminal, a third input terminal of the op amp with resistive IV - end, the third inverting terminal of operational amplifier circuits floor R4 'and one end of the third operational amplifier A3 is connected to the positive-phase input terminal, an inverting terminal of the third operational amplifier circuits floor R / other end, a first positive input of the op amp other end of the resistor & connected to the reference voltage Vrefl ', the fourth terminal of the inverting operational amplifier input resistor IV - terminal, the output terminal of the first amplifier A1 and the third operational feedback variable resistor R / connect the other end, the fourth terminal of the inverting operational amplifier input resistor IV the other end, the fourth feedback resistor R / - ^ end and a second operational amplifier inverting input terminal, a fourth input terminal of the op amp phase IV other end of resistor connected to the reference voltage Vref2 ', the other end of the second feedback resistor R7 a second operational amplifier connected to the output, the fourth feedback resistor R / and the other end of the fourth operational amplifier connected to the output.

[0035] 移相全桥变换器通过引入谐振电感,在开关管都关断的死区时间内,利用谐振电感Lr和谐振电容(C1-C4)的电压不阶跃性,实现零电压开通。 [0035] The phase-shifted full bridge converter by introducing a resonant inductor in the dead time switches are turned off by the voltage resonant inductor Lr and the resonant capacitor (C1-C4) not stepwise, to achieve ZVS. 当变换器处于轻载时,Lr不能完成对C;的充放电,因此滞后管不能实现ZVS导通;如果谐振电感k和C;参数不匹配, 那么电路可能存在潜在路径(潜电路),出现非正常的工作模态,就会导致滞后臂的开关管很难实现ZVS。 When the converter is lightly loaded, Lr of C is not completed; charge and discharge, and therefore can not achieve ZVS lagging conductive; if k resonant inductance, and C; parameters do not match, then there may be a potential path circuit (circuit potential), there non-normal operating mode, will cause the switch arm lagging difficult to achieve ZVS. 以上情况都会因开关管不能实现ZVS而增大开关损耗。 Such condition can not be achieved due to switch ZVS switching loss increases.

[0036] 开关损耗由下述表达式决定: [0036] The switching losses determined by the following expression:

[0037] Pk = \^ipucdt : Δ t时间内开关损耗。 [0037] Pk = \ ^ ipucdt: Δ t time switching losses.

[0038] ip :初级谐振电感电流。 [0038] ip: the primary resonance inductor current.

[0039] mCJ谐振电容的电压。 [0039] mCJ resonant capacitor voltage.

[0040] At同桥臂开关管关断到另一开关管开通的时间。 [0040] At the same bridge arm switch is turned off to another time switch opened.

[0041] 本发明的方案是,不管电路处于轻载还是电路谐振参数不匹配状况下,在滞后臂开关管关断之前,检测谐振电容C3电压&3 ;在滞后臂关断后,初级电感电流过零时,检测谐振电容C4电压&4,分别判断&3、所处的状态类型,实时调节同桥臂开关管死区时间,使开关管开通时的电压最小,此时与此开关管并联的结电容电流不会回升,即保证开关损耗最小。 [0041] The embodiment of the present invention, the matter circuit is lightly loaded or the circuit resonators parameters do not match condition, before the lag arm switch is turned off, the detection of the resonant capacitor C3 voltage & 3; hysteresis arm turned off, the primary inductor current zero detection voltage resonant capacitor C4 & 4, & 3 are determined, which state the type of real-time adjustment with the bridge arm switch dead time, so that the minimum voltage at the opening switch, then the junction capacitance in parallel with this switch tube current will not rise, i.e. guaranteed minimum switching losses.

[0042] 图1是本发明的控制方法的流程图。 [0042] FIG. 1 is a flowchart illustrating a control method of the present invention. 采样存储单元和判断单元、控制运算单元和信号发生单元采用TI公司的TMS320F2812DSP。 Sampling and storing unit judging unit, arithmetic unit and control signal generation unit using TI's TMS320F2812DSP. 检测单元检测移相全桥变换器两桥臂下管谐振电容(C3、C4)电压,电平转换电路将电压转换为0〜3V,并送至TMS320F2812 DSP的A/ D接口,启动采样,读取AdcRegs. RESULTxo采样存储规律是,单周期内正常工作状态下,当超前臂开关管关断后,开始采样,并计时、,直到另一对开关管都开通,时长At,采样点数50 ;开关单周期采样持续1/6个工频周期,即一个工频周期内共6次;一个工频周期存储数据全部更新一次。 Detecting means for detecting a phase shift full-bridge resonant capacitor A pipe (C3, C4) a voltage level conversion circuit that converts a voltage 0~3V, and sent down converter TMS320F2812 DSP two arm / D interfaces, sampling start reading take AdcRegs RESULTxo sampling rule is stored, under normal operating conditions in a single cycle, when the ultra forearm switch turns off, start sampling, and another pair of timing ,, until switches are opened, the duration at, 50 sampling points; switch sustained single cycle 1/6 the sampling frequency cycle, i.e., a cycle frequency 6 times; a cycle frequency of all the stored data is updated.

[0043] dsp中程序判断单元判断谐振电容c3、c4的电压%和% : [0043] dsp program determining unit determines the resonant capacitor c3, c4 and voltage%%:

[0044] (1)判断滞后臂谐振电容c3电压的%,在滞后臂关断前,判断&3大小所属类型; [0044] (1) Analyzing the lagging leg% c3 voltage resonant capacitor, before the lagging leg off, size 3 & determines their type;

[0045] (2)判断超前臂谐振电容c4电压的%,在滞后开关管关断后,判断ip下降至零时刻的谐振电容C4电压&4大小所属类型; [0045] (2) determines the resonant capacitor c4%-leg voltage, the hysteresis switch is turned off, decreased to Analyzing ip voltage resonant capacitor C4 4 & magnitude relevant to the type of time zero;

[0046] 参见图3,当谐振电容电压「C, >Q时,将其判为I类;谐振电容电压^; =Q,将其判为II类;进一步判断,若谐振电容电压& >|,则将其判为III类,若<·^,则将 [0046] Referring to FIG 3, when the resonant capacitor voltage "C,> Q, then it is judged as a Class I; resonant capacitor voltage ^; = Q, it is judged as Class II; further judges, if the resonant capacitor voltage &> | , it is judged as class III, if <* ^, then

其判为IV类。 It ruled Class IV. 控制运算单元根据前一步判断单元实时判断的结果(谐振电容C3、C4电压vC3、电压所属类型),分别计算出滞后臂和超前臂最佳死区时间。 Analyzing the results of step (resonant capacitor C3, C4 voltage VC3, relevant to the type of voltage) determines the previous control unit in real time according to the operating unit, and calculates the hysteresis arm-leg optimal dead time.

[0047] II类:在超前臂(滞后臂)开关管关断后,在谐振电容C3 (C4)电压% (Fq)第一个 [0047] Class II: (lagging arm) switch turned off in the ultra forearm, the resonant capacitor C3 (C4) Voltage% (Fq) first

极小值点处开通同桥臂另一开关管,即t3时刻开通滞后臂开关管。 At the minimum point with the opening of the other switch bridge arm, i.e. the lag time t3 arm switch opening. 图如,0 < t彡T/2内超前臂:td = At2 = t「t。;图4c,Τ/2 < t < T 内滞后臂:td = At2 = t3-t2 ; FIG As, 0 <t T the San / 2-leg: td = At2 = t 't .; FIG. 4c, Τ / 2 <t <T within the hysteresis arm: td = At2 = t3-t2;

[0048] III类:在超前臂(滞后臂)开关管关断后谐振电容C3(C4)电压& )降至 [0048] Class III: ultra forearm (lagging arm) switch turned off resonant capacitor C3 (C4) & voltage) drops

时,开通另一开关管,即t4时刻开通滞后臂开关管。 , The opening of the other switch, i.e. the lag time t4 to open the switch arm. 图如,0<{彡172内超前臂:td= At3 =t3-t0 ;图4c,Τ/2 < t < T 内滞后臂:td' = At3' = t4-t2 ; FIG e.g., 0 <{San the lead arm 172: td = At3 = t3-t0; FIG. 4c, Τ / 2 <t <T within the hysteresis arm: td '= At3' = t4-t2;

[0049] IV类:在谐振电容C3(C4)电压&3 降为零后开通超前臂(滞后臂)开关管。 [0049] IV categories: open lead arm after resonant capacitor C3 (C4) & 3 reduced to zero voltage (lagging arm) switch. 图4b,0 < t彡T/2内超前臂:取~ =^1-¾;图4(d),T/2 < t < T内滞后臂:取 FIG. 4b, 0 <t T the San / 2-leg: take ~ = ^ 1-¾; FIG. 4 (d), T / 2 <t <T lag inner arm: Take

f ' _h+hf Td - ----h。 f '_h + hf Td - ---- h.

[0050] 图4为ii、iii、iv类情况下&3 (¾)和初级电感电流波形。 [0050] FIG. 4 is a ii, iii, iv category where the & 3 (¾) and the primary inductor current waveform. 虚线部分为死区时间足够大时的谐振电容c3(c4)电压fc3 (fc4)波形,实线部分是按计算出最佳死区时间开通超前臂(滞后臂)开关管的&3 [Vc4)波形。 The dotted line is a resonant capacitor C3 (C4) voltage fc3 (fc4) waveform when the dead time is large enough, the solid line is based on the calculated optimum deadtime turn lead arm (lagging arm) & 3 [Vc4) waveform switch tube .

[0051] 按照计算的最佳死区时间,死区信号发声单元直接生成高频宽度为最佳死区时间大小的序列脉冲。 [0051] According to a preferred calculated dead time, dead-sounding signal means generates a high frequency direct sequence pulse width of the dead zone time optimal size.

[0052] 采用协同控制方法,dsp根据负载和输入变化同时产生移相信号,将死区时间序列脉冲注入移相信号脉冲生成死区时间实时调整的移相触发脉冲。 [0052] The cooperative control method, dsp while generating shift signal input and the load changes, the dead time shift signal sequence pulse injection dead time pulse generator trigger pulse is shifted real-time adjustment. [0053] 根据以上实验验证,图5是滞后臂下管固定死区时间的驱动电压Vg和谐振电容电压Vc4波形图,图6是采用本发明后滞后臂下管死区时间实时调节后驱动电压Vg和电压Vc4 波形图,对比图5和图6可知,在相同的运行情况下,本发明的方法降低了开关管开通时的电压,从而大大降低移相全桥变换器的开关损耗。 [0053] According to the above experiments, FIG. 5 is a driving voltage Vg and the resonant capacitor voltage Vc4 waveform diagram tube fixed dead time at the lagging leg, FIG 6 is the use of the tube dead hysteretic arm post according to the present invention, the time adjusted in real time the driving voltage Vg and the voltage Vc4 waveform diagram comparing FIGS. 5 and 6 that, under the same operating conditions, the method of the present invention reduces the voltage when the switch opened, thereby greatly reducing the phase-shift full-bridge converter switching losses.

Claims (10)

  1. 1.降低移相全桥变换器开关损耗的装置,其特征在于包括:顺次连接的谐振电容电压检测单元、判断单元、控制运算单元和信号发生单元,信号发生单元包括移相信号发生单元、死区信号发生单元和移相触发脉冲发生单元;谐振电容电压检测单元检测谐振电容电压信号并转化此信号送至判断单元;判断单元判断谐振电容电压检测单元转换的信号所属类型;控制运算单元根据判断单元判断信号类型计算出最佳死区时间;信号发生单元输出控制运算单元所计算出的移相全桥两桥臂上下管开关的死区时间的移相触发脉冲。 1. The phase shift means reducing the full-bridge converter switching losses, characterized by comprising: a resonant capacitor connected to the voltage detection means sequentially, determination unit, a control arithmetic unit and a signal generating unit, signal generating means comprises a shift signal generation unit, dead-signal generating unit and a phase shift trigger pulse generating means; means for detecting the resonant capacitor voltage detecting the resonant capacitor voltage signal and converts the signal to the determination unit; determining unit determines the type of signal belongs resonant capacitor voltage detection unit conversion; the control arithmetic unit Analyzing the signal type determination unit calculates the optimum dead time; a signal generation control unit outputs the calculated phase arithmetic unit shift dead-time phase shift full bridge two bridge arm switch trigger pulse tube.
  2. 2.如权利要求1所述的降低移相全桥变换器开关损耗的装置,其特征在于所述谐振电容电压检测单元包括与移相全桥两桥臂下管两个谐振电容(C3、C4)并联的第一串联电阻和第二串联电阻,两个电平转换电路和采样存储单元;第一串联电阻包括串联的第一分压电阻(Rdl)和第二分压电阻(Rd2),第二串联电阻包括串联的第三分压电阻(Rd3)和第四分压电阻(Rd4);第一分压电阻(I^dl) —端接地,另一端与第二分压电阻(Rd2) —端连接;所述第三分压电阻(Rd3) —端接地,另一端与第四分压电阻(Rd4) —端连接。 2. The phase-shifted full bridge converter switching losses apparatus as claimed in claim 1 reduction, wherein the resonant capacitor voltage detecting means comprises two tubular resonant capacitor (C3 under the two phase-shifted full bridge arm, C4 ) in parallel with a first resistor and a second series resistor connected in series, two level conversion circuits and the sample storage unit; a first series resistor comprises a first voltage dividing resistor (Rdl) connected in series and a second voltage dividing resistor (Rd2), first two series resistance comprises a series of a third voltage dividing resistor (Rd3) and fourth voltage dividing resistor (Rd4); a first voltage dividing resistor (I ^ dl) - grounded, the other end of the second voltage dividing resistor (Rd2) - end; said third voltage dividing resistor (Rd3) - grounded, the other end of the fourth voltage dividing resistor (Rd4) - terminal.
  3. 3.如权利要求2所述的降低移相全桥变换器开关损耗的装置,其特征在于所述的电平转换电路包括两个级联运放电路:第一级联运放电路和第二级联运放电路;其中第一级联运放电路包括第一运放(A1)、第二运放(A2)、第一运放反相端输入电阻(R1)、第一运放正相端输入电阻(R2)、第一反馈可调电阻(R3)、第一运放反相端落地电阻(R4)、第二运放反相端输入电阻(R5)、第二运放正相端输入电阻(R6)、第二反馈电阻(R7)和第二运放反相端落地电路(R8);所述第二级联运放电路包括第三运放、第四运放、第三运放反相端输入电阻OV )、第三运放正相端输入电阻OV )、第三反馈可调电阻(R/ )、第三运放反相端落地电路OV )、第四运放反相端输入电阻OV )、第四运放正相端输入电阻OV )、第四反馈电阻(R7,)和第四运放反相端接地电阻OV )。 3. The phase-shifted full bridge converter apparatus as claimed in reducing the switching loss of 2, wherein said level shift circuit comprises two stages transport discharge circuit: a first stage amplifier circuit and a second transport transport stage amplifier circuit; wherein the discharge circuit includes a first stage transport the first operational amplifier (A1), a second operational amplifier (A2), a first terminal of the inverting operational amplifier input resistor (R1), a first op-phase end of an input resistor (R2), a first feedback adjustable resistor (R3), the ground terminal of the first operational amplifier inverting resistor (R4), the second operational amplifier inverting input terminal of a resistor (R5), a second operational amplifier inverting terminal input resistor (R6), a second feedback resistor (R7) and a ground terminal of second operational amplifier inverting circuit (R8); a second amplifier circuit comprises a third transport stage operational amplifier, a fourth operational amplifier, a third operational put the negative input resistor OV), a third operational amplifier inverting terminal input resistance OV), an adjustable third feedback resistor (R /), the ground terminal of the third operational amplifier inverting circuit OV), a fourth op amp inverting end of the input resistance OV), the fourth operational amplifier inverting terminal input resistance OV), the fourth feedback resistor (R7,) and a fourth op amp inverting end of the resistor OV).
  4. 4.如权利要求3所述的降低移相全桥变换器开关损耗的装置,其特征在于第一级联运放电路中,第一运放反相端输入电阻(R1) —端、第一分压电阻(Rdl) —端和第二分压电阻(Rd2) —端连接,第一运放反相端输入电阻(R1)另一端、第一反馈可调电阻(R3) —端和第一运放(A1)的反相输入端连接,第一运放正相端输入电阻(R2) —端、第一运放反相端落地电阻(R4) —端和第一运放(A1)的正相输入端连接,第一运放反相端落地电阻(R4)另一端接地,第一运放正相端输入电阻(R2)另一端连接参考电压(VMfl),第二运放反相端输入电阻(R5) —端、第一运放(A1)的输出端与第一反馈可调电阻(R3)另一端连接,第二运放反相端输入电阻(R5)另一端、第二反馈电阻(R7) —端和第二运放(A2)的反相输入端连接,第二运放正相端输入电阻(R6) —端、第二运放反相端落地电路 4. The phase-shifted full bridge converter switching losses apparatus as claimed in claim 3 reduced, characterized in that the first transport stage amplifier circuit, the first terminal of the inverting operational amplifier input resistor (R1) - ends, a first voltage dividing resistors (Rdl) - end and a second voltage dividing resistor (Rd2) - terminal is connected, a first operational amplifier inverting input terminal of the other end of the resistor (Rl), a first feedback adjustable resistor (R3) - a first end and a operational amplifier (A1) is connected to an inverting input terminal, a first terminal of the op amp with an input resistor (R2) - end, a first landing operational amplifier inverting terminal resistor (R4) - end and a first operational amplifier (A1), positive-phase input terminal connected to the ground terminal of the first operational amplifier inverting resistor (R4) to the other end, a first positive input of op-resistor (R2) and the other end connected to the reference voltage (VMfl), a second operational amplifier inverting terminal an input resistor (R5) - end, a first operational amplifier (A1) is adjustable output terminal of the first feedback resistor (R3) connected to the other end of the second operational amplifier inverting input terminal of the other end of the resistor (R5), a second feedback a resistor (R7) - and an inverting input terminal of a second operational amplifier (A2) connected with the second terminal of the op amp input resistor (R6) - terminal, a second terminal of the inverting operational amplifier circuit ground R8) —端和第一运放(A1)的正相输入端连接,第二运放反相端落地电路(R8)另一端接地,第二运放正相端输入电阻(R6)另一端连接另一参考电压(Vref2),所述第二级联运放电路中,第三运放反相端输入电阻(R/ ) 一端、第三分压电阻(Rd3) —端和第四分压电阻(Rd4) —端连接,第三运放反相端输入电阻(R/ )另一端、第三反馈可调电阻(R3' ) 一端和第三运放(A3)的反相输入端连接,第三运放正相端输入电阻OV ) 一端、第三运放反相端落地电路OV ) 一端和第三运放(A3)的正相输入端连接,第三运放反相端落地电路0V)另一端接地,第一运放正相端输入电阻(R2) 另一端连接参考电压(υ),第四运放反相端输入电阻αν) —端、第一运放(A1)的输出端与第三反馈可调电阻αν)另一端连接,第四运放反相端输入电阻αν)另一端、第四反馈电阻(R/ ) 一端和第二运放(A2) R8) - end and a first operational amplifier (A1) is connected to the positive input terminal, a second terminal of the inverting operational amplifier circuit ground (R8) other end, the second operational amplifier inverting terminal input resistor (R6) connected to the other end a further reference voltage (Vref2), the second transport stage amplifier circuit, the third terminal of the inverting operational amplifier input resistor (R /) at one end, a third voltage dividing resistor (Rd3) - end and a fourth voltage dividing resistors (Rd4) - terminal is connected, a third operational amplifier inverting input terminal of the other end of the resistor (R /), an adjustable third feedback resistor (R3 ') and the end of the third operational amplifier (A3) connected to the inverting input terminal, a first three-phase terminal of the op amp input resistor OV) at one end, a third ground terminal of the inverting operational amplifier circuit OV) and the end of the third operational amplifier (A3) connected to the positive input, a third inverting operational amplifier circuit ground terminal 0V) other end, with the first operational amplifier positive input terminal of a resistor (R2) and the other end connected to the reference voltage ([upsilon]), a fourth terminal of the inverting operational amplifier input resistance αν) - end, a first operational amplifier (A1) and the output terminal third feedback variable resistor αν) and the other end connected to the inverting terminal of the fourth operational amplifier input resistor αν) the other end, the fourth feedback resistor (R /) and one end of a second operational amplifier (A2) 反相输入端连接,第四运放正相端输入电阻OV )另一端连接参考电压(VMf2'),第二反馈电阻(R7)另一端与第二运放的输出端连接,第四反馈电阻(R/)另一端与第四运放的输出端连接;采用存储单元的一个接收端(人)与第二运放(A2)的输出端连接,另一个接收端(/2)与第四运放的输出端连接。 Inverting input terminal connected to a fourth operational amplifier inverting terminal input resistance OV) and the other end connected to the reference voltage (VMf2 '), the other end of the second feedback resistor (R7) and a second operational amplifier connected to the output, the fourth feedback resistor the other end (R & lt /) of the fourth operational amplifier is connected to an output terminal; a memory cell using a receiving terminal (al) and the second operational amplifier (A2) connected to the output, another receiving terminal (/ 2) and the fourth the operational amplifier output is connected.
  5. 5.利用权利要求1所述装置降低移相全桥变换器开关损耗的方法,其特征在于包括如下步骤:(1)谐振电容电压检测单元检测转换谐振电容电压信号后送至判断单元;(2)利用判断单元判断由检测单元检测出来的移相全桥变换器中两桥臂下管谐振电容电压信号的类型;(3)控制运算单元根据判断单元判断的类型分别实时计算两桥臂中同一桥臂上下两开关管的最佳死区时间;所述死区时间包括移相全桥的同一桥臂中超前臂和滞后臂上下两个开关管间的死区时间,两个桥臂的最佳死区时间独立产生;(4)经信号发生单元产生的死区时间为最佳死区时间的移相触发脉冲使开关管开通时承受电压最小,从而降低开关管的开关损耗。 5. The apparatus of claim 1 using the method of reducing the full-bridge converter switching losses shift, characterized by comprising the steps of: (a) detecting means for detecting the resonant capacitor voltage converted signal to the resonant capacitor voltage determining means; (2 phase full-bridge converter type tube resonant capacitor voltage signal in the two arm shift) using the determination unit determines detected by the detection unit; (3) respectively, the control arithmetic unit calculates the real-time two bridge arm of the same type determining unit determines the the optimum dead time includes phase-shifting the same bridge arm and forearm Super hysteresis lower arm dead time between the two switches of the full bridge, the two bridge arms; optimal dead time of the bridge arm of the two switch dead time generated independently; (4) the dead time generated by the signal generating unit to phase shift the optimum dead time so that the withstand voltage of the trigger pulse when the minimum opening switch, thereby reducing switching loss of the switch.
  6. 6.根据权利要求5所述的方法,其特征在于步骤O)中判断单元判断两桥臂下管谐振电容电压的大小,然后进行分类;步骤(3)中控制运算单元根据判断单元对两桥臂下管谐振电容电压大小的分类,实时计算出两桥臂中同一桥臂上下两开关管的最佳死区时间。 6. The method according to claim 5, characterized in that the size of the tube voltage of the resonant capacitor unit determines that the two-arm Step O) is determined, and then classified; Step (3) The arithmetic unit determines the control unit of the two bridges lower arm pipe classified resonant capacitor voltage magnitude, calculated in real time the optimal dead time in the same two-arm bridge arm of the two-switch.
  7. 7.根据权利要求5所述的方法,其特征在于步骤中死区信号发生单元产生的死区信号是一系列死区时间为最佳死区时间的脉冲,通过将该系列脉冲注入到所述移相脉冲发生单元中,产生实时可调且死区时间最佳的移相脉冲信号。 7. The method according to claim 5, characterized in that the dead dead step signal generating unit generates a dead time signal is a series of pulse optimal dead time, the series of pulses is injected through the phase shift pulse generating unit, generates a pulse signal phase shift is adjustable in real time and the dead time best.
  8. 8.根据权利要求5所述的方法,其特征在于步骤(4)移相脉冲发生单元通过协同控制, 控制最佳死区时间可调和控制触发脉冲移相。 8. The method according to claim 5, wherein the step (4) the phase shift pulse generating means controlled by the cooperative control optimal dead time adjustable trigger pulse and phase shift control.
  9. 9.根据权利要求5所述的方法,其特征在于步骤(1)采样存储规律是,单周期内正常工作状态下,当超前臂开关管关断后,开始采样,并计时,直到同桥臂另一个开关管都开通, 时长△ t,采样点数50 ;开关单周期采样持续1/6个工频周期,即一个工频周期内共6次采样;一个工频周期存储数据全部更新一次。 9. The method according to claim 5, wherein the step (1) sample storage rule is, under normal operating conditions in a single cycle, when the ultra forearm switch turns off, start sampling, and time, with the arm until the the other switches are opened, the duration △ t, 50 sampling points; single switching cycle of the sampling frequency cycle duration 1/6, i.e., a cycle frequency of 6 samples; the entire period of a frequency storing updated data.
  10. 10.根据权利要求5所述的方法,其特征在于死区信号发生单元,采用TI公司的TMS320F2812DSP,死区信号发生单元根据谐振电容电压信号分类计算出大小为最佳死区时间、频率为开关频率的一系列脉冲。 10. The method according to claim 5, characterized in that the dead-signal generating unit, using TI's TMS320F2812DSP, dead signal generating unit calculates the resonant capacitor voltage signal is classified according to the size of the optimum dead time, the switching frequency a series of pulse frequencies.
CN 201110078847 2011-03-30 2011-03-30 Method and device for reducing switching loss of phase-shifting full-bridge converter CN102111074B (en)

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CN102629831A (en) * 2012-04-01 2012-08-08 华为技术有限公司 Method, circuit and device for soft switch detection
CN104135159A (en) * 2014-07-21 2014-11-05 中国东方电气集团有限公司 Regulation control method for variable dead zone of phase-shifted full-bridge converter
CN104578777A (en) * 2015-01-30 2015-04-29 西安电子科技大学 Dead time control circuit applied to buck-type DC (direct-current)-DC converter
CN105656301A (en) * 2016-03-25 2016-06-08 明纬(广州)电子有限公司 Resonance control device

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CN201352763Y (en) * 2009-01-05 2009-11-25 西安理工大学 Phase-shifted full bridge zero-current and zero-voltage PWM converter
CN101847936A (en) * 2010-05-28 2010-09-29 南京航空航天大学 Soft switching full-bridge direct-current converter with lag leg connected with auxiliary network in parallel

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WO2005015717A2 (en) * 2003-08-09 2005-02-17 Astec International Limited A circuit for reducing losses at light load in a soft switching full bridge converter
CN201352763Y (en) * 2009-01-05 2009-11-25 西安理工大学 Phase-shifted full bridge zero-current and zero-voltage PWM converter
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CN102629831A (en) * 2012-04-01 2012-08-08 华为技术有限公司 Method, circuit and device for soft switch detection
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CN104135159A (en) * 2014-07-21 2014-11-05 中国东方电气集团有限公司 Regulation control method for variable dead zone of phase-shifted full-bridge converter
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CN104578777A (en) * 2015-01-30 2015-04-29 西安电子科技大学 Dead time control circuit applied to buck-type DC (direct-current)-DC converter
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CN105656301A (en) * 2016-03-25 2016-06-08 明纬(广州)电子有限公司 Resonance control device

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