CN102110683A - High-voltage vertical structure semiconductor light emitting diode - Google Patents

Abstract

The invention relates to a high voltage vertical structure semiconductor light emitting diode. A high-voltage vertical structure LED chip includes a support substrate and several vertical structure LED units. The vertical structure LED units are arranged on the insulating support substrate with through holes, and the vertical structure LED units are electrically connected in series. The vertical structure LED unit includes: (A) semiconductor epitaxial thin film; the semiconductor epitaxial thin film is arranged on the metal film of the insulating support substrate with through holes. (B) Passivation layer; The passivation layer covers the insulating support substrate, metal film and semiconductor epitaxial film with through holes; Forms a window at a predetermined position on the passivation layer above the semiconductor epitaxial film; On the metal film Form a window at a predetermined position on the passivation layer above; (C) metal electrode; the metal electrode is stacked on the semiconductor epitaxial film through the window and extends to the metal film of the predetermined adjacent vertical structure LED unit and passes through the The window on the metal film of the adjacent vertical structure LED units is electrically connected to the metal film, so that two adjacent vertical structure LED units are electrically connected in series.

Description

High Voltage Vertical Structure Semiconductor Light Emitting Diodes

technical field

The invention discloses a high-voltage vertical structure semiconductor light-emitting diode (HV Vertical LED), which belongs to the field of optoelectronic technology.

Background technique

Semiconductor light-emitting diodes (LEDs) are entering the field of general lighting, and high-voltage-driven LED chips have been introduced to the market. However, each LED unit in existing high-voltage semiconductor light emitting diodes has a lateral structure. The disadvantage of the lateral structure LED unit is that it cannot be driven by a large current, low luminous efficiency, current crowding, large thermal resistance, etc. Therefore, a high-voltage semiconductor light-emitting diode is required, which can be driven by a large current and further improve the luminous intensity. efficiency and improved thermal dissipation.

The present invention discloses a high-voltage vertical structure LED chip to overcome the above disadvantages.

Contents of the invention

The structure of an embodiment of the high-voltage vertical structure LED chip of the present invention is as follows: a high-voltage vertical structure LED chip includes a support substrate and at least two vertical structure LED units, and at least two vertical structure LED units are formed on at least one main surface of the support substrate. A sheet of metal film; the vertical structure LED units are formed on the metal film respectively; the vertical structure LED units are electrically connected in series, so that the vertical structure LED chips can withstand high voltage

The structure of one embodiment of a high voltage vertical structure LED chip includes:

(1) Support substrate. The support substrate includes: (A) an insulating support substrate, or (B) an insulating support substrate with vias. An insulating support substrate includes an insulating substrate and a plurality of mutually electrically insulating metal films formed on one main surface thereof. The insulating substrate includes a silicon insulating substrate, or a ceramic insulating substrate, or a graphite foam (Graphite foam) insulating substrate, or a metal substrate having an insulating layer on one main surface. A metal substrate with an insulating layer on its main surface is defined as a type of insulating substrate, which has the advantage of excellent thermal conductivity. Ceramic insulating substrates include aluminum nitride substrates and aluminum oxide substrates. An insulating support substrate with through holes includes an insulating substrate and a plurality of through holes formed therein in which metal plugs are filled; each of the two main surfaces of the insulating substrate with through holes At least two metal films are respectively formed on the surface, and the two metal films formed on one main surface are electrically connected to the corresponding two metal films formed on the other main surface through metal plugs in the through holes. On the first main surface, at least two metal films are formed; on the second main surface, only two metal films are formed, and these two metal films will be connected with the positive and negative electrodes of the external power supply.

(2) At least two vertical structure LED units connected in series. The vertical structure LED unit includes, (A) a semiconductor epitaxial film; the structure of the semiconductor epitaxial film includes, but not limited to, a first type confinement layer, an active layer, and a second type confinement layer. The activation layer is formed between the first type confinement layer and the second type confinement layer. The semiconductor epitaxial thin film is provided on the metal film of the supporting substrate. (B) a passivation layer; the passivation layer covers the support substrate, the metal film and the semiconductor epitaxial film; a window is formed at a predetermined position on the passivation layer above the semiconductor epitaxial film, so that the semiconductor epitaxial film is exposed in the window; Form a window at a predetermined position on the passivation layer above the metal film, so that the metal film is exposed in the window; (C) metal electrode; the metal electrode is laminated on the semiconductor epitaxial film through the window and extends to the predetermined adjacent vertical The metal film of the structure LED unit extends and forms an electrical connection with the metal film of the adjacent vertical structure LED unit through the window on the metal film, so that two adjacent vertical structure LED units form an electrical connection in series. Each semiconductor epitaxial film, corresponding passivation layer and metal electrode constitute a vertical structure LED unit.

The second-type confinement layer of the semiconductor epitaxial film is arranged on the metal film of the supporting substrate, and the method of setting includes bonding and bonding. Wherein, the setting may be a setting at a wafer level (wafer level bonding), or a setting at a chip (chip level flip chip bonding) level. The bonding medium includes gold tin, silver tin, gold indium, gold, etc. The bonding medium includes conductive glue and solder paste.

One embodiment (FIG. 2a): For the insulating support substrate, except for the metal film used as the bonding pad connected to the external power supply, there are semiconductor epitaxial thin films on the other metal films. The number of metal films is greater than that of semiconductor epitaxial films.

An embodiment (Fig. 3b): three metal films are formed on the first main surface of the insulating support substrate with through holes; two metal films are formed on the second main surface, and these two metal films are formed on the The corresponding two metal films on the first main surface are electrically connected with the metal plugs therein through through holes; at least two semiconductor epitaxial thin films are respectively formed on different metal films on the first main surface. The number of metal films ≥ the number of semiconductor epitaxial thin films+1.

metal electrodes. Through the window of the passivation layer on the first-type confinement layer of the semiconductor epitaxial film, the metal electrode is stacked on the first-type confinement layer of the semiconductor epitaxial film, and extends to another adjacent metal film and passes through another metal film The upper window forms an electrical connection with the metal film. Since the second-type confinement layer of another semiconductor epitaxial film is disposed on the metal film, the first-type confinement layer of one semiconductor epitaxial film forms a serial electrical connection with the second-type confinement layer of another semiconductor epitaxial film, Thus, two vertical structure LED units form a series connection. In the same way, a predetermined number of vertical structure LED units are connected in series, so that higher voltage can be tolerated.

An embodiment of the arrangement of the vertical structure LED units on the support substrate: several vertical structure LED units are arranged in a matrix with N rows and M columns, where N≥1 and M≥2. When N=1, M≥2, several vertical structure LED units are arranged in a straight line. When N>1, and N≠M, several vertical structure LED units are arranged in a rectangular matrix. When N>1, and N=M, several vertical structure LED units are arranged in a square matrix.

There are two types of metal electrodes, one is to connect adjacent semiconductor epitaxial films in series according to a predetermined method, and the other is to electrically connect the semiconductor epitaxial films to an external power source.

transparent electrodes. Between the metal electrode and the first type confinement layer of the semiconductor epitaxial thin film, a transparent electrode of a predetermined shape is formed. The transparent electrode has a single-layer or multi-layer structure. The material of each layer of the transparent electrode is selected from a group of conductive transparent oxide materials or a group of transparent metal materials. The conductive transparent oxide materials include: ITO, ZnO: Al, ZnGa2O4, SnO2:Sb, Ga2O3:Sn, In2O3:Zn, NiO, MnO, CuO, SnO, GaO; transparent metal materials include: Ni/Au, Ni/Pt, Ni/Pd, Ni/Co, Pd/Au , Pt/Au, Ti/Au, Cr/Au, Sn/Au.

Another embodiment: the surface of the transparent electrode has a roughened structure.

The purpose of the present invention and the various effects that can be achieved are as follows:

(1) The present invention provides high-voltage vertical structure LED chips (including gallium nitride-based, gallium phosphide-based, gallium nitrogen phosphorus-based, and zinc oxide-based LED chips), and a single vertical structure LED unit is still a vertical structure driven by a low voltage. Structured LED; high voltage vertical structure LED chips have all the advantages of vertical structure LED chips, further improve luminous efficiency and heat dissipation, so that high voltage vertical structure LED chips can quickly enter general lighting.

(2) The high-voltage vertical structure LED chip provided by the present invention can be directly driven by a higher voltage. Therefore, in the control circuit of the lamp, the transformer is saved and the cost is reduced.

(3) The high-voltage vertical structure LED chip provided by the present invention has no current crowding, can pass a large current, and has excellent heat dissipation.

(4) For the high-voltage vertical structure LED chip of the present invention using an insulating support substrate with through holes, the chip manufacturing process and packaging process are combined to simplify the manufacturing process.

(5) The high-voltage vertical structure LED chip provided by the present invention, for the semiconductor epitaxial film that adopts chip horizontal bonding, does not need to etch any light-emitting layer material, so 100% utilizes the light-emitting layer material.

(6) The high-voltage vertical structure LED chip provided by the present invention has higher light extraction efficiency because the surface of the transparent electrode is roughened.

The present invention and its features and benefits will be better demonstrated in the following detailed description.

Description of drawings

Figures 1a-1c show three embodiments of support substrates.

Figure 2a shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 2b shows a cross-sectional view of one embodiment of the high voltage vertical structure LED chip shown in Figure 2a.

Fig. 2c shows a cross-sectional view of another embodiment of the high voltage vertical structure LED chip shown in Fig. 2a.

Figure 2d shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 3a shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 3b shows a cross-sectional view of one embodiment of the high voltage vertical structure LED chip shown in Figure 3a.

Figure 3c shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 4a shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 4b shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 5a shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 5b shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 6a shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 6b shows a top view of one embodiment of a high voltage vertical structure LED chip.

Figure 7 shows a top view of one embodiment of a high voltage vertical structure LED chip.

specific embodiment

Although specific embodiments of the present invention will be described below, the following descriptions only illustrate the principle of the present invention, rather than limit the present invention to the descriptions of the following specific implementation examples.

Note: the following items are applicable to all specific embodiments of the high-voltage vertical structure LED chip of the present invention:

(1) The ratio of each part in the figure does not represent the ratio of the real product.

(2) The last process step of the production process for manufacturing the high voltage vertical structure LED chips of the present invention is to divide the array with high voltage vertical structure LED chips into individual high voltage vertical structure LED chips. Therefore, in order to simplify the drawing, in the embodiment shown in the figure, only several vertical structure LED units of a high voltage vertical structure LED chip are shown.

(3) A high-voltage vertical-structure LED chip includes a support substrate and multiple low-voltage vertical-structure LED units. Support substrate. The support substrate includes: (A) an insulating support substrate, or (B) an insulating support substrate with vias.

(4) The arrangement of the vertical structure LED units on the support substrate includes: several vertical structure LED units are arranged in a matrix with N rows and M columns, wherein N≥1 and M≥2. When N=1, M≥2, several vertical structure LED units are arranged in a straight line. When N>1, and N≠M, several vertical structure LED units are arranged in a rectangular matrix. When N>1, and N=M, several vertical structure LED units are arranged in a square matrix.

(5) An insulating support substrate includes an insulating substrate and a plurality of metal films formed on one main surface thereof to be electrically insulated from each other. The insulating substrate includes a silicon insulating substrate, or a ceramic insulating substrate, or a graphite foam insulating substrate, or a metal substrate having an insulating layer on one main surface. A metal substrate with an insulating layer on its main surface is defined as a type of insulating substrate, which has the advantage of excellent thermal conductivity. For a metal substrate with an insulating layer, the metal film is formed on the insulating layer. Therefore, The metal films are electrically insulated from each other. Ceramic insulating substrates include aluminum nitride insulating substrates and aluminum oxide insulating substrates. The number of metal films ≥ the number of semiconductor epitaxial films.

(6) An insulating support substrate with through holes, including an insulating substrate with through holes, a plurality of through holes formed therein, metal plugs filled in the through holes, and a plurality of through holes formed on both main surfaces. two metal films electrically insulated from each other; at least three metal films are respectively formed on the first main surface of the insulating support substrate with through holes, and two metal films are formed on the other main surface and are formed on the first main surface. Corresponding metal films on the major surfaces are electrically connected by metal plugs in the vias. The number of metal films ≥ the number of semiconductor epitaxial thin films+1.

(7) The vertical structure LED unit includes a semiconductor epitaxial film, a passivation layer and a metal electrode.

(8) The semiconductor epitaxial film includes a first type confinement layer, an active layer, and a second type confinement layer. The activation layer is formed between the first type confinement layer and the second type confinement layer.

(9) The second type confinement layer of the semiconductor epitaxial thin film is provided on the metal film on one main surface of the support substrate. Methods of setup include metal bonding and bonding. Settings can be at the wafer level (wafer level bonding), or at the chip (chip level flip chip bonding) level.

Metal bonding media include gold tin, silver tin, gold indium, gold, etc. The bonding medium includes conductive glue and solder paste.

(10) For the use of metal bonding, it is necessary to pre-laminate a conductive reflective/ohmic/bonding layer (not shown in the figure) on the semiconductor epitaxial film. The conductive reflective/ohmic/bonding layer has a multi-layer structure and its function is to reflect light , maintain ohmic contact, and bond with other metal layers. Metal bonding media include gold tin, gold indium, silver tin, gold, and the like. For an arrangement using bonding, it is only necessary to pre-laminate a conductive reflective/ohmic layer (not shown) on the semiconductor epitaxial film.

(11) The material of the semiconductor epitaxial thin film is selected from a group of materials including gallium nitride-based, gallium phosphide-based, gallium nitrogen phosphorus-based, and zinc oxide-based materials. Among them, gallium nitride-based materials include: binary system, ternary system, and quaternary system materials of gallium, aluminum, indium, and nitrogen. Binary, ternary, and quaternary materials of gallium, aluminum, indium, and nitrogen include GaN, GaInN, AlGaInN, AlGaInN, and the like. Gallium phosphide-based materials include: binary system, ternary system, and quaternary system materials of gallium, aluminum, indium, and phosphorus. Binary, ternary, and quaternary materials of gallium, aluminum, indium, and phosphorus include GaP, GaInP, AlGaInP, and InP, etc. Gallium nitrogen phosphorus-based materials include: gallium, aluminum, indium, nitrogen, phosphorus binary system, ternary system, quaternary system and quinary system materials. Binary, ternary, quaternary, and quinary materials of gallium, aluminum, indium, nitrogen, and phosphorus include GaNP, AlGaNP, GaInNP, and AlGaInNP, etc. Zinc oxide-based materials include, ZnO, and the like. Gallium nitride-based, gallium phosphide-based, gallium nitrogen-phosphorus-based, and zinc oxide-based epitaxial films include: gallium nitride-based, gallium phosphide-based, gallium nitrogen-phosphorus-based, and zinc oxide-based LED epitaxial films. The crystal plane of the gallium nitride-based epitaxial layer is selected from a group of crystal planes, and the group of crystal planes includes: c-plane, a-plane and m-plane.

(12) A passivation layer covers the top of the support substrate and the semiconductor epitaxial film. An opening is formed at a predetermined position above the first type confinement layer of the semiconductor epitaxial thin film and above the metal film, so that the semiconductor epitaxial thin film and the metal film are respectively exposed in the opening.

(13) The material of the passivation layer is selected from a group of materials including silicon oxide (SiO2), silicon nitride (SiN), silicon on glass (SOG), and the like.

(14) The metal electrode is stacked on the first-type confinement layer of a semiconductor epitaxial film through the window and extends to the predetermined adjacent metal film of another vertical structure LED unit, and forms an electrical connection with the metal film through the window. Since the second-type confinement layer of another adjacent semiconductor epitaxial film is arranged on the metal film, the first-type confinement layer of one semiconductor epitaxial film is electrically connected to the second-type confinement layer of another adjacent semiconductor epitaxial film. connected, and thus, the two semiconductor epitaxial films form a series connection. In the same manner, a predetermined number of semiconductor epitaxial thin films are connected in series. There are two types of metal electrodes, one is to connect two semiconductor epitaxial films in series, and the other is to electrically connect the semiconductor epitaxial films to an external power source. The metal electrode forms an electrical connection between the semiconductor epitaxial film and the metal film in a predetermined manner through the window.

(15) Between the metal electrode and the first type confinement layer of the semiconductor epitaxial thin film, a transparent electrode of a predetermined shape is formed. The transparent electrode has a single-layer or multi-layer structure. The material of each layer of the transparent electrode is selected from a group of conductive transparent oxide materials and a group of transparent metal materials. The conductive transparent oxide materials include: ITO, ZnO: Al, ZnGa2O4, SnO2:Sb, Ga2O3:Sn, In2O3:Zn, NiO, MnO, CuO, SnO, GaO; transparent metal materials include: Ni/Au, Ni/Pt, Ni/Pd, Ni/Co, Pd/Au , Pt/Au, Ti/Au, Cr/Au, Sn/Au.

(16) On the surface of the high-voltage vertical structure LED chip, a roughened structure or a photonic crystal structure (not shown in the figure) is formed.

(17) On the surface of the transparent electrode of the high-voltage vertical structure LED chip, a roughened structure is formed.

Figures 1a-1c show three embodiments of support substrates.

Figure Ia shows one embodiment of an insulating support substrate 100a. The insulating support substrate 100a includes an insulating substrate 101a and a plurality of metal films 102a, 102b, 102c and 102d electrically insulated from each other. Among them, the metal film 102a, the metal film 102b, the metal film 102c, and the metal film 102d are formed on the insulating substrate 101a.

A dotted line between the metal film 102b and the metal film 102c indicates that a plurality of metal films may be formed between the metal film 102b and the metal film 102c on the insulating substrate 101a.

Figure Ib shows one embodiment of an insulating support substrate 100b. The insulating support substrate 100b includes a metal substrate 101b, an insulating layer 103, and a plurality of metal films 102a, 102b, 102c, and 102d. The insulating layer 103 is formed on one main surface of the metal substrate 101b; the metal film 102a, the metal film 102b, the metal film 102c, and the metal film 102d are formed on the insulating layer 103, and therefore, the metal film 102a, the metal film 102b, the metal film 102c and the metal film 102d are electrically insulated from each other.

A dotted line between the metal film 102b and the metal film 102c indicates that a plurality of metal films may be formed between the metal film 102b and the metal film 102c on the insulating layer 103 .

Figure 1c shows one embodiment of an insulating support substrate 100c with vias. The support substrate 100c includes an insulating substrate 101a with a through hole, the through hole and metal plugs, and metal films respectively formed on both main surfaces of the insulating substrate 101a. Metal plugs 104a and metal plugs 104b are respectively filled in the through holes of the insulating substrate 101a. Three metal films 102a, a metal film 102b, and a metal film 102c are formed on a first main surface of an insulating substrate 101a, and two metal films 105a and a metal film 105b are formed on a second main surface, so that the metal film 102a and the metal film 102c is electrically connected to the metal film 105a and the metal film 105b respectively by filling the metal plug 104a and the metal plug 104b in the through hole. The metal film 105a and the metal film 105b will be electrically connected to an external power source. At least two semiconductor epitaxial thin films are respectively formed on different metal films on the first main surface. A dotted line between the metal film 102b and the metal film 102c indicates that a plurality of metal films may be formed between the metal film 102b and the metal film 102c on the insulating substrate 101a with via holes.

Note that the metal film 102a and the metal film 102c are electrically connected to the corresponding metal film 105a and the metal film 105b formed on the second main surface respectively by filling the metal plug 104a and the metal plug 104b in the through hole, and the other metal The film 102b, etc., has no corresponding metal film formed on the second main surface. The number of metal films on the first main surface ≥ the number of semiconductor epitaxial films+1.

2a to 2c show two embodiments of the high voltage vertical structure LED chip 200 of the present invention, these two embodiments have the same top view (Fig. 2a), but the supporting substrate is different, the supporting substrate of one embodiment Having an insulating substrate 101a (FIG. 2b), another embodiment of a support substrate has a metal substrate 101b with an insulating layer 103 on one main surface (FIG. 2c).

The high-voltage vertical structure LED chip 200 includes, (1) an insulating substrate 101a, (2) a metal film 102a, a metal film 102b, a metal film 102c, and a metal film 102d formed on the insulating substrate 101a, (3) respectively Semiconductor epitaxial thin film 110a and semiconductor epitaxial thin film 110b on metal film 102b and metal film 102c, (4) form on insulating substrate 101a, metal film 102a, metal film 102b, metal film 102c, metal film 102d, semiconductor epitaxial thin film 110a and the passivation layer 111 on the semiconductor epitaxial film 110b (the passivation layer 111 is only shown in Fig. 2b, 2c), (5) metal electrode 107a, metal electrode 107b and metal electrode 107c.

Window 106a and window 106g, window 106b, window 106d, window 106f and window 106h are respectively formed at predetermined positions of passivation layer 111 above metal film 102a, metal film 102b, metal film 102c and metal film 102d, so that metal film 102a , metal film 102b, metal film 102c and metal film 102d are respectively exposed in window 106a and window 106g, window 106b, window 106d and window 106f and window 106h; Passivation layer 111 on semiconductor epitaxial film 110a and semiconductor epitaxial film 110b A window 106c and a window 106e are respectively formed at predetermined positions, so that the semiconductor epitaxial film 110a and the semiconductor epitaxial film 110b are respectively exposed in the window 106c and the window 106e.

Both ends of the metal electrode 107a are respectively formed on the metal film 102a and the metal film 102b through the window 106a and the window 106b, so that the metal film 102a and the metal film 102b are electrically connected.

The parts of the metal film 102a and the metal film 102d exposed in the window 106g and the window 106h become the bonding pad 108a and the bonding pad 108b. The wire bonding pad 108a and the wire bonding pad 108b are electrically connected to an external power source through gold wires 109a and 109b respectively.

The semiconductor epitaxial thin film 110a disposed on the metal film 102b is electrically connected to the bonding pad 108a through the metal film 102b, the metal electrode 107a, and the metal film 102a.

The two ends of the metal electrode 107b are respectively formed on the semiconductor epitaxial film 110a and the metal film 102c through the window 106c and the window 106d, so that the semiconductor epitaxial film 110a and the metal film 102c are electrically connected. The semiconductor epitaxial film 110b is disposed on the metal film 102c, therefore, the semiconductor epitaxial film 110a and the semiconductor epitaxial film 110b are electrically connected in series.

Both ends of the metal electrode 107c pass through the window 106e and the window 106f, and are respectively formed on the semiconductor epitaxial film 110b and the metal film 102d, so that the semiconductor epitaxial film 110b is electrically connected to the bonding pad 108b through the metal electrode 107c and the metal film 102d.

Note that the metal electrode 107b is formed on the semiconductor epitaxial film 110a through the window 106c, extends to the adjacent metal film 102c, and is electrically connected to the metal film 102c through the window 106d on the metal film 102c. Since the second-type confinement layer of the semiconductor epitaxial film 110b is disposed on the metal film 102c, the first-type confinement layer of the semiconductor epitaxial film 110a is electrically connected to the second-type confinement layer of the semiconductor epitaxial film 110b, thus, the two semiconductor epitaxial films Thin films 110a and 110b form a series connection.

In the same way, a predetermined number of semiconductor epitaxial thin films can be connected in series.

Figure 2b shows an A-A cross-sectional view of one embodiment of the high voltage vertical structure LED chip shown in Figure 2a. A metal film 102a, a metal film 102b, a metal film 102c, and a metal film 102d are formed on an insulating substrate 101a.

Fig. 2c shows an A-A cross-sectional view of another embodiment of the high voltage vertical structure LED chip shown in Fig. 2a. The insulating layer 103 is formed on one main surface of the metal substrate 101b, and the metal film 102a, the metal film 102b, the metal film 102c, and the metal film 102d are formed on the insulating layer 103, and therefore, the metal film 102a, the metal film 102b, the metal film 102c and the metal film 102d are electrically insulated from each other. An advantage of a supporting substrate having a metal substrate 101b with an insulating layer 103 on its main surface is that it has excellent heat dissipation performance.

Figure 2d shows a top view of another embodiment of a high voltage vertical structure LED chip. The difference between the high-voltage vertical structure LED chip shown in FIG. 2d and the high-voltage vertical structure LED chip shown in FIG. 2a is that: in FIG. Several semiconductor epitaxial films enable the high-voltage vertical structure LED chip shown in FIG. 2d to withstand higher voltages. In FIG. 2a, only two semiconductor epitaxial films 110a and semiconductor epitaxial films 110b are connected in series. Figure 2d shows the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED chip (and thus, the high-voltage vertical structure LED unit) and the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED unit shown in Figure 2a the same way.

Fig. 2d only shows a top view of a high-voltage vertical structure LED chip, and its supporting substrate can have at least two types as shown in Fig. 1a and Fig. 1b.

Figures 3a and 3b respectively show a top view and an A-A cross-sectional view of one embodiment of a high voltage vertical structure LED chip. The high-voltage vertical structure LED chip 300 includes, (1) an insulating support substrate with through holes, including an insulating substrate 101b and a plurality of through holes formed therein, and metal plugs 104a and metal plugs 104b are filled in the through holes (2) metal film 102b, metal film 102c and metal film 102d formed on the first main surface of insulating substrate 101b, two metal films 105a and metal film are formed on the second main surface of insulating substrate 101b 105b, the metal film 102b and metal film 102d formed on the first main surface and the corresponding metal film 105a and metal film 105b formed on the second main surface respectively pass through the metal plug 104a and the metal plug in the through hole 104b to form an electrical connection; (3) the semiconductor epitaxial film 110a and the semiconductor epitaxial film 110b respectively arranged on the metal film 102b and the metal film 102c, (4) formed on the insulating substrate 101b, the metal film 102b, the metal film 102c, the metal film 102d and the semiconductor epitaxial film 110a and the passivation layer 111 on the semiconductor epitaxial film 110b (the passivation layer 111 is only shown in FIG. 3b ), (5) the metal electrode 107b and the metal electrode 107c.

Window 106d and window 106f are respectively formed on predetermined positions of passivation layer 111 above metal film 102c and metal film 102d, so that metal film 102c and metal film 102d are exposed in window 106d and window 106f respectively; A window 106c and a window 106e are respectively formed at predetermined positions of the passivation layer 111 above the semiconductor epitaxial film 110b, so that the semiconductor epitaxial film 110a and the semiconductor epitaxial film 110b are respectively exposed in the window 106c and the window 106e.

The two ends of the metal electrode 107b are respectively formed on the semiconductor epitaxial film 110a and the metal film 102c through the window 106c and the window 106d, so that the semiconductor epitaxial film 110a and the metal film 102c are electrically connected. The semiconductor epitaxial film 110b is disposed on the metal film 102c, and thus, the semiconductor epitaxial film 110a and the semiconductor epitaxial film 110b are electrically connected in series.

Both ends of the metal electrode 107c are respectively formed on the semiconductor epitaxial film 110b and the metal film 102d through the window 106e and the window 106f, so that the semiconductor epitaxial film 110b is electrically connected to the metal film 102d through the metal electrode 107c.

Note that the metal electrode 107b is formed on the semiconductor epitaxial film 110a through the window 106c, extends to the adjacent metal film 102c, and is electrically connected to the metal film 102c through the window 106d on the metal film 102c. Since the second-type confinement layer of the semiconductor epitaxial film 110b is disposed on the metal film 102c, the first-type confinement layer of the semiconductor epitaxial film 110a is electrically connected to the second-type confinement layer of the semiconductor epitaxial film 110b, thus, the two semiconductor epitaxial films Thin films 110a and 110b form a series connection.

In the same way, a predetermined number of semiconductor epitaxial thin films can be connected in series.

Figure 3c shows a top view of another embodiment of a high voltage vertical structure LED chip. The difference between the high-voltage vertical structure LED chip shown in FIG. 3c and the high-voltage vertical structure LED chip shown in FIG. 3a is that: in FIG. Several semiconductor epitaxial films make the high-voltage vertical structure LED chips shown in Figure 3c able to withstand higher voltages. In FIG. 3a, only two semiconductor epitaxial films 110a and 110b are connected in series. Figure 3c shows the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED chip (hence, the high-voltage vertical structure LED unit) and the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED unit shown in Figure 3a the same way.

Fig. 3c only shows a top view of a high-voltage vertical structure LED chip, and its supporting substrate has at least one kind, as shown in Fig. 1c.

Figure 3a and Figure 3c show that the advantages of high-voltage vertical structure LED chips are: surface-mounted packaging (SMD), no gold wire packaging process is required, and reflow soldering can be directly performed.

Figure 4a shows a top view of one embodiment of a high voltage vertical structure LED chip. The high voltage vertical structure LED chip shown in Fig. 4a is basically the same as the high voltage vertical structure LED chip shown in Fig. 2a, the difference is that the high voltage vertical structure LED chip shown in Fig. The metal film 102b is electrically connected to the wire bonding pad 108a. In contrast to the high-voltage vertical structure LED chip shown in FIG. 4a, the bonding pad 108a is directly formed on the metal film 102b through the window 106g on the passivation layer.

The high-voltage vertical structure LED chip shown in Figure 4b is basically the same as the high-voltage vertical structure LED chip shown in Figure 4a. Several semiconductor epitaxial thin films are connected in series, so that the high-voltage vertical structure LED chip shown in Figure 4b can withstand higher voltage. In FIG. 4a, only two semiconductor epitaxial films 110a and 110b are connected in series. Figure 4b shows the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED chip (hence, the high-voltage vertical structure LED unit) and the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED unit shown in Figure 4a. the same way.

Figure 5a shows a top view of one embodiment of a high voltage vertical structure LED chip. The high-voltage vertical structure LED chip shown in FIG. 5a is basically the same as the high-voltage vertical structure LED chip shown in FIG. 4a. The difference is that the high-voltage vertical structure LED chip shown in FIG. An electrical connection is made to the wire bonding pad 108b. In contrast to the high-voltage vertical structure LED chip shown in FIG. 5a, the bonding pad 108b is directly formed on the semiconductor epitaxial film 110b through the window 106h on the passivation layer.

The high-voltage vertical structure LED chip shown in Figure 5b is basically the same as the high-voltage vertical structure LED chip shown in Figure 5a. Several semiconductor epitaxial thin films are connected in series, so that the high-voltage vertical structure LED chip shown in Figure 5b can withstand higher voltage. However, in FIG. 5a, only two semiconductor epitaxial films 110a and a semiconductor epitaxial film 110b are connected in series. Figure 5b shows the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED chip (hence, the high-voltage vertical structure LED unit) and the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED unit shown in Figure 5a. the same way.

Figure 6a shows a top view of one embodiment of a high voltage vertical structure LED chip. The high-voltage vertical structure LED chip shown in FIG. 6a is basically the same as the high-voltage vertical structure LED chip shown in FIG. 2a. The difference is that the high-voltage vertical structure LED chip shown in FIG. An electrical connection is made to the wire bonding pad 108b. In contrast to the high-voltage vertical structure LED chip shown in FIG. 6a , the bonding pad 108b is directly formed on the semiconductor epitaxial film 110b through the window 106h on the passivation layer.

The high-voltage vertical structure LED chip shown in Figure 6b is basically the same as the high-voltage vertical structure LED chip shown in Figure 6a. Several semiconductor epitaxial thin films are connected in series, so that the high-voltage vertical structure LED chip shown in FIG. 6b can withstand higher voltage. However, in FIG. 6a, only two semiconductor epitaxial films 110a and a semiconductor epitaxial film 110b are connected in series. Figure 6b shows the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED chip (hence, the high-voltage vertical structure LED unit) and the series connection between the semiconductor epitaxial films in the high-voltage vertical structure LED chip shown in Figure 6a. the same way.

Figure 7 shows a top view of one embodiment of a high voltage vertical structure LED chip. The high voltage vertical structure LED chip shown in Figure 7 is basically the same as the high voltage vertical structure LED chip shown in Figure 2d, the difference is that the vertical structure LED units in the high voltage vertical structure LED chip clearly shown in Figure 7 are arranged in Matrix form of N rows and M columns; the vertical structure LED units of the high-voltage vertical structure LED chip shown in Fig. 2d are arranged in a straight line form or a matrix form of N rows and M columns.

The arrangement of the vertical structure LED units on the support substrate includes: several vertical structure LED units 110a, 110b, 110c and 110d are arranged in a matrix with N rows and M columns, where N≥1 and M≥2. When N=1, M≧2, several vertical structure LED units are arranged in a straight line (for example, FIG. 2a, FIG. 3a, FIG. 4a, FIG. 5a, FIG. 6a). When N>1, and N≠M, several vertical structure LED units are arranged in a rectangular matrix. When N>1, and N=M, several vertical structure LED units are arranged in an NxM square matrix. FIG. 7 shows that several vertical structure LED units are arranged in a rectangular matrix or several vertical structure LED units are arranged in a square matrix.

The semiconductor epitaxial film 110a and the semiconductor epitaxial film 110b constitute the first row of vertical structure LED units of the vertical structure LED chip, and the semiconductor epitaxial film 110c and the semiconductor epitaxial film 110d constitute the Nth row of vertical structure LED units of the vertical structure LED chip. The dotted line 120b indicates that there are (N−2) rows of vertical structure LED units between the first row of vertical structure LED units and the Nth row of vertical structure LED units.

The semiconductor epitaxial film 110a and the semiconductor epitaxial film 110d constitute the first vertical structure LED unit of the vertical structure LED chip, and the semiconductor epitaxial film 110b and the semiconductor epitaxial film 110c constitute the vertical structure LED unit of the Mth column of the vertical structure LED chip, as indicated by the dotted line 120a, There are (M−2) columns of vertical structure LED units between the first column of vertical structure LED units and the Mth column of vertical structure LED units.

Note that in order to simplify the drawing, the passivation layer window above the semiconductor epitaxial film and the metal film is not shown in FIG. 7 .

The above specific description does not limit the scope of the present invention, but only provides some specific illustrations of the present invention. Accordingly, the scope of the present invention should be determined by the claims and their legal equivalents, rather than by the above detailed description and implementation examples.

Claims (6)

1. A vertical structure LED chip, characterized in that, said vertical structure LED chip comprises an insulating support substrate with a through hole and at least two vertical structure LED units; wherein said through hole The insulating support substrate includes an insulating substrate, through holes and metal plugs, and a plurality of metal films formed on both main surfaces of the insulating substrate; wherein, the through holes are formed on the insulating substrate. hole, the metal plug is filled in the through hole; at least three of the metal films are formed on the first main surface of the insulating substrate with the through hole; two of the metal film is formed on the second main surface of the insulating substrate with through holes; the two metal films formed on the second main surface are formed on the first The corresponding two metal films on the main surface are electrically connected through the metal plugs; the plurality of metal films formed on the same main surface are electrically insulated from each other; the vertical structure LED units are respectively arranged on On the metal film on the first main surface of the insulating substrate with through holes; the vertical structure LED units are electrically connected in series, so that the vertical structure LED chips can withstand high voltage. 2. according to the vertical structure LED chip of claim 1, it is characterized in that, described vertical structure LED unit comprises: (1) semiconductor epitaxial film, comprises: first type confinement layer, activation layer and second type confinement layer; The activation layer is stacked between the first type confinement layer and the second type confinement layer; the semiconductor epitaxial thin film is formed on the metal film; (2) passivation layer; the a passivation layer covering the support substrate, the metal film and the semiconductor epitaxial film; forming a window at a predetermined position on the passivation layer above the semiconductor epitaxial film, The semiconductor epitaxial film is exposed in the window; a window is formed at a predetermined position on the passivation layer above the metal film, and the metal film is exposed in the window (3) The metal electrode is laminated on the semiconductor epitaxial film through the window and extends to the metal film of a predetermined adjacent vertical structure LED unit and passes through the metal film of the adjacent vertical structure LED unit. The window on the metal film forms an electrical connection with the metal film, so that two adjacent vertical structure LED units form an electrical connection in series. 3. according to the vertical structure LED chip of claim 2, it is characterized in that, the material of described semiconductor epitaxial film is selected from a group of materials, and this group of materials comprises: (1) gallium nitride base material; (2) Gallium phosphide-based materials; (3) gallium nitrogen phosphide-based materials; (4) zinc oxide-based materials. 4. The vertical structure LED chip according to claim 1, wherein said insulating substrate comprises a silicon insulating substrate, or a ceramic insulating substrate, or a graphite foam insulating substrate, or a main surface with a layer of insulating layers of metal substrates. 5. The LED chip with vertical structure according to claim 4, wherein the ceramic insulating substrate comprises an aluminum nitride insulating substrate, or an aluminum oxide insulating substrate. 6. The vertical structure LED chip according to claim 1, wherein the arrangement of the vertical structure LED units on the support substrate comprises that the vertical structure LED units are arranged in a matrix of N rows and M columns , wherein, N≥1, M≥2; said vertical structure LED units are electrically connected in series.

Images