CN102103563A - High-speed transceiver - Google Patents

High-speed transceiver Download PDF

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Publication number
CN102103563A
CN102103563A CN 201010603341 CN201010603341A CN102103563A CN 102103563 A CN102103563 A CN 102103563A CN 201010603341 CN201010603341 CN 201010603341 CN 201010603341 A CN201010603341 A CN 201010603341A CN 102103563 A CN102103563 A CN 102103563A
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comma
described
detection module
data
signal
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CN 201010603341
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Chinese (zh)
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CN102103563B (en
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石进中
徐茂
李涛
傅东
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合肥昊特信息科技有限公司
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Abstract

The invention discloses a high-speed transceiver. The high-speed transceiver comprises a clock and data restoring circuit. The circuit comprises a data acquisition and conversion detection module, a clock restoring module, a COMMA detection module and a data time sequence regulation module, wherein the data acquisition and conversion detection module acquires an input differential signal and inputs the input differential signal into the COMMA detection module and the clock storing module; the clock restoring module receives a reference clock signal and an input signal of the data acquisition and conversion detection module, generates a restoring byte clock signal and inputs the restoring byte clock signal into the COMMA detection module; the COMMA detection module is used for detecting COMMA; and the data time sequence regulation module receives the input of the COMMA detection module, performs data parallelization and defines a byte boundary. The high-speed transceiver has the advantages that: the COMMA detection is integrated to the clock and data restoring circuit before data serialization, so the time delay is reduced, the number of transistors is decreased and the practicability is strong.

Description

High-speed transceiver

Technical field

The present invention relates to the high-speed transceiver technical field, especially with utilize the improvement type circuit to carry out that the high speed flow receives relevant with the network equipment of transmission and in order to the high-speed transceiver of minimizing Data Receiving/transmission delay.

Background technology

High-speed transceiver (SERDES) is as a kind of signal conversion equipment, its utilization scope is very extensive, fields such as covering communication, computing machine, industry and storage, and often be used between chip and the chip/module or on backboard/cable in the system of transferring large number of data.

In data communication or switching fabric application, high-speed transceiver is as the core link technology of implementing whole architecture, for the complicacy that reduces system, the design of simplified system, high-speed transceiver is designed to ASIC(Application Specific Integrated Circuit) (ASIC) usually, and an embedded SERDES who is used as in the asic chip carries out work; Wherein, a clock and data recovery (CDR) circuit is the Key Circuit of SERDES receiving end, and this circuit imports the phase place of data in order to tracking, to produce and output data clock signal synchronous (RBC).But, because the clock signal and the relation of importing between the data bit of data stream are fixing, so after finishing the clock and data recovery process, also need to carry out the COMMA detecting operation one time, " bit boundary " will import the data-signal that bit stream is divided into separation at each to be used for.

For the COMMA detecting operation, traditional method for designing just provides an outer logic circuit of separating from the clock and data recovery logical circuit, but externally in the logical circuit, the operation that detects for data com MA normally needs at least three even more clock period, therefore under these circumstances, adopt the independent logical algorithm not only to need more interface overhead (waste system resource), and COMMA detection required clock period itself also increased and received and the time delay of transmission data, and then greatly reduce transceiver speed.

With reference to shown in Figure 1, it is the functional block diagram of conventional transceiver.Described transceiver comprises transmitter and receiver, and wherein, transmitter comprises parallel data grabbing card, 8B/10B scrambler, serialization unit and TX Clock PLL; Described receiver comprises parallel data grabbing card, 10B/8B scrambler, COMMA code detector, parallelization unit and RX Clock PLL.For the data transmission of transmitter, parallel data bit TD8.10 and REFCCLK/TCB at first together are imported into parallel data grabbing card, secondly, through a 8B/10B scrambler 8 bit parallel data are converted to 10 bit parallel data, realizing the dc balance data stream and to increase the success ratio of data-switching, wherein the increase of this success ratio is to recover the possibility that byte clock signal (data that receive from receiver) is locked to the transmission data and realize by increasing.

Consult shown in Fig. 2, in the system configuration of traditional transceiver, the COMMA testing circuit is implemented as an independent circuit of ce circuit outside again.In general, traditional COMMA testing circuit is mainly used to detect the COMMA character, and it comprises a shift register array (not shown) that is connected to CDR.During operation, the COMMA testing circuit receives the parallel data among the CDR, and it is latching to shift register, and further itself and one group of COMMA character is carried out bit pattern relatively.When coupling in the COMMA character of parallel data of finding to import into and standard, then mean to detect a COMMA.

But, there are some shortcomings in this kind COMMA detection mode, and is specific as follows:

At first, owing to need to use a plurality of clock period to finish a COMMA detecting operation process, wherein, after data are by parallelization, a COMMA detecting operation needs 3 to 4 complete clock period, and in the process of this detecting operation since use shift register implement COMMA detect with latch, contrast and matched data position, and other data processing function is for being in idle state, therefore will inevitably cause tangible time delay under this kind mode, system performance also will be received influence greatly.

Secondly, owing to need to use many shift registers, also need more flip-flop circuit accordingly, therefore increased in integrated circuit (IC) design under this kind mode and the chip area that uses in making, again, because the increase of flip-flop circuit quantity, its power consumption and heat dissipation have also been brought restriction to the COMMA detecting operation.

Further, because the increase of time delay, the transceiver of being furnished with above-mentioned traditional C OMMA detecting device, especially for must satisfy sequential require, must be for the transceiver of more speed work, adopting the traditional COMMA detecting device of this kind is to be difficult to satisfy the sequential requirement.For example, transceiver with the fast speed operation of 3.125Gbps, it need be furnished with the internal clocking that is used for 20 bit parallel data-interfaces, 156.25MHz frequency, but for a logic comparator circuit that the 6.4ns clock period is arranged, time sequence allowance is very nervous, and for the 10 bit parallel data-interfaces that use the 312.5Mhz internal clocking, the COMMA detecting device must detect a COMMA at 3.2ns in the clock period.

Owing in the recovered clock operation of legacy system configuration, considered the shake factor, so the time sequence allowance that provides is provided traditional COMMA is very nervous, often do not satisfy the requirement of logical design, and because the border interface between the analog-and digital-logical circuit is unclean, traditional C OMMA detecting device with and system configuration also produced another potential problems, and this potential problems reason takes place is exactly that COMMA detects the clock source of logical circuit use recovered clock (RBC) as a register, therefore, the quality of RBC can directly have influence on the performance of logical circuit, RBC clock jitter even can cause COMMA to detect foundation or retention time that logical circuit does not satisfy trigger particularly, and can cause the bit error rate (BER) potentially.

In sum, the parallel bus of normal transceiver design at present can't have been satisfied actual application requirements far away, still there are more technical limitation in its conventional system configuration, promptly, be difficult to the demand of the time of satisfying, the obvious time delay that technical existence is caused by the COMMA detecting operation, transceiver speed is slow.

Summary of the invention

In view of the problem that prior art exists, fundamental purpose of the present invention is to provide the time delay of a kind of reception and transmission data little, receives and dispatches fireballing high-speed transceiver.

To achieve these goals, the present invention has adopted following technical proposals:

Described high-speed transceiver comprises the clock and data recovery circuit, comprise data acquisition and transition detection module, clock recovery module, COMMA detection module and data time sequence adjusting module in this circuit, wherein, described data acquisition and transition detection module be in order to gathering input differential signal, and and be about in its input COMMA detection module and the clock recovery module; Described clock recovery module receives the signal of reference clock signal and data acquisition and the input of transition detection module, and generation recovery byte clock signal is input to the COMMA detection module; Described COMMA detection module links to each other with transition detection module, clock recovery module and data time sequence adjusting module with data acquisition respectively, and receive and recover the input differential signal that byte clock signal and data acquisition and transition detection module transmit, and detect COMMA by a plurality of binary bits and the COMMA pattern of relatively recovering in the byte clock signal period; Described data time sequence adjusting module is in order to the input of reception COMMA detection module, and the parallelization of execution data, defines a byte boundary.

Further, described clock recovery circuitry comprises translate phase testing circuit, phase corrector, phase frequency detector, charge pump, low-pass filter and the voltage controlled oscillator that is connected in regular turn; Wherein, described translate phase testing circuit receives the signal of data acquisition and the input of transition detection module and detects the phase of input signals conversion; Described phase corrector receiving phase is changed and is produced frequency or phase clock signal according to this phase transition; Frequency or phase clock signal that described phase frequency detector receiving phase corrector produces, and according to frequency or phase differential generation charging and discharging signal; Described charge pump receives the charging and discharging signal that phase frequency detector produces, and produces charge pump signal according to this charging and discharging signal; Described low-pass filter receives this charge pump signal and passes through it is filtered high frequency noise; Described voltage controlled oscillator receives the signal after low-pass filter filters and generates and recovers the byte clock signal.

Further, described COMMA detection module comprises data latch unit and COMMA pattern search unit; Wherein, described data latch unit is in order to latch a plurality of binary bits; Described COMMA pattern search unit connects data latch unit, and in order to search COMMA pattern and detection COMMA.

In addition, in high-speed transceiver of the present invention, described charge pump comprises first charge pump and second charge pump; Wherein, the two ends of first charge pump are connected with second charge pump with phase frequency detector respectively; A second charge pump then end links to each other with first charge pump, and the other end then is connected in described low-pass filter.

Described COMMA pattern comprise COMMA detect be not activated, positive COMMA detects and is activated, negative COMMA detects and is activated and positive COMMA and negative COMMA detect and be activated.

High-speed transceiver of the present invention has the following advantages:

1) COMMA is detected a part that is integrated into the clock and data recovery circuit, and prior to data serializing, significantly reduced time delay, improved the speed of transceiver, and this COMMA detects and is designed in the core of clock and data recovery circuit, reduces the uncertainty of logical design.

2) circuit design that provides of the application of the invention, COMMA detects required number of transistors and can significantly reduce during practical application, has strengthened the dirigibility of high-speed transceiver design, has practical value.

Description of drawings

Fig. 1 is the functional block diagram of conventional transceiver;

The system configuration synoptic diagram that Fig. 2 detects for conventional transceiver COMMA;

Fig. 3 is the synoptic diagram of clock and data recovery circuit in the high-speed transceiver of the present invention;

Fig. 4 is the system layout that high-speed transceiver COMMA of the present invention detects;

Fig. 5 is the sequential chart of recovery byte clock of the present invention;

Fig. 6 is the synoptic diagram of COMMA detecting operation of the present invention.

Embodiment

Come high-speed transceiver of the present invention is described in further detail below in conjunction with accompanying drawing and specific embodiment.

With reference to shown in Figure 3, described clock and data recovery circuit comprises data acquisition and transition detection module 10, clock recovery module 20, COMMA detection module 30 and data time sequence adjusting module 40.

Described data acquisition and transition detection module 10 be in order to gathering input differential signal, and and be about in its input COMMA detection module 30 and the clock recovery module 20;

Described clock recovery module 20 receives the signal of reference clock signal and data acquisition and 10 inputs of transition detection module, and generation recovery byte clock signal is input to COMMA detection module 30;

Described COMMA detection module 30 respectively with data acquisition and transition detection module 10, clock recovery module 20 and data time sequence adjusting module 40 link to each other, and receive and recover the input differential signal that byte clock signal and data acquisition and transition detection module 10 are gathered, and detect COMMA by a plurality of binary bits and the COMMA pattern of relatively recovering in the byte clock signal period, wherein, described COMMA pattern comprises that the COMMA detection is not activated, positive COMMA detects and is activated, negative COMMA detects and is activated and positive COMMA and negative COMMA detect 4 kinds of patterns such as be activated.

Described data time sequence adjusting module 40 in order to the input of reception COMMA detection module 30, and is carried out the data parallelization after 30 operations of COMMA detection module, define a byte boundary.

In addition, when above-mentioned COMMA detection module 30 enables, can produce COMMA when detecting byte boundary and detect indicator signal.

In addition, clock recovery module 20 of the present invention further comprises translate phase testing circuit 201, phase corrector 202, phase frequency detector 203, charge pump 204, low-pass filter 205 and the voltage controlled oscillator 206 that is connected in regular turn; Wherein, described translate phase testing circuit 201 receives the signal of data acquisition and 10 inputs of transition detection module and detects the phase of input signals conversion; Described phase corrector 202 receiving phases are changed and are produced frequency or phase clock signal according to this phase transition; Frequency or phase clock signal that described phase frequency detector 203 receiving phase correctors 202 produce, and according to frequency or phase differential generation charging and discharging signal; Described charge pump 204 receives the charging and discharging signal that phase frequency detector 203 produces, and produces charge pump signal according to this charging and discharging signal, and during practical application, this charge pump can be 2, i.e. first charge pump 2041 and second charge pump 2042; Wherein, the two ends of first charge pump 2041 are connected with second charge pump 2042 with phase frequency detector 203 respectively; 2,042 one ends of second charge pump link to each other with first charge pump 2041, and the other end then is connected in described low-pass filter 205; Described low-pass filter 205 receives this charge pump signal and passes through it is filtered high frequency noise; Described voltage controlled oscillator 206 receives the signal after low-pass filter filters and generates and recovers the byte clock signal.

Described COMMA detection module 30 further comprises data latch unit (not shown) and COMMA pattern search unit (not shown); Wherein, described data latch unit is in order to latch a plurality of binary bits; Described COMMA pattern search unit connects data latch unit, and in order to search COMMA pattern and detection COMMA.

During practical operation, be that data and COMMA that data latch unit is exported are compared, in case COMMA pattern match, then can from a plurality of clocks that recover the byte clock signal, select a clock signal, and find out a COMMA byte boundary, further, the parallel data of this byte boundary can be exported according to the clock of selected particular phases.

Again referring to shown in Figure 4, compared to existing technologies, COMMA detection module 30 operations of the present invention are prior to the data bit parallelization, and be later than the data acquisition and the transition detection module 10 of input differential signal (RXP/RXN), therefore, high-speed transceiver under this kind system configuration need not the extra clock period to carry out COMMA and detects, and has significantly reduced time delay, has improved the speed of transceiver.

Shown in Fig. 5 and Fig. 6, it has shown recovery byte clock signal (Recovered Byte Clock, the sequential of sequential RBC) and COMMA detecting operation.

Among the figure, recover the byte clock signal and be multiphase clock by ck0 to ck9 mark, between differ 1/10th recovery byte clock signal periods successively.At first, input data bit d_in is moved into data latch unit, and further the output data of data latch unit is compared with COMMA, when in a single day the COMMA pattern mates, then a correct relatively clock signal can be selected by system from ck0 to ck9, finds out a COMMA byte boundary.Secondly, according to the clock of selected particular phases, the parallel data d_out[9:0 of described byte boundary] be output.

(1) positive COMMA detects the pattern that is activated

(Least Significant Bit, LSB), detailed process is as follows to search minimum effective bit in the data stream in positive COMMA detects.

For positive COMMA sequence, at first search position 0, and then search a 011111xxx.The Module Design method is: detect the input position constantly, determine COMMA.In case a certain sequences match is to the COMMA sequence, then this sequence can be shifted out by parallel, and this minimum effective bit is the minimum effective bit of COMMA.

Detailed step is as follows:

Activating COMMA detects;

Check input bit,, otherwise carried out for the 2nd step if the 3rd step was carried out in position 0;

Check next bit,, otherwise carried out for the 2nd step if the 4th step was carried out in position 0;

Check next bit,, otherwise carried out for the 3rd step if the 5th step was carried out in position 1;

Check next bit,, otherwise carried out for the 3rd step if the 6th step was carried out in position 1;

Check next bit,, otherwise carried out for the 3rd step if the 7th step was carried out in position 1;

Check next bit,, otherwise carried out for the 3rd step if the 8th step was carried out in position 1;

Check next bit,, otherwise carried out for the 3rd step if the 9th step was carried out in position 1;

In a single day COMMA is determined, and COMMA detection module 30 produces a COMMA and detects id signal, represents that this COMMA is locked.This COMMA detects id signal and also is used for selecting one group of data bit, and form is " xxx1111100 ".

(2) negative COMMA detects the pattern that is activated

In detecting, searches negative COMMA the LSB in the data stream

For negative COMMA sequence, COMMA detection module 30 begins to search position 1, and then searches a 100000xxx.The design of COMMA detection module 30 is: detect input position and definite COMMA constantly.If a certain sequences match is to negative COMMA sequence, then this sequence can be shifted out by parallel, and this minimum effective bit will be the minimum effective bit of COMMA.

Detailed step is as follows:

Activate COMMA and detect,

Check input bit,, otherwise carried out for the 2nd step if the 3rd step was carried out in position 1;

Check next bit,, otherwise carried out for the 2nd step if the 4th step was carried out in position 1;

Check next bit,, otherwise carried out for the 3rd step if the 5th step was carried out in position 0;

Check next bit,, otherwise carried out for the 3rd step if the 6th step was carried out in position 0;

Check next bit,, otherwise carried out for the 3rd step if the 7th step was carried out in position 0;

Check next bit,, otherwise carried out for the 3rd step if the 8th step was carried out in position 0;

Check next bit,, otherwise carried out for the 3rd step if the 9th step was carried out in position 0;

In a single day COMMA is determined, and COMMA detection module 30 produces a COMMA and detects id signal, represents that this COMMA is locked.This COMMA detects id signal also can be used for selecting one group of data bit, and form is " xxx0011111 ".

(3) positive COMMA and negative COMMA detect the pattern that is activated

In positive COMMA and negative COMMA detection, search the minimum effective bit in the data stream

In this COMMA sequence, its form can be " xxx1111100 ", perhaps " xxx0000011 ".Detailed step is as follows:

Activating COMMA detects;

Check signal bit,, otherwise carried out for the 9th step if the 3rd step was carried out in position 1;

Check next bit,, otherwise carried out for the 2nd step if the 4th step was carried out in position 1;

Check next bit,, otherwise carried out for the 3rd step if the 5th step was carried out in position 0;

Check next bit,, otherwise carried out for the 3rd step if the 6th step was carried out in position 0;

Check next bit,, otherwise carried out for the 3rd step if the 7th step was carried out in position 0;

Check next bit, if 0 carry out the 8th the step, otherwise carry out the 3rd the step;

Check next bit,, otherwise carried out for the 3rd step if the 15th step was carried out in position 0;

Check next bit,, otherwise carried out for the 3rd step if the 10th step was carried out in position 0;

Check next bit,, otherwise carried out for the 9th step if the 11st step was carried out in position 1;

Check next bit,, otherwise carried out for the 9th step if the 12nd step was carried out in position 1;

Check next bit,, otherwise carried out for the 9th step if the 13rd step was carried out in position 1;

Check next bit,, otherwise carried out for the 9th step if the 8th step was carried out in position 1;

Check next bit,, otherwise carried out for the 9th step if the 15th step was carried out in position 1;

In a single day COMMA is determined, and COMMA detection module 30 produces a COMMA and detects id signal, represents that this COMMA is locked.This COMMA detects id signal and also is used for selecting one group of data bit, and its form can be " xxx1111100 ", perhaps " xxx0000011 ".

As mentioned above, by using clock and data recovery circuit and COMMA to detect integrated mode, multiphase clock (ck0 to ck9) can be used to deal with data and carry data, when use on the historical facts or anecdotes border, the retardation rate of data transmission just can significantly be reduced, further, this kind mode is with respect to traditional design, and its transistorized quantity of carrying out the COMMA detection equally also can correspondingly reduce.

The above only is the preferred embodiments of the present invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to be done; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.

Claims (5)

1. high-speed transceiver, comprise the clock and data recovery circuit, it is characterized in that, this circuit comprises data acquisition and transition detection module, clock recovery module, COMMA detection module and data time sequence adjusting module, wherein, described data acquisition and transition detection module be in order to gathering input differential signal, and and be about in its input COMMA detection module and the clock recovery module; Described clock recovery module receives the signal of reference clock signal and data acquisition and the input of transition detection module, and generation recovery byte clock signal is input to the COMMA detection module; Described COMMA detection module links to each other with transition detection module, clock recovery module and data time sequence adjusting module with data acquisition respectively, and receive and recover the input differential signal that byte clock signal and data acquisition and transition detection module transmit, and detect COMMA by a plurality of binary bits and the COMMA pattern of relatively recovering in the byte clock signal period; Described data time sequence adjusting module is in order to the input of reception COMMA detection module, and the parallelization of execution data, defines a byte boundary.
2. according to the described high-speed transceiver of claim 1, it is characterized in that described clock recovery circuitry comprises translate phase testing circuit, phase corrector, phase frequency detector, charge pump, low-pass filter and the voltage controlled oscillator that is connected in regular turn; Wherein, described translate phase testing circuit receives the signal of data acquisition and the input of transition detection module and detects the phase of input signals conversion; Described phase corrector receiving phase is changed and is produced frequency or phase clock signal according to this phase transition; Frequency or phase clock signal that described phase frequency detector receiving phase corrector produces, and according to frequency or phase differential generation charging and discharging signal; Described charge pump receives the charging and discharging signal that phase frequency detector produces, and produces charge pump signal according to this charging and discharging signal; Described low-pass filter receives this charge pump signal and passes through it is filtered high frequency noise; Described voltage controlled oscillator receives the signal after low-pass filter filters and generates and recovers the byte clock signal.
3. according to the described high-speed transceiver of claim 1, it is characterized in that described COMMA detection module comprises data latch unit and COMMA pattern search unit; Wherein, described data latch unit is in order to latch a plurality of binary bits; Described COMMA pattern search unit connects data latch unit, and in order to search COMMA pattern and detection COMMA.
4. according to the described high-speed transceiver of claim 2, it is characterized in that described charge pump comprises first charge pump and second charge pump; Wherein, the two ends of first charge pump are connected with second charge pump with phase frequency detector respectively; A second charge pump then end links to each other with first charge pump, and the other end then is connected in described low-pass filter.
5. according to claim 1 or 3 described high-speed transceivers, it is characterized in that, described COMMA pattern comprise COMMA detect be not activated, positive COMMA detects and is activated, negative COMMA detects and is activated and positive COMMA and negative COMMA detect and be activated.
CN201010603341XA 2010-12-24 2010-12-24 High-speed transceiver CN102103563B (en)

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WO2013155893A1 (en) * 2012-04-20 2013-10-24 浪潮(北京)电子信息产业有限公司 Method and system for aligning high speed serial communication channels
CN103606367A (en) * 2013-11-22 2014-02-26 广东威创视讯科技股份有限公司 Signal cascade transmission method and signal cascade device

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CN1622067A (en) * 2003-11-26 2005-06-01 北京微辰信息技术有限公司 Method for high speed SATA interface data recovery and serial-parallel conversion and circuit module
US20050193290A1 (en) * 2004-02-25 2005-09-01 Cho James B. Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data buffer

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CN1310531A (en) * 2000-02-23 2001-08-29 华为技术有限公司 Error detection method for high speed data transmission
CN1622067A (en) * 2003-11-26 2005-06-01 北京微辰信息技术有限公司 Method for high speed SATA interface data recovery and serial-parallel conversion and circuit module
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WO2013155893A1 (en) * 2012-04-20 2013-10-24 浪潮(北京)电子信息产业有限公司 Method and system for aligning high speed serial communication channels
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