CN102083188B - Digital pre-distortion model-based loop gain control system and method - Google Patents
Digital pre-distortion model-based loop gain control system and method Download PDFInfo
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- CN102083188B CN102083188B CN 201010558073 CN201010558073A CN102083188B CN 102083188 B CN102083188 B CN 102083188B CN 201010558073 CN201010558073 CN 201010558073 CN 201010558073 A CN201010558073 A CN 201010558073A CN 102083188 B CN102083188 B CN 102083188B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/04—TPC
- H04W52/06—TPC algorithms
- H04W52/14—Separate analysis of uplink or downlink
- H04W52/143—Downlink power control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/04—TPC
- H04W52/18—TPC being performed according to specific parameters
- H04W52/22—TPC being performed according to specific parameters taking into account previous information or commands
- H04W52/225—Calculation of statistics, e.g. average, variance
Abstract
The invention discloses a digital pre-distortion model-based loop gain control system. The system comprises a core processing unit, a digital signal processing (DSP) unit, a field programmable gate array (FPGA) unit and a downlink gain adjustment unit, wherein the core processing unit is used for counting initial downlink power and initial feedback power before delivery, transmitting the initial downlink power and the initial feedback power to the DSP unit and transmitting a loop gain adjustment value Wdelta to the downlink gain adjustment unit; the DSP unit is used for calculating initial loop gain Wo according to the initial downlink power and the initial feedback power, solving the current loop gain Wr according to the current downlink power and feedback power, calculating the loop gain adjustment value Wdelta according to Wr and Wo, and reporting Wdelta to the core processing unit; the FPGA unit is used for counting the power of the current downlink and a feedback link and reporting the power to the DSP unit; and the downlink gain adjustment unit is used for adjusting the power of an input nonlinear amplifier. The invention also discloses a gain control method. By the system and the method, the operational stability of a digital pre-distortion system is improved.
Description
Technical field
The present invention relates to wireless communication technology field, be specifically related to loop gain control method and system based on the digital pre-distortion model.
Background technology
AGC (Automatic Gain Control, automatic gain control) is used for the loop gain control of descending main collection link in the GSM repeater, and to guarantee the stability of digital pre-distortion algorithm operation, operation is monitored to power amplifier simultaneously.
In the use of repeater, because the existence of digital pre-distortion, the unsteadiness that can occur GSM nonlinear power amplifier (abbreviation power amplifier) gain once in a while, and the further situation of amplification can appear in this unsteadiness in the closed-loop digital pre-distortion system, thereby causes the fluctuation of service of digital pre-distortion system.
Summary of the invention
The invention discloses a kind of loop gain control method and system based on the digital pre-distortion model, guarantee the stability of GSM digital pre-distortion system operation.
The invention discloses a kind of loop gain control system based on the digital pre-distortion model, it is characterized in that, comprising:
Core processing unit is used for adding up initial downlink power before dispatching from the factory and initial feedback power is handed down to the DSP unit and described loop gain adjusted value W Δ is handed down to descending gain adjusting unit;
The DSP unit, be used for according to initial downlink power and the initial loop gain Wo of initial feedback power calculation, try to achieve current loop gain Wr and calculate loop gain adjustment value W Δ according to described Wr and described Wo according to current descending power, feedback power, and described W Δ is reported core processing unit;
The FPGA unit is used for described DSP unit is added up and reported to the power of current down link and based on feedback link;
Descending gain adjusting unit is used for according to described W Δ the non-linear power of putting amplifier of input being adjusted.
Also disclose a kind of use based on the gain method of control of the loop gain control system of digital pre-distortion model, it is characterized in that, having comprised:
(1) core processing unit was added up initial downlink power and initial feedback power is handed down to the DSP unit before dispatching from the factory, and described DSP unit is according to described initial downlink power and the initial loop gain Wo of described initial feedback power calculation;
(2) the FPGA unit is added up the power of current down link and based on feedback link, and reports described DSP unit;
(3) big and current feedback power is bigger than initial feedback power if current descending power is than initial downlink power, and then current loop gain Wr is tried to achieve according to described current descending power and feedback power in described DSP unit;
(4) described DSP unit calculates loop gain adjustment value W Δ according to described Wr and described Wo, and described W Δ is reported described core processing unit;
(5) described core processing unit is handed down to descending gain adjusting unit with described W Δ, and described descending gain adjusting unit is adjusted importing the non-linear power of putting amplifier according to described W Δ.
The present invention coordinates to obtain the loop gain adjusted value by core processing unit, DSP unit and FPGA unit, carries out the power adjustment by descending gain adjusting unit, the stability of loop gain when having guaranteed the operation of GSM digital pre-distortion system.
Description of drawings
Fig. 1 is a system construction drawing of the present invention;
Fig. 2 is an embodiment flow chart of the inventive method.
Embodiment
Be the embodiment of system of the present invention below, system configuration of the present invention such as Fig. 1 comprise: DSP unit 101, core processing unit 102, FPGA unit 103, DA converting unit 104, descending gain adjusting unit 105, downlink radio frequency unit 106, non-linear power amplifier 107 and feedback radio frequency unit 108.Down link comprises DAC and descending gain adjusting unit 105 and downlink radio frequency unit 106 in the system; Based on feedback link comprises ADC and feedback radio frequency unit 108; Down link and based on feedback link provide signal for FPGA unit 103; The DA converting unit comprises ADC and DAC.
The invention discloses a kind of loop gain control system based on the digital pre-distortion model, comprising:
Descending gain adjusting unit 105 is used for according to this W Δ the non-linear power of putting amplifier of input being adjusted.
The present invention coordinates to obtain the loop gain adjusted value by DSP unit 101, core processing unit 102 and FPGA unit 103, carries out the power adjustment by descending gain adjusting unit, the stability of loop gain when having guaranteed the operation of GSM digital pre-distortion system.
Wherein this core processing unit 102 also is used for issuing current temperature adjusted value and current downstream attenuation value is given this DSP unit 101;
This DSP unit 101 also is used for calculating loop gain adjustment value W Δ according to this temperature adjusted value, this Wr and this Wo, and the loop gain adjusted value W1 after the W Δ is merged into the downstream attenuation value and obtains merging, and this W1 is reported this core processing unit 102;
This descending gain adjusting unit 105 also is used for adjusting according to this W1 the power of input nonlinear power amplifier.
This core processing unit 102 also is used for sending fault warning.
This DSP unit 101 also is used for processing that this W1 is rounded up, is that 0.5 adjusted value W3 reports this core processing unit 102 with the precision that obtains, and the adjusted value W2 that will cast out is handed down to this descending gain adjusting unit 105;
This descending gain adjusting unit 105 also is used for according to this W2 the power of input nonlinear power amplifier being adjusted.Increase fine gains mechanism and improved the adjustment precision.
With reference to figure 2, the inventive method is realized by following several steps:
201, add up initial power and calculate initial loop gain Wo;
Core processing unit added up initial downlink power before dispatching from the factory and initial feedback power is handed down to Digital Signal Processing (Digital Signal Processing, DSP) unit, this DSP unit is according to this initial downlink power and the initial loop gain Wo of this initial feedback power calculation.
202, statistics current power;
Field programmable gate array (Field-Programmable Gate Array, FPGA) add up the power of current down link and based on feedback link, and report this DSP unit by the unit.
203, calculate current loop gain Wr;
If current descending power is bigger than initial downlink power, and current feedback power is bigger than initial feedback power, and then current loop gain Wr is tried to achieve according to current descending power and feedback power in this DSP unit.
204, according to Wr and Wo calculate adjusting values;
This DSP unit calculates loop gain adjustment value W Δ according to this Wr and this Wo, and this W Δ is reported this core processing unit.
205, adjust power according to adjusted value.
This core processing unit is handed down to descending gain adjusting unit with this W Δ, and this descending gain adjusting unit is adjusted importing the non-linear power of putting amplifier according to this W Δ.
The present invention coordinates to obtain the loop gain adjusted value by core processing unit (embedded chip), DSP unit and FPGA unit, carries out the power adjustment by descending gain adjusting unit, the stability of loop gain when having guaranteed the operation of GSM digital pre-distortion system.
Wherein the step of FPGA unit statistics power is: the FPGA unit is with analog/digital converter (Analog-to-Digital Converter, ADC) data that report are carried out homophase and are asked mould to obtain this current descending power and (Digital to Analog Converter, the data that DAC) report are carried out quadrature and asked mould to obtain this current feedback power to digital/analog converter.
Also comprise step among Fig. 2 embodiment:
Core processing unit issues current temperature adjusted value and gives this DSP unit; Core processing unit issues current downstream attenuation value and gives this DSP unit; This current downstream attenuation value is the pad value that manually arranges;
This DSP unit calculates loop gain adjustment value W Δ according to this temperature adjusted value, this Wr and this Wo, and the loop gain adjusted value W1 after this W Δ is merged into this downstream attenuation value and obtains merging, and this W1 is reported this core processing unit;
If this W1 is greater than the threshold values of setting, then this core processing unit is handed down to this descending gain adjusting unit with this W1; This descending gain adjusting unit is adjusted the power of input nonlinear power amplifier according to this W1.
This step has increased temperature compensation value and the manually power control of the downstream attenuation value of setting, has further stablized the operation stability of pre-distortion system.
Further comprise: bigger fluctuation occurred if this W1, then judges current power amplifier gain less than the threshold values of setting, notified this core processing unit alarm and stop current AGC computing; If this W1, then notifies the core processing unit alarm less than 0 and stops current AGC computing.
Before reporting this W1 to core processing unit, comprising: the DSP unit is 0.5 adjusted value W3 to this W1 through obtaining precision after rounding up, and when the precision of this W3 is continuous when being 0.5 5 times, just carries out the step that reports to this core processing unit.Because power amplifier is non-linear, the statistics of FPGA unit has fluctuation to a certain degree, again because the precision of descending gain control unit is 0.5dB, therefore the performance number of statistics can occur ± fluctuation of 0.5dB, fine gains is worth unsettled phenomenon, increase shake removal function herein, reduced this wild effect.
This DSP unit will be handed down to this FPGA unit through the adjusted value W2 that is cast out in the processing procedure that rounds up, and be adjusted importing the non-linear power of putting amplifier by this FPGA unit.Increase fine gains mechanism herein, made the precision of adjusting bring up to 0.1dB.
Can also comprise step as the further improvement to Fig. 2 embodiment:
If this descending power is littler or this initial feedback power of this based on feedback link power ratio is little than this initial downlink power, then notifies the current loop of this core processing unit to adjust, and allow system enter idle condition.Need not operate this moment to loop.
If this Wr is littler than this Wo, then notify this core processing unit to surpass the concurrent warning of being out of order of adjusting range of loop.
The embodiment of the present invention of more than being somebody's turn to do does not constitute the restriction to protection range of the present invention.Any modification of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection range of the present invention.
Claims (11)
1. the loop gain control system based on the digital pre-distortion model is characterized in that, comprising:
Core processing unit is used for adding up initial downlink power before dispatching from the factory and initial feedback power is handed down to the DSP unit and loop gain adjusted value W Δ is handed down to descending gain adjusting unit;
The DSP unit, be used for according to described initial downlink power and the initial loop gain Wo of described initial feedback power calculation, try to achieve current loop gain Wr and calculate loop gain adjustment value W Δ according to described Wr and described Wo according to current descending power, feedback power, and described W Δ is reported core processing unit;
The FPGA unit is used for described DSP unit is added up and reported to the power of current down link and based on feedback link;
Descending gain adjusting unit is used for according to described W Δ the power of the nonlinear power amplifier of input being adjusted.
2. the loop gain control system based on the digital pre-distortion model according to claim 1, it is characterized in that described core processing unit also is used for issuing current temperature adjusted value and current downstream attenuation value is given described DSP unit and W1 is handed down to described descending gain adjusting unit;
Described DSP unit also is used for calculating loop gain adjustment value W Δ according to described temperature adjusted value, described Wr and described Wo, and the loop gain adjusted value W1 after the W Δ is merged into the downstream attenuation value and obtains merging, and described W1 is reported described core processing unit;
Described descending gain adjusting unit also is used for adjusting according to described W1 the power of input nonlinear power amplifier.
3. the loop gain control system based on the digital pre-distortion model according to claim 2 is characterized in that,
Described core processing unit also is used for sending fault warning;
Described DSP unit also is used for processing that described W1 is rounded up, is that 0.5 adjusted value W3 reports described core processing unit with the precision that obtains, and the adjusted value W2 that will cast out is handed down to described FPGA unit;
Described FPGA unit also is used for according to described W2 the power of input nonlinear power amplifier being adjusted.
4. the method that right to use requires 1 described loop gain control system to gain and control is characterized in that, comprising:
(1) core processing unit was added up initial downlink power and initial feedback power is handed down to the DSP unit before dispatching from the factory, and described DSP unit is according to described initial downlink power and the initial loop gain Wo of described initial feedback power calculation;
(2) the FPGA unit is added up the power of current down link and based on feedback link, and reports described DSP unit;
(3) if current descending power is bigger and current feedback power is bigger than initial feedback power than initial downlink power, then current loop gain Wr is tried to achieve according to current descending power and feedback power in described DSP unit;
(4) described DSP unit calculates loop gain adjustment value W Δ according to described Wr and described Wo, and described W Δ is reported described core processing unit;
(5) described core processing unit is handed down to descending gain adjusting unit with described W Δ, and described descending gain adjusting unit is adjusted the power of input nonlinear power amplifier according to described W Δ.
5. method according to claim 4, it is characterized in that the step of described FPGA unit statistics power: the data that the FPGA unit reports ADC are carried out homophase and are asked mould to obtain described current descending power and the data that DAC reports are carried out quadrature ask mould to obtain described current feedback power.
6. method according to claim 4 is characterized in that, also comprises step:
Described core processing unit issues current temperature adjusted value and gives described DSP unit;
Described core processing unit issues current downstream attenuation value and gives described DSP unit;
Described DSP unit calculates loop gain adjustment value W Δ according to described temperature adjusted value, described Wr and described Wo, and the loop gain adjusted value W1 after the stack of described W Δ and described downstream attenuation value obtained merging, and described W1 reported described core processing unit;
If described W1 is greater than the threshold values of setting, then described core processing unit is handed down to described descending gain adjusting unit with described W1;
Described descending gain adjusting unit is adjusted the power of input nonlinear power amplifier according to described W1.
7. method according to claim 4 is characterized in that, also comprises step:
The described initial feedback power of little or described current based on feedback link power ratio is little if described current descending power is than described initial downlink power, then notifies the current loop of described core processing unit to adjust, and allows system enter the IDLE state.
8. method according to claim 4 is characterized in that, also comprises step:
If described Wr is littler than described Wo, then notify described core processing unit to surpass the concurrent warning of being out of order of adjusting range of loop.
9. method according to claim 6 is characterized in that, also comprises step:
If described W1, then notifies described core processing unit alarm less than the threshold values of setting and stops current AGC computing; If described W1, then notifies described core processing unit alarm less than 0 and stops current AGC computing.
10. method according to claim 6, it is characterized in that, before reporting described W1 to described core processing unit, comprise: the DSP unit is 0.5 adjusted value W3 to described W1 through obtaining precision after rounding up, when the precision of described W3 is continuous when being 0.5 5 times, just carry out the step that reports to described core processing unit.
11. method according to claim 10, it is characterized in that, described DSP unit will be handed down to described FPGA unit through the adjusted value W2 that is cast out in the processing procedure that rounds up, and by described FPGA unit the power of input nonlinear power amplifier be adjusted.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010558073 CN102083188B (en) | 2010-11-24 | 2010-11-24 | Digital pre-distortion model-based loop gain control system and method |
| PCT/CN2011/082131 WO2012068961A1 (en) | 2010-11-24 | 2011-11-14 | Loop gain control system and method based on digital pre-distortion model |
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| CN 201010558073 CN102083188B (en) | 2010-11-24 | 2010-11-24 | Digital pre-distortion model-based loop gain control system and method |
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| CN102083188B true CN102083188B (en) | 2013-08-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107425897A (en) * | 2017-07-21 | 2017-12-01 | 京信通信技术(广州)有限公司 | Loop gain control system and method |
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| CN102083188B (en) * | 2010-11-24 | 2013-08-07 | 京信通信系统（中国）有限公司 | Digital pre-distortion model-based loop gain control system and method |
| CN103118426B (en) * | 2011-11-17 | 2016-03-16 | 京信通信系统（中国）有限公司 | broadband multi-channel power control method and device |
| CN107276647B (en) * | 2017-07-07 | 2023-10-10 | 京信网络系统股份有限公司 | Loop gain control system and method |
| CN110048785B (en) * | 2019-05-22 | 2022-02-08 | 东信和平科技股份有限公司 | Method for carrying out radio frequency calibration on NB-IOT module and related equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102083188B (en) * | 2010-11-24 | 2013-08-07 | 京信通信系统（中国）有限公司 | Digital pre-distortion model-based loop gain control system and method |
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- 2010-11-24 CN CN 201010558073 patent/CN102083188B/en active Active
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- 2011-11-14 WO PCT/CN2011/082131 patent/WO2012068961A1/en active Application Filing
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| CN1341992A (en) * | 2000-08-04 | 2002-03-27 | Lg电子株式会社 | Predistortion digital linearizing circuit and gain control method |
| US7738904B1 (en) * | 2005-06-30 | 2010-06-15 | Marvell International Ltd. | Systems and methods for calibrating power regulated communication circuitry |
| CN101350638A (en) * | 2008-09-04 | 2009-01-21 | 电子科技大学 | Linear transmitter using non-linear element |
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| CN107425897A (en) * | 2017-07-21 | 2017-12-01 | 京信通信技术(广州)有限公司 | Loop gain control system and method |
| CN107425897B (en) * | 2017-07-21 | 2021-03-12 | 京信通信系统（中国）有限公司 | Loop gain control system and method |
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| WO2012068961A1 (en) | 2012-05-31 |
| CN102083188A (en) | 2011-06-01 |
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