CN102044520B - Package carrier plate, package structure and manufacturing process of package carrier plate - Google Patents
Package carrier plate, package structure and manufacturing process of package carrier plate Download PDFInfo
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- CN102044520B CN102044520B CN 201010143715 CN201010143715A CN102044520B CN 102044520 B CN102044520 B CN 102044520B CN 201010143715 CN201010143715 CN 201010143715 CN 201010143715 A CN201010143715 A CN 201010143715A CN 102044520 B CN102044520 B CN 102044520B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The present invention discloses a package carrier plate, a package structure and a manufacturing process of the package carrier plate. The package carrier plate comprises the following components: a dielectric layer, a patterned conductive layer, a plurality of conductive columns and a patterned welding-proof layer. The dielectric layer is provided with a first surface, a second surface which is opposite from the first surface, and a plurality of openings. The patterned conductive layer is inserted into the first surface of the dielectric layer. The conductive columns are respectively configured in the openings. The openings extend from the second surface of the dielectric layer to the patterned conductive layer. Furthermore the conductive columns are connected with the patterned conductive layer. The patterned welding-proof layer is configured on the first surface of the dielectric layer and exposes partial patterned conductive layer.
Description
Technical field
The present invention relates to a kind of Chip Packaging, and particularly relate to a kind of encapsulating carrier plate, encapsulating structure and encapsulating carrier plate manufacture craft.
Background technology
The purpose of Chip Packaging is to protect exposed chip, reduces the density of chip contact and provide chip good heat radiation.A kind of common packaged type is that chip is mounted to an encapsulating carrier plate, and the contact of chip is electrically connected to encapsulating carrier plate.Therefore, the contact of chip distributes and can reconfigure through encapsulating carrier plate, distributes with the contact of the outer member that meets next level.
Summary of the invention
The present invention provides a kind of encapsulating carrier plate, in order to carries chips.
The present invention provides a kind of encapsulating structure, in order to packaged chip.
The present invention provides a kind of encapsulating carrier plate manufacture craft, in order to make encapsulating carrier plate.
A kind of encapsulating carrier plate proposed by the invention, it comprises a dielectric layer, a patterned conductive layer, a plurality of conductive pole and a patterned anti-soldering layer.Dielectric layer has a first surface and opposing a second surface and an a plurality of opening for first surface.Patterned conductive layer is embedded in the first surface of dielectric layer.These conductive poles are disposed at respectively in these openings, and wherein these openings extend to patterned conductive layer from the second surface of dielectric layer, and these conductive poles are connected with patterned conductive layer.Patterned anti-soldering layer is disposed on the first surface of dielectric layer, and exposes partially patterned conductive layer.
A kind of encapsulating structure proposed by the invention, it comprises an encapsulating carrier plate, a plurality of soldered ball, a chip, many bonding wires and a packing colloid.It comprises a dielectric layer, a patterned conductive layer, a plurality of conductive pole and a patterned anti-soldering layer encapsulating carrier plate.Dielectric layer has a first surface and opposing a second surface and an a plurality of opening for first surface.Patterned conductive layer is embedded in the first surface of dielectric layer.These conductive poles are disposed at respectively in these openings, and wherein these openings extend to patterned conductive layer from the second surface of dielectric layer, and these conductive poles are connected with patterned conductive layer.Patterned anti-soldering layer is disposed on the first surface of dielectric layer, and exposes partially patterned conductive layer.These soldered balls are disposed at the second surface of dielectric layer, and lay respectively on these conductive poles.Chip configuration and is positioned at the first surface of dielectric layer on encapsulating carrier plate, chip is electrically connected on the part that patterned conductive layer is exposed to patterned anti-soldering layer.Packing colloid coating chip and part encapsulating carrier plate.
A kind of encapsulating carrier plate proposed by the invention, it comprises a dielectric layer, a patterned conductive layer, a plurality of conductive pole, a pattern etched stop layer and a patterned anti-soldering layer.Dielectric layer has a first surface and opposing a second surface and an a plurality of perforation that extends to second surface from first surface for first surface.Patterned conductive layer is disposed on the first surface of dielectric layer, and covers an end of these perforations.These conductive poles are disposed at respectively in these perforations.The pattern etched stop layer is disposed in these perforations, and between these conductive poles and patterned conductive layer.Patterned anti-soldering layer is disposed on the first surface of dielectric layer, and the overlay pattern conductive layer, and wherein patterned anti-soldering layer exposes partially patterned conductive layer.
A kind of encapsulating structure proposed by the invention, it comprises an encapsulating carrier plate, a plurality of soldered ball, a chip, many bonding wires and a packing colloid.Encapsulating carrier plate comprises a dielectric layer, a patterned conductive layer, a plurality of conductive pole, a pattern etched stop layer and a patterned anti-soldering layer.Dielectric layer has a first surface and opposing a second surface and an a plurality of perforation that extends to second surface from first surface for first surface.Patterned conductive layer is disposed on the first surface of dielectric layer, and covers an end of these perforations.These conductive poles are disposed at respectively in these perforations.The pattern etched stop layer is disposed in these perforations, and between these conductive poles and patterned conductive layer.Patterned anti-soldering layer is disposed on the first surface of dielectric layer, and the overlay pattern conductive layer, and wherein patterned anti-soldering layer exposes partially patterned conductive layer.These soldered balls are disposed at the second surface of dielectric layer, and lay respectively on these conductive poles.Chip configuration and is positioned at the first surface of dielectric layer on encapsulating carrier plate, chip is electrically connected on the part that patterned conductive layer is exposed to patterned anti-soldering layer.Packing colloid coating chip and part encapsulating carrier plate.
A kind of encapsulating carrier plate manufacture craft proposed by the invention, it comprises the following steps.One conduction initiation layer is provided, and the initiation layer that wherein conducts electricity has a first surface and an opposing second surface for first surface.Form an etch stop layer on the second surface of conduction initiation layer.Form a conductive layer on etch stop layer.The pattern conductive initiation layer is to form a plurality of conductive poles.Remove etch stop layer and be exposed to the part outside these conductive poles, to expose the partially conductive layer.Pressing one dielectric layer is on conductive layer, and wherein dielectric layer exposes these conductive poles.Patterned conductive layer is to form a patterned conductive layer.Form a patterned anti-soldering layer on dielectric layer, wherein patterned anti-soldering layer exposes partially patterned conductive layer.
The present invention also proposes a kind of encapsulating carrier plate manufacture craft, and it comprises the following steps.One conduction initiation layer is provided, and the initiation layer that wherein conducts electricity has a first surface and an opposing second surface for first surface.Form a patterned conductive layer on the first surface of conduction initiation layer.Form a plurality of conductive poles on patterned conductive layer.Pressing one dielectric layer on the first surface of conduction initiation layer, dielectric layer overlay pattern conductive layer wherein, and expose these conductive poles.Remove the conduction initiation layer to exposing dielectric layer and patterned conductive layer.Form a patterned anti-soldering layer on dielectric layer, wherein patterned anti-soldering layer exposes partially patterned conductive layer.
Based on above-mentioned, the present invention is after forming earlier a plurality of and conductive pole that conductive layer (or patterned conductive layer) is electrically connected, and pressing one dielectric layer and makes dielectric layer expose the part of these conductive poles on conductive layer (or patterned conductive layer) again.Be compared to the existing dielectric layer that provides earlier; Be electrically connected the patterned conductive layer on the dielectric layer with via or the conductive hole that runs through dielectric layer again; Encapsulating structure of the present invention can have less package area having under the layout of same signal circuit with the existing chip encapsulating structure.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended accompanying drawing to elaborate as follows.
Description of drawings
Figure 1A is the generalized section of a kind of encapsulating structure of one embodiment of the invention;
Figure 1B to Fig. 1 H is the generalized section of the encapsulating structure of a plurality of embodiment of the present invention;
Fig. 2 A is the generalized section of a kind of encapsulating structure of another embodiment of the present invention;
Fig. 2 B to Fig. 2 D is the generalized section of the encapsulating structure of a plurality of embodiment of the present invention;
Fig. 3 A to Fig. 3 R illustrates the generalized section of a kind of encapsulating carrier plate manufacture craft of one embodiment of the invention;
Fig. 4 A to Fig. 4 Q illustrates the generalized section of a kind of encapsulating carrier plate manufacture craft of another embodiment of the present invention;
Fig. 5 A to Fig. 5 M illustrates the generalized section of a kind of encapsulating carrier plate manufacture craft of another embodiment of the present invention;
Fig. 6 A to Fig. 6 M illustrates the generalized section of a kind of encapsulating carrier plate manufacture craft of an embodiment more of the present invention.
The main element symbol description
10a～10h: encapsulating structure
100a～100d: encapsulating carrier plate
102: soldered ball
102a: first soldered ball
102b: second soldered ball
104: chip
106: bonding wire
108: packing colloid
109a, 109b: adhesion coating
110: dielectric layer
112: first surface
114: second surface
116: opening
120: patterned conductive layer
130a, 130b: conductive pole
140a, 140b: patterned anti-soldering layer
20a～20d: encapsulating structure
200a～200d: encapsulating carrier plate
202: soldered ball
204: chip
206: bonding wire
208: packing colloid
209a, 209b: adhesion coating
210: dielectric layer
212: first surface
214: second surface
216: perforation
220: patterned conductive layer
230a, 230b: conductive pole
240: the pattern etched stop layer
250a, 250b: patterned anti-soldering layer
300: encapsulating carrier plate
302: the conduction initiation layer
302a, 302b: conductive pole
303a: first surface
303b: second surface
304: the first photopolymer layers
306: the first carriers
308: etch stop layer
308a: pattern etched stop layer
312: conductive layer
312a: patterned conductive layer
314: the second photopolymer layers
316: the second carriers
318: dielectric layer
318a: opening
322: the three photopolymer layers
324: the three carriers
326: patterned anti-soldering layer
328: sealer
332: sealer
400: encapsulating carrier plate
402: the conduction initiation layer
402a: conductive pole
403a: first surface
403b: second surface
404: the first photopolymer layers
406: the first carriers
408: etch stop layer
408a: pattern etched stop layer
412: conductive layer
412a: patterned conductive layer
414: the second photopolymer layers
416: the second carriers
418: dielectric layer
418a: opening
422: the three photopolymer layers
424: the three carriers
426: patterned anti-soldering layer
428: sealer
432: sealer
500: encapsulating carrier plate
502: the conduction initiation layer
503a: first surface
503b: second surface
504: the first carriers
506: patterned conductive layer
508,508a: conductive pole
512: dielectric layer
512a: opening
514: photopolymer layer
516: the second carriers
518: patterned anti-soldering layer
522: sealer
524: sealer
600: encapsulating carrier plate
602: the conduction initiation layer
603a: first surface
603b: second surface
604: the first carriers
606: patterned conductive layer
608,608a: conductive pole
612: dielectric layer
612a: opening
614: photopolymer layer
616: the second carriers
618: patterned anti-soldering layer
622: sealer
624: sealer
Embodiment
Figure 1A is the generalized section of a kind of encapsulating structure of one embodiment of the invention.Please earlier with reference to Figure 1A, in the present embodiment, encapsulating structure 10a comprises an encapsulating carrier plate 100a, a plurality of soldered ball 102, a chip 104, many bonding wires 106 and a packing colloid 108.
In detail, encapsulating carrier plate 100a comprises a dielectric layer 110, a patterned conductive layer 120, a plurality of conductive pole 130a and a patterned anti-soldering layer 140a.Dielectric layer 110 has a first surface 112 and opposing a second surface 114 and an a plurality of opening 116 for first surface 112.Dielectric layer 110 can comprise resin material; Fluoram resin (Ammonium BifluorideAjinomotobuild-up film for example; ABF), bimaleimide resin (Bismaleimide Triazine; BT), the Polyimide resin (Polyimide, PI), liquid crystal polymer resin thing (LCP), epoxy resin (Epoxy).These resin materials can mix with glass fiber cellucotton pad or fill specialty fibers for example, to strengthen the structural strength of dielectric layer 110.
Patterned conductive layer 120 is embedded in the first surface 112 of dielectric layer 110.That is to say that patterned conductive layer 120 can be considered a kind of embedded line.These conductive poles 130a is disposed at respectively in these openings 116, and wherein these openings 116 are that second surface 114 from dielectric layer 110 extends to patterned conductive layer 120, and these conductive poles 130a is connected with patterned conductive layer 120.In the present embodiment, the height of these conductive poles 130a is respectively less than the degree of depth of these openings 116.Patterned anti-soldering layer 140a is disposed on the first surface 112 of dielectric layer 110, and exposes partially patterned conductive layer 120.
These soldered balls 102 are disposed at the second surface 114 of dielectric layer 110, and lay respectively on these conductive poles 130a.In the present embodiment, because the height of these conductive poles 130a is respectively less than the degree of depth of these openings 116, so the part of these soldered balls 102 is to lay respectively in these corresponding openings 116.
Because the encapsulating structure 10a of present embodiment replaces through the mode that these conductive poles 130a connects patterned conductive layer 120 (meaning is an embedded line) existingly to come electrical connection graph case conductive layer with via or the conductive hole that runs through dielectric layer; Therefore the encapsulating structure 10a of present embodiment can have less package area having under the layout of same signal circuit (meaning is the layout of patterned conductive layer) with the existing chip encapsulating structure.
Figure 1B is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to Figure 1A and Figure 1B; The encapsulating structure 10b of Figure 1B is similar with the encapsulating structure 10a of Figure 1A, and the two main difference part is: the adhesion coating 109b of the encapsulating structure 10b of Figure 1B is disposed between the partially patterned conductive layer 120 that patterned anti-soldering layer 140b exposed and chip 104 of encapsulating carrier plate 100b.
Fig. 1 C is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to Figure 1A and Fig. 1 C, the encapsulating structure 10c of Fig. 1 C is similar with the encapsulating structure 10a of Figure 1A, and the two main difference part is: the height of these conductive poles 130b of the encapsulating carrier plate 100c of Fig. 1 C equates in fact with the degree of depth of these openings 116.That is to say that the end of these conductive poles 130b and the second surface 114 of dielectric layer 110 trim in fact, and these soldered balls 102 only are disposed on corresponding these conductive poles 130b, and are not positioned at these corresponding openings 116.
Fig. 1 D is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to Figure 1A and Fig. 1 D; The encapsulating structure 10d of Fig. 1 D is similar with the encapsulating structure 10a of Figure 1A, and the two main difference part is: the adhesion coating 109b of the encapsulating structure 10d of Fig. 1 D is disposed between the partially patterned conductive layer 120 that patterned anti-soldering layer 140b exposed and chip 104 of encapsulating carrier plate 100d.In addition, the height of these conductive poles 130b of encapsulating carrier plate 100d equates in fact with the degree of depth of these openings 116.That is to say that the end of these conductive poles 130b and the second surface 114 of dielectric layer 110 trim in fact, and these soldered balls 102 only are disposed on corresponding these conductive poles 130b, and are not positioned at these corresponding openings 116.
Fig. 1 E is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to Figure 1A and Fig. 1 E; The encapsulating structure 10e of Fig. 1 E is similar with the encapsulating structure 10a of Figure 1A; And the two main difference part is: these soldered balls 102 of the encapsulating structure 10e of Fig. 1 E comprise a plurality of first soldered ball 102a and one second soldered ball 102b; The orthographic projection overlaid of the second soldered ball 102b on orthographic projection on the first surface 112 of dielectric layer 110 and the first surface 112 of chip 104 wherein at dielectric layer 110, and the volume of each first soldered ball 102a is less than the volume of the second soldered ball 102b.
Fig. 1 F is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to Figure 1A and Fig. 1 F; The encapsulating structure 10f of Fig. 1 F is similar with the encapsulating structure 10a of Figure 1A, and the two main difference part is: the adhesion coating 109b of the encapsulating structure 10f of Fig. 1 F is disposed between the partially patterned conductive layer 120 and chip 104 that patterned anti-soldering layer 140b exposed.In addition; These soldered balls 102 of encapsulating structure 10f comprise a plurality of first soldered ball 102a and one second soldered ball 102b; The orthographic projection overlaid of the second soldered ball 102b on orthographic projection on the first surface 112 of dielectric layer 110 and the first surface 112 of chip 104 wherein at dielectric layer 110, and the volume of each first soldered ball 102a is less than the volume of the second soldered ball 102b.
Fig. 1 G is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to Figure 1A and Fig. 1 G; The encapsulating structure 10g of Fig. 1 G is similar with the encapsulating structure 10a of Figure 1A; And the two main difference part is: these soldered balls 102 of the encapsulating structure 10g of Fig. 1 G comprise a plurality of first soldered ball 102a and one second soldered ball 102b; The orthographic projection overlaid of the second soldered ball 102b on orthographic projection on the first surface 112 of dielectric layer 110 and the first surface 112 of chip 104 wherein at dielectric layer 110, and the volume of each first soldered ball 102a is less than the volume of the second soldered ball 102b.In addition, the height of these conductive poles 130b equates in fact with the degree of depth of these openings 116.That is to say that the end of these conductive poles 130b and the second surface 114 of dielectric layer 110 trim in fact, and these first soldered balls 102a only is disposed on corresponding these conductive poles 130b with the second soldered ball 102b, and is not positioned at these corresponding openings 116.
Fig. 1 H is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to Figure 1A and Fig. 1 H; The encapsulating structure 10h of Fig. 1 H is similar with the encapsulating structure 10a of Figure 1A, and the two main difference part is: the adhesion coating 109b of the encapsulating structure 10h of Fig. 1 H is disposed between the partially patterned conductive layer 120 and chip 104 that patterned anti-soldering layer 140b exposed.In addition; These soldered balls 102 of encapsulating structure 10h comprise a plurality of first soldered ball 102a and one second soldered ball 102b; The orthographic projection overlaid of the second soldered ball 102b on orthographic projection on the first surface 112 of dielectric layer 110 and the first surface 112 of chip 104 wherein at dielectric layer 110, and the volume of each first soldered ball 102a is less than the volume of the second soldered ball 102b.Moreover the height of these conductive poles 130b equates in fact with the degree of depth of these openings 116.That is to say that the end of these conductive poles 130b and the second surface 114 of dielectric layer 110 trim in fact, and these first soldered balls 102a only is disposed on corresponding these conductive poles 130b with the second soldered ball 102b, and is not positioned at these corresponding openings 116.
Fig. 2 A is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please refer to Fig. 2 A, in the present embodiment, encapsulating structure 20a comprises an encapsulating carrier plate 200a, a plurality of soldered ball 202, a chip 204, many bonding wires 206 and a packing colloid 208.
In detail, encapsulating carrier plate 200a comprises a dielectric layer 210, a patterned conductive layer 220, a plurality of conductive pole 230a, a pattern etched stop layer 240 and a patterned anti-soldering layer 250a.Dielectric layer 210 has a first surface 212 and opposing a second surface 214 and an a plurality of perforation 216 that extends to second surface 214 from first surface 212 for first surface 212.Patterned conductive layer 220 is disposed on the first surface 212 of dielectric layer 210, and covers an end of these perforations 216.That is to say that patterned conductive layer 220 can be considered a kind of non-embedded line.These conductive poles 230a is disposed at respectively in these perforations 216.In the present embodiment, the height of these conductive poles 230a is respectively less than the degree of depth of these perforations 216.Pattern etched stop layer 240 is disposed in these perforations 216; And between these conductive poles 230a and patterned conductive layer 220; Wherein these conductive poles 230a can be electrically connected with patterned conductive layer 220 through pattern etched stop layer 240, and the material of pattern etched stop layer 240 for example is a nickel.Patterned anti-soldering layer 250a is disposed on the first surface 212 of dielectric layer 210, and overlay pattern conductive layer 220, and wherein patterned anti-soldering layer 250a exposes partially patterned conductive layer 220.
These soldered balls 202 are disposed at the second surface 214 of dielectric layer 210, and lay respectively at 230a on these conductive poles.In the present embodiment, because the height of these conductive poles 230a is respectively less than the degree of depth of these perforations 216, so the part of these soldered balls 202 is to lay respectively in these corresponding perforations 216.Chip 204 is disposed on the encapsulating carrier plate 200a, and is positioned at the first surface 212 of dielectric layer 210.In the present embodiment, encapsulating structure 20a more comprises an adhesion coating 209a, and wherein adhesion coating 209a is disposed between chip 204 and the patterned anti-soldering layer 250a, in order to chip 204 is adhered to encapsulating carrier plate 200a.
These bonding wires 206 are connected between the patterned conductive layer 220 that chip 204 and patterned anti-soldering layer 250a exposed, in order to be electrically connected chip 204 and patterned conductive layer 220.Packing colloid 208 coating chips 204, these bonding wires 206 and part encapsulating carrier plate 200a.
Because the encapsulating structure 20a of present embodiment comes the mode of electrical connection graph case conductive layer 220 (meaning is non-embedded line) to replace through these conductive poles 230a and pattern etched stop layer 240 existingly to come electrical connection graph case conductive layer with via or the conductive hole that runs through dielectric layer; Therefore the encapsulating structure 20a of present embodiment can have less package area having under the layout of same signal circuit (meaning is the layout of patterned conductive layer) with the existing chip encapsulating structure.
Fig. 2 B is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to figure 2A and Fig. 2 B; The encapsulating structure 20b of Fig. 2 B is similar with the encapsulating structure 20a of Fig. 2 A, and the two main difference part is: the adhesion coating 209b of the encapsulating structure 20b of Fig. 2 B is disposed between the partially patterned conductive layer 220 that patterned anti-soldering layer 250b exposed and chip 204 of encapsulating carrier plate 200b.
Fig. 2 C is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to figure 2A and Fig. 2 C, the encapsulating structure 20c of Fig. 2 C is similar with the encapsulating structure 20a of Fig. 2 A, and the two main difference part is: the height of these conductive poles 230b of the encapsulating carrier plate 200c of Fig. 2 C equates in fact with the degree of depth of these perforations 216.That is to say that the end of these conductive poles 230b and the second surface 214 of dielectric layer 210 trim in fact, and these soldered balls 202 only are disposed on corresponding these conductive poles 230b, and are not positioned at these corresponding perforations 216.
Fig. 2 D is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please be simultaneously with reference to figure 2A and Fig. 2 D; The encapsulating structure 20d of Fig. 2 D is similar with the encapsulating structure 20a of Fig. 2 A, and the two main difference part is: the adhesion coating 209b of the encapsulating structure 20d of Fig. 2 D is disposed between the partially patterned conductive layer 220 that patterned anti-soldering layer 250b exposed and chip 204 of encapsulating carrier plate 200d.In addition, the height of these conductive poles 230b of encapsulating carrier plate 200d equates in fact with the degree of depth of these perforations 216.That is to say that the end of these conductive poles 230b and the second surface 214 of dielectric layer 210 trim in fact, and these soldered balls 202 only are disposed on corresponding these conductive poles 230b, and are not positioned at these corresponding perforations 216.
In certain embodiments; Patterned conductive layer in order to the exposed surface of wire bonds on can be provided with a protective layer (not being shown among the figure); For example be nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin and alloy (like leypewter) thereof, silver or change the nickel palladium soak gold (Electroless Nickel Electroless Palladium ImmersionGold, ENEPIG).
Though among the aforesaid chip packing-body embodiment, chip all illustration is electrically connected with patterned conductive layer with the mode that routing engages.Yet, do not illustrate among the embodiment at another, as long as with the zone of the expose portion of patterned conductive layer design under chip, the mode that chip also can chip bonding (flip chip bonding) is electrically connected with patterned conductive layer.Detailed speech; Chip can be connected to the expose portion of patterned conductive layer through conductive projection, and conductive projection for example is solder bump (solder bump), copper post (copperpillar), copper bump (copper stud bump) or golden projection (golden stud bump).In addition, a primer can between chip and encapsulating carrier plate, be disposed, with the coated with conductive projection.
The present invention also provides the manufacture craft of making encapsulating carrier plate 300,400,500,600 following, and cooperates Fig. 3 A to Fig. 3 R, Fig. 4 A to Fig. 4 Q, Fig. 5 A to Fig. 5 M and Fig. 5 A to Fig. 6 M that encapsulating carrier plate 300,400,500,600 is carried out detailed explanation.
Fig. 3 A to Fig. 3 R illustrates the generalized section of a kind of encapsulating carrier plate manufacture craft of one embodiment of the invention.Please according to the encapsulating carrier plate manufacture craft of present embodiment, at first, a conduction initiation layer 302 be provided earlier with reference to figure 3A, the initiation layer 302 that wherein conducts electricity has a first surface 303a and an opposing second surface 303b for first surface 303a.In the present embodiment, conduction initiation layer 302 for example is a Copper Foil.
Then, please refer to Fig. 3 B, dispose one first carrier 306 and one first photopolymer layer 304 on the first surface 303a of conduction initiation layer 302, wherein first photopolymer layer 304 is between first carrier 306 and conduction initiation layer 302.
Then, please refer to Fig. 3 C, form an etch stop layer 308 on the second surface 303b of conduction initiation layer 302.In the present embodiment, the material of etch stop layer 308 for example is a nickel.
Then, please refer to Fig. 3 D, form a conductive layer 312 on etch stop layer 308.In the present embodiment, the material of conductive layer 312 for example is a copper.
Then; Please refer to Fig. 3 E; Remove first carrier 306 exposing first photopolymer layer 304, and dispose one second carrier 316 and one second photopolymer layer 314 on conductive layer 312, wherein second photopolymer layer 314 is between second carrier 316 and conductive layer 312.
Then, please be simultaneously with reference to figure 3E and with reference to figure 3F, pattern conductive initiation layer 302 is to form a plurality of conductive pole 302a.In the present embodiment, the step of pattern conductive initiation layer 302 comprises that patterning first photopolymer layer 304 is to form one first patterning photopolymer layer (not illustrating).Then, be an etching mask through the first patterning photopolymer layer, etching conduction initiation layer 302 to be forming these conductive poles 302a, and exposes etch stop layer 308.Afterwards, remove the first patterning photopolymer layer.
Then, please refer to Fig. 3 G, remove etch stop layer 308 and be exposed to the part outside these conductive poles 302a, exposing partially conductive layer 312, and form one be positioned at these conductive poles 302a below pattern etched stop layer 308a.
Then; Please be simultaneously with reference to figure 3H and Fig. 3 I; Provide a dielectric layer 318 above conductive layer 312; And through the mode of hot pressing dielectric layer 318 is pressure bonded on the conductive layer 312, wherein these conductive poles 302a passes dielectric layer 318 preformed a plurality of opening 318a respectively, makes dielectric layer 318 expose these conductive poles 302a.In the present embodiment, dielectric layer 318 for example is a fiber preimpregnation material (prepreg).
Then, please refer to Fig. 3 J, remove the part of these conductive poles 302a, to form a plurality of conductive pole 302b, wherein the height of each conductive pole 302b adds the thickness of the thickness of pattern etched stop layer 308a less than dielectric layer 318.
Then, please refer to Fig. 3 K, dispose one the 3rd photopolymer layer 322 on dielectric layer 318.
Then, please refer to Fig. 3 L, remove second carrier 316 that is positioned on second photopolymer layer 314, and dispose one the 3rd carrier 324 on the 3rd photopolymer layer 322, so that the 3rd photopolymer layer 322 is between the 3rd carrier 324 and dielectric layer 318.
Then, please be simultaneously with reference to figure 3L and Fig. 3 M, patterned conductive layer 312 is to form a patterned conductive layer 312a.In the present embodiment, the step of patterned conductive layer 312 comprises that patterning second photopolymer layer 314 is to form one second patterning photopolymer layer (not illustrating).Then, be an etching mask through the second patterning photopolymer layer, etching conductive layer 312 to be forming patterned conductive layer 312a, and exposes part dielectric layer 318.At last, remove the second patterning photopolymer layer.
Then, please refer to Fig. 3 N, form a patterned anti-soldering layer 326 on dielectric layer 318, wherein patterned anti-soldering layer 326 exposes partially patterned conductive layer 312a.
Then, please refer to Fig. 3 O, form a sealer 328 on the patterned conductive layer 312a that patterned anti-soldering layer 326 is exposed, wherein sealer 328 coats the patterned conductive layer 312a that patterned anti-soldering layer 326 is exposed.In this mandatory declaration be; Sealer 328 on the patterned conductive layer 312a is except the oxidation rate that can slow down patterned conductive layer 312a; When connection pad that this patterned conductive layer 312a engages as a routing, this sealer 328 also can increase the bond strength between patterned conductive layer 312a and the bonding wire (not illustrating).Sealer 328 for example be nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin and alloy (like leypewter) thereof, silver or change the nickel palladium soak gold (Electroless Nickel Electroless Palladium Immersion Gold, ENEPIG).Then, please refer to Fig. 3 P, remove the 3rd carrier 324, to expose the 3rd photopolymer layer 322.
Afterwards, please refer to Fig. 3 Q, remove the 3rd photopolymer layer 322, to expose dielectric layer 318 and these conductive poles 302b.
At last; Please refer to Fig. 3 R, form a sealer 332 on these conductive poles 302b, wherein sealer 332 for example is an anti oxidation layer (organic solderability preservative (Organic SolderabilityPreservative for example; OSP)), in order to slow down the oxidation rate of these conductive poles 302b.So far, accomplished the making of encapsulating carrier plate 300.The organic solderability preservative that is fit to use for example is a BTA system (benzotriazole), benzimidazole system (Benzimidazoles), and related derivatives.
Because present embodiment is to form these conductive poles 302a that is electrically connected with conductive layer 312 earlier; Pressing dielectric layer 318 is on conductive layer 312 again; And expose the part of these conductive poles 302a; Form patterned conductive layer 312 at last again, and accomplish the encapsulating carrier plate 300 that has non-embedded line and these conductive poles 302a simultaneously.Be compared to the existing dielectric layer that provides earlier; Come electrical connection graph case conductive layer with via or the conductive hole that runs through dielectric layer again; Encapsulating carrier plate 300 of the present invention can effectively reduce the area of encapsulation having under the layout of same signal circuit (meaning is the layout of patterned conductive layer 312) with the existing chip encapsulating carrier plate.
Fig. 4 A to Fig. 4 Q illustrates the generalized section of a kind of encapsulating carrier plate manufacture craft of another embodiment of the present invention.Please according to the encapsulating carrier plate manufacture craft of present embodiment, at first, a conduction initiation layer 402 be provided earlier with reference to figure 4A, the initiation layer 402 that wherein conducts electricity has a first surface 403a and an opposing second surface 403b for first surface 403a.In the present embodiment, conduction initiation layer 402 for example is a Copper Foil.
Then, please refer to Fig. 4 B, dispose one first carrier 406 and one first photopolymer layer 404 on the first surface 403a of conduction initiation layer 402, wherein first photopolymer layer 404 is between first carrier 406 and conduction initiation layer 402.
Then, please refer to Fig. 4 C, form an etch stop layer 408 on the second surface 403b of conduction initiation layer 402.In the present embodiment, the material of etch stop layer 408 for example is a nickel.
Then, please refer to Fig. 4 D, form a conductive layer 412 on etch stop layer 408.In the present embodiment, the material of conductive layer 412 for example is a copper.
Then; Please refer to Fig. 4 E; Remove first carrier 406 exposing first photopolymer layer 404, and dispose one second carrier 416 and one second photopolymer layer 414 on conductive layer 412, wherein second photopolymer layer 414 is between second carrier 416 and conductive layer 412.
Then, please be simultaneously with reference to figure 4E and with reference to figure 4F, pattern conductive initiation layer 402 is to form a plurality of conductive pole 402a.In the present embodiment, the step of pattern conductive initiation layer 402 comprises that patterning first photopolymer layer 404 is to form one first patterning photopolymer layer (not illustrating).Then, be an etching mask through the first patterning photopolymer layer, etching conduction initiation layer 402 to be forming these conductive poles 402a, and exposes etch stop layer 408.Afterwards, remove the first patterning photopolymer layer.
Then, please refer to Fig. 4 G, remove etch stop layer 408 and be exposed to the part outside these conductive poles 402a, exposing partially conductive layer 412, and form one be positioned at these conductive poles 402a below pattern etched stop layer 408a.
Then; Please be simultaneously with reference to figure 4H and Fig. 4 I; Provide a dielectric layer 418 above conductive layer 412; And through the mode of hot pressing dielectric layer 418 is pressure bonded on the conductive layer 412, wherein these conductive poles 402a passes dielectric layer 418 preformed a plurality of opening 418a respectively, makes dielectric layer 418 expose these conductive poles 402a.In the present embodiment, the thickness of dielectric layer 418 adds that with the height of each conductive pole 402a the thickness of pattern etched stop layer 408a is identical in fact, and dielectric layer 418 for example is a fiber preimpregnation material (Prepreg).
Then, please refer to Fig. 4 J, dispose one the 3rd photopolymer layer 422 on dielectric layer 418, wherein these conductive poles 402a directly contacts the 3rd photopolymer layer 422.
Then, please refer to Fig. 4 K, remove second carrier 416 that is positioned on second photopolymer layer 414, and dispose one the 3rd carrier 424 on the 3rd photopolymer layer 422, so that the 3rd photopolymer layer 422 is between the 3rd carrier 424 and dielectric layer 418.
Then, please be simultaneously with reference to figure 4K and Fig. 4 L, patterned conductive layer 412 is to form a patterned conductive layer 412a.In the present embodiment, the step of patterned conductive layer 412 comprises that patterning second photopolymer layer 414 is to form one second patterning photopolymer layer (not illustrating).Then, be an etching mask through the second patterning photopolymer layer, etching conductive layer 412 to be forming patterned conductive layer 412a, and exposes part dielectric layer 418.At last, remove the second patterning photopolymer layer.
Then, please refer to Fig. 4 M, form a patterned anti-soldering layer 426 on dielectric layer 418, wherein patterned anti-soldering layer 426 exposes partially patterned conductive layer 412a.
Then, please refer to Fig. 4 N, form a sealer 428 on the patterned conductive layer 412a that patterned anti-soldering layer 426 is exposed, wherein sealer 428 coats the patterned conductive layer 412a that patterned anti-soldering layer 426 is exposed.In this mandatory declaration be; Sealer 428 on the patterned conductive layer 412a is except the oxidation rate that can slow down patterned conductive layer 412a; When connection pad that this patterned conductive layer 412a engages as a routing, this sealer 428 also can increase the bond strength between patterned conductive layer 412 and the bonding wire (not illustrating).Sealer 428 for example be nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin and alloy (like leypewter) thereof, silver or change the nickel palladium soak gold (Electroless Nickel Electroless Palladium Immersion Gold, ENEPIG).
Then, please refer to Fig. 4 O, remove the 3rd carrier 424, to expose the 3rd photopolymer layer 422.
Afterwards, please refer to Fig. 4 P, remove the 3rd photopolymer layer 422, to expose dielectric layer 418 and these conductive poles 402a.
At last, please refer to Fig. 4 Q, form a sealer 432 on these conductive poles 402a, wherein sealer 432 for example is an anti oxidation layer, in order to slow down the oxidation rate of these conductive poles 402a.So far, accomplished the making of encapsulating carrier plate 400.
Fig. 5 A to Fig. 5 M illustrates the generalized section of a kind of encapsulating carrier plate manufacture craft of one embodiment of the invention.Please according to the encapsulating carrier plate manufacture craft of present embodiment, at first, a conduction initiation layer 502 be provided earlier with reference to figure 5A, the initiation layer 502 that wherein conducts electricity has a first surface 503a and an opposing second surface 503b for first surface 503a.In the present embodiment, conduction initiation layer 502 for example is a Copper Foil.
Then, please refer to Fig. 5 B, dispose one first carrier 504 on the second surface 503b of conduction initiation layer 502.
Then, please refer to Fig. 5 C, utilize half addition manufacture craft (semi-additive process) to form a patterned conductive layer 506 on the first surface 503a of conduction initiation layer 502.Particularly, with the temporary transient mask configuration of dielectric, photoresist or other suitable materials on conduction initiation layer 502.Then this mask of patterning is to form opening in patterned conductive layer 506 desired positions.Utilize conduction initiation layer 502 as negative electrode, form patterned conductive layer 506 in these openings, to electroplate.Remove the mask that this electroplates usefulness then.
Then, please refer to Fig. 5 D, utilize half addition manufacture craft (semi-additive process) to form a plurality of conductive poles 508 on patterned conductive layer 506.Particularly, with the temporary transient mask configuration of dielectric, photoresist or other suitable materials on the structure of Fig. 5 C.Then this mask of patterning is to form opening in these conductive pole 508 desired positions.Utilize conduction initiation layer 502 and patterned conductive layer 506 as negative electrode, form these conductive poles 508 in these openings, to electroplate.Remove the mask that this electroplates usefulness then.
Then; Please be simultaneously with reference to figure 5E and Fig. 5 F; Provide a dielectric layer 512 the conduction initiation layer 502 first surface 503a above; And the mode through hot pressing is pressure bonded to dielectric layer 512 on the first surface 503a of conduction initiation layer 502, and wherein these conductive poles 508 pass dielectric layer 512 preformed a plurality of opening 512a respectively, makes dielectric layer 512 overlay pattern conductive layers 506 and expose these conductive poles 508.In the present embodiment, dielectric layer 512 for example is a fiber preimpregnation material (Prepreg).
Then, please refer to Fig. 5 G, remove the part of these conductive poles 508, to form a plurality of conductive pole 508a, wherein the height of each conductive pole 508a adds the thickness of the thickness of patterned conductive layer 506 less than dielectric layer 512.In the present embodiment, the method that removes these conductive poles 508 comprises an etching step.
Then; Please refer to Fig. 5 H; Remove first carrier 504 exposing the second surface 503b of conduction initiation layer 502, and dispose one second carrier 516 and a photopolymer layer 514 on dielectric layer 512, wherein photopolymer layer 514 is between second carrier 516 and dielectric layer 512.
Then, please refer to Fig. 5 I, remove conduction initiation layer 502 to exposing dielectric layer 512 and patterned conductive layer 506.In the present embodiment, remove the conduction initiation layer 502 method comprise an etching step.
Then, please refer to Fig. 5 J, form a patterned anti-soldering layer 518 on dielectric layer 512, wherein patterned anti-soldering layer 518 exposes partially patterned conductive layer 506.
Then, please refer to Fig. 5 K, form a sealer 522 on the patterned conductive layer 506 that patterned anti-soldering layer 518 is exposed.In this mandatory declaration be; Sealer 522 on the patterned conductive layer 506 is except the oxidation rate that can slow down patterned conductive layer 506; When connection pad that this patterned conductive layer 506 engages as a routing, this sealer 522 also can increase the bond strength between patterned conductive layer 506 and the bonding wire (not illustrating).
Afterwards, please refer to Fig. 5 L, remove second carrier 516 and be positioned at the photopolymer layer 514 on second carrier 516, to expose dielectric layer 512 and these conductive poles 508a.
At last, please refer to Fig. 5 M, form 524 layers of surface protections on these conductive poles 508a, wherein sealer 524 for example is an anti oxidation layer, in order to slow down the oxidation rate of these conductive poles 508a.So far, accomplished the making of encapsulating carrier plate 500.
Because present embodiment is to form these conductive poles 508 that are electrically connected with patterned conductive layer 506 earlier; Pressing dielectric layer 512 is on patterned conductive layer 506 again; And expose the part of these conductive poles 508a, and accomplish the encapsulating carrier plate 500 that has embedded line and these conductive poles 508a simultaneously.Be compared to the existing dielectric layer that provides earlier; Come electrical connection graph case conductive layer with via or the conductive hole that runs through dielectric layer again; Encapsulating carrier plate 500 of the present invention can have less package area having under the layout of same signal circuit (meaning is the layout of patterned conductive layer 506) with the existing chip encapsulating carrier plate.
Fig. 6 A to Fig. 6 M illustrates the generalized section of a kind of encapsulating carrier plate manufacture craft of another embodiment of the present invention.Please according to the encapsulating carrier plate manufacture craft of present embodiment, at first, a conduction initiation layer 602 be provided earlier with reference to figure 6A, the initiation layer 602 that wherein conducts electricity has a first surface 603a and an opposing second surface 603b for first surface 603a.In the present embodiment, the material of conduction initiation layer 602 for example is a Copper Foil.
Then, please refer to Fig. 6 B, dispose one first carrier 604 on the second surface 603b of conduction initiation layer 602.
Then, please refer to Fig. 6 C, form a patterned conductive layer 606 on the first surface 603a of conduction initiation layer 602.
Then, please refer to Fig. 6 D, form a plurality of conductive poles 608 on patterned conductive layer 606.
Then; Please be simultaneously with reference to figure 6E and Fig. 6 F; Provide a dielectric layer 612 the conduction initiation layer 602 first surface 603a above; And the mode through hot pressing is pressure bonded to dielectric layer 612 on the first surface 603a of conduction initiation layer 602, and wherein these conductive poles 608 pass dielectric layer 612 preformed a plurality of opening 612a respectively, makes dielectric layer 612 overlay pattern conductive layers 606 and expose these conductive poles 608.In the present embodiment, dielectric layer 612 for example is a fiber preimpregnation material (Prepreg).
Then, please refer to Fig. 6 G, remove the part of these conductive poles 608, to form a plurality of conductive pole 608a, wherein the thickness of dielectric layer 612 adds that with the height of each conductive pole 608a the thickness of patterned conductive layer 606 is identical in fact.In the present embodiment, the method that removes these conductive poles 608 comprises an etching step.
Then; Please refer to Fig. 6 H; Remove first carrier 604 exposing the second surface 603b of conduction initiation layer 602, and dispose one second carrier 616 and a photopolymer layer 614 on dielectric layer 612, wherein photopolymer layer 614 is between second carrier 616 and dielectric layer 612.
Then, please refer to Fig. 6 I, remove conduction initiation layer 602 to exposing dielectric layer 612 and patterned conductive layer 606.In the present embodiment, remove the conduction initiation layer 602 method comprise an etching step.
Then, please refer to Fig. 6 J, form a patterned anti-soldering layer 618 on dielectric layer 612, wherein patterned anti-soldering layer 618 exposes partially patterned conductive layer 606.
Then, please refer to Fig. 6 K, form a sealer 622 on the patterned conductive layer 606 that patterned anti-soldering layer 618 is exposed.In this mandatory declaration be; Sealer 622 on the patterned conductive layer 606 is except the oxidation rate that can slow down patterned conductive layer 606; When connection pad that this patterned conductive layer 606 engages as a routing, this sealer 622 also can increase the bond strength between patterned conductive layer 606 and the bonding wire (not illustrating).
Afterwards, please refer to Fig. 6 L, remove second carrier 616 and be positioned at the photopolymer layer 614 on second carrier 616, to expose dielectric layer 612 and these conductive poles 608a.
At last, please refer to Fig. 6 M, form 624 layers of surface protections on these conductive poles 608a, wherein sealer 624 for example is an anti oxidation layer, in order to slow down the oxidation rate of these conductive poles 608a.So far, accomplished the making of encapsulating carrier plate 600.
In sum; Encapsulating carrier plate of the present invention replaces existing via or conductive hole through conductive pole; Can effectively reduce package area; And use the encapsulating structure of encapsulating carrier plate of the present invention, and have under the layout of same signal circuit with the existing chip encapsulating structure, can have less package area.
Though disclosed the present invention in conjunction with above embodiment; Yet it is not in order to limit the present invention; Be familiar with this operator in the technical field under any; Do not breaking away from the spirit and scope of the present invention, can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (15)
1. encapsulating structure comprises:
Encapsulating carrier plate comprises:
Dielectric layer has a first surface and opposing a second surface and an a plurality of opening for this first surface;
Patterned conductive layer is embedded in this first surface of this dielectric layer;
A plurality of conductive poles are disposed at respectively in those openings, and wherein those openings extend to this patterned conductive layer from this second surface of this dielectric layer, and those conductive poles are connected with this patterned conductive layer; And
Patterned anti-soldering layer is disposed on this first surface of this dielectric layer, and exposes this patterned conductive layer of part;
A plurality of soldered balls are disposed at this second surface of this dielectric layer, and lay respectively on those conductive poles, and wherein those soldered balls comprise a plurality of first soldered balls and one second soldered ball, and respectively the volume of this first soldered ball less than the volume of this second soldered ball;
Chip; Be disposed on this encapsulating carrier plate; And be positioned at this first surface of this dielectric layer; This chip is electrically connected on the part that this patterned conductive layer is exposed to this patterned anti-soldering layer, wherein the orthographic projection overlaid of this second soldered ball on the orthographic projection on this first surface of this dielectric layer and this chip this first surface at this dielectric layer; And
Packing colloid coats this chip and this encapsulating carrier plate of part.
2. encapsulating structure as claimed in claim 1 also comprises an adhesion coating, is disposed between this chip and this patterned anti-soldering layer.
3. encapsulating structure as claimed in claim 1 also comprises an adhesion coating, is disposed between this patterned conductive layer of part and this chip that this patterned anti-soldering layer exposes.
4. encapsulating structure as claimed in claim 1, wherein the height of those conductive poles makes each those soldered ball have at least part to be embedded in the corresponding opening respectively less than the degree of depth of those openings.
5. encapsulating structure as claimed in claim 1, wherein the height of those conductive poles equates in fact with the degree of depth of those openings.
6. encapsulating carrier plate manufacture craft comprises:
One conduction initiation layer is provided, and this conduction initiation layer has a first surface and an opposing second surface for this first surface;
Form an etch stop layer on this second surface of this conduction initiation layer;
Forming this etch stop layer before on this second surface of this conduction initiation layer; Dispose one first carrier and one first photopolymer layer on this first surface of this conduction initiation layer, wherein this first photopolymer layer is between this first carrier and this conduction initiation layer;
Form a conductive layer on this etch stop layer;
Remove this first carrier, and this first photopolymer layer of patterning is to form one first patterning photopolymer layer;
Through this first patterning photopolymer layer is an etching mask, and this conduction initiation layer of etching is to form a plurality of conductive poles;
Remove this first patterning photopolymer layer;
Remove this etch stop layer and be exposed to the part outside those conductive poles, to expose this conductive layer of part;
Form a dielectric layer on this conductive layer, wherein this dielectric layer exposes those conductive poles;
This conductive layer of patterning is to form a patterned conductive layer; And
Form a patterned anti-soldering layer on this dielectric layer, wherein this patterned anti-soldering layer exposes this patterned conductive layer of part.
7. encapsulating carrier plate manufacture craft as claimed in claim 6, wherein form this dielectric layer on this conductive layer after, also comprise:
Remove the part of those conductive poles, so that respectively the height of this conductive pole adds the thickness of the thickness of this etch stop layer less than this dielectric layer.
8. encapsulating carrier plate manufacture craft as claimed in claim 6, wherein form this dielectric layer on this conductive layer after, the thickness of this dielectric layer adds that with the height of this conductive pole respectively the thickness of this etch stop layer is identical in fact.
9. encapsulating carrier plate manufacture craft as claimed in claim 6 also comprises:
After this conductive layer of formation is on this etch stop layer, dispose one second carrier and one second photopolymer layer on this conductive layer, wherein this second photopolymer layer is between this second carrier and this conductive layer;
Before this conductive layer of patterning, remove this second carrier, and this second photopolymer layer of patterning is to form one second patterning photopolymer layer;
Through this second patterning photopolymer layer is an etching mask, and this conductive layer of etching is to form this patterned conductive layer; And
Remove this second patterning photopolymer layer.
10. encapsulating carrier plate manufacture craft as claimed in claim 6 also comprises:
After this dielectric layer of formation is on this conductive layer, dispose one the 3rd carrier and one the 3rd photopolymer layer on this dielectric layer, wherein the 3rd photopolymer layer is between the 3rd carrier and this dielectric layer; And
After this patterned anti-soldering layer of formation is on this dielectric layer, removes the 3rd carrier and be positioned at the 3rd photopolymer layer on the 3rd carrier.
11. an encapsulating carrier plate manufacture craft comprises:
One conduction initiation layer is provided, and this conduction initiation layer has a first surface and an opposing second surface for this first surface;
Utilize half addition manufacture craft (semi-additive process) to form a patterned conductive layer on this first surface of this conduction initiation layer;
Utilize half addition manufacture craft to form a plurality of conductive poles on this patterned conductive layer, wherein those conductive poles are directly connected in this patterned conductive layer;
Form a dielectric layer on this first surface of this conduction initiation layer, wherein this dielectric layer covers this patterned conductive layer, and exposes those conductive poles;
Remove this conduction initiation layer to exposing this dielectric layer and this patterned conductive layer; And
Form a patterned anti-soldering layer on this dielectric layer, wherein this patterned anti-soldering layer exposes this patterned conductive layer of part.
12. encapsulating carrier plate manufacture craft as claimed in claim 11, wherein form this dielectric layer on this first surface of this conduction initiation layer after, more comprise:
Remove the part of those conductive poles, so that respectively the height of this conductive pole adds the thickness of the thickness of this patterned conductive layer less than this dielectric layer.
13. encapsulating carrier plate manufacture craft as claimed in claim 11, wherein form this dielectric layer on this conduction initiation layer after, the thickness of this dielectric layer adds that with the height of this conductive pole respectively the thickness of this patterned conductive layer is identical in fact.
14. encapsulating carrier plate manufacture craft as claimed in claim 11 also comprises:
Forming this patterned conductive layer before on this first surface of this conduction initiation layer, dispose one first carrier on this second surface of this conduction initiation layer; And
Before removing this conduction initiation layer, remove this first carrier.
15. encapsulating carrier plate manufacture craft as claimed in claim 11 also comprises:
After this dielectric layer of formation is on this first surface of this conduction initiation layer, dispose one second carrier and a photopolymer layer on this dielectric layer, wherein this photopolymer layer is between this second carrier and this dielectric layer; And
After this patterned anti-soldering layer of formation is on this dielectric layer, removes this second carrier and be positioned at this photopolymer layer on this second carrier.
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| US25139609P | 2009-10-14 | 2009-10-14 | |
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| US29451910P | 2010-01-13 | 2010-01-13 | |
| US61/294,519 | 2010-01-13 |
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| CN102044520A CN102044520A (en) | 2011-05-04 |
| CN102044520B true CN102044520B (en) | 2012-11-07 |
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| CN 201010143715 Active CN102044520B (en) | 2009-10-14 | 2010-03-17 | Package carrier plate, package structure and manufacturing process of package carrier plate |
| CN 201010167361 Active CN102044515B (en) | 2009-10-14 | 2010-04-26 | Package carrier, package structure, and process for fabricating same |
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| TWI409920B (en) * | 2011-06-01 | 2013-09-21 | Powertech Technology Inc | Leadless leadframe type chip package preventing die pad from delamination |
| CN103066051B (en) * | 2011-10-20 | 2017-03-01 | 先进封装技术私人有限公司 | Base plate for packaging and its processing technology, semiconductor component packaging structure and processing technology |
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| TWI442530B (en) | 2014-06-21 |
| TW201114000A (en) | 2011-04-16 |
| CN102044515B (en) | 2013-05-01 |
| CN102044520A (en) | 2011-05-04 |
| TW201113999A (en) | 2011-04-16 |
| TWI489604B (en) | 2015-06-21 |
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