CN102034790A - Electric fuse structure and manufacturing method thereof - Google Patents
Electric fuse structure and manufacturing method thereof Download PDFInfo
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- CN102034790A CN102034790A CN2009101789095A CN200910178909A CN102034790A CN 102034790 A CN102034790 A CN 102034790A CN 2009101789095 A CN2009101789095 A CN 2009101789095A CN 200910178909 A CN200910178909 A CN 200910178909A CN 102034790 A CN102034790 A CN 102034790A
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- fuse
- electric fuse
- metal silicide
- negative electrode
- anode
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Abstract
The preferred embodiment of the invention discloses an electric fuse structure, which comprises a fuse body, an anode and a cathode, wherein the fuse body is arranged on the surface of a semiconductor substrate; the anode is electrically connected with one end of the fuse body; the cathode is electrically connected with the other end of the fuse body; and at least a part of the cathode is not provided with any silicified metal layer.
Description
Technical field
The invention relates to a kind of electric fuse structure, particularly a kind of electric fuse structure that on negative electrode, does not form metal silicide layer.
Background technology
Along with the microminiaturization of manufacture of semiconductor and the raising of complexity, semiconductor element easier various defective or the impurity of being subjected to that also becomes influences, and the inefficacy of single metal connecting line, diode or transistor etc. often promptly constitutes the defective of entire chip.Therefore in order to address this problem, existing technology just can form the connecting line (fusible links) of some fusible in integrated circuit, and fuse (fuse) just is to guarantee the utilizability of integrated circuit.
Generally speaking, fuse is the redundant circuit (redundancy circuit) that connects in the integrated circuit, in case detect when finding that partial circuit has defective, these connecting lines just can be used for repairing (repairing) or replacing these defective circuit.In addition, present fuse design more can provide the function of stylize (programmingelements), the circuit so that the different function design of various client Ke Yi is stylized.And from mode of operation, fuse roughly is divided into two kinds of thermo-fuse and electric fuses (eFuse).So-called thermo-fuse is to cut off by the step of a laser cutting (laser zip); As for electric fuse then is to utilize the principle of electromigration (electro-migration) to make fuse occur opening circuit, with effect that reaches repairing or the function that stylizes.In addition, the electric fuse in the semiconductor element can be for example polysilicon electric fuse (poly efuse), the anti-fuse of mos capacitance (MOS capacitor anti-fuse), diffusion electric fuse (diffusion fuse), contact plunger electric fuse (contact efuse), anti-fuse of contact plunger (contact anti-fuse) or the like.
On the typical case, the disconnection mechanism of electric fuse as shown in Figure 1, the negative electrode of one electric fuse structure 1 is electrically connected with the transistor drain of a device for fusing (blowing device) 2, on the anode of electric fuse structure 1, apply a voltage Vfs, apply a voltage Vg, transistorized source ground at transistorized grid.Electric current (I) flows to the negative electrode of electric fuse structure 1 by the anode of electric fuse structure 1, and electron stream (e-) is by the cathode system of electric fuse structure 1 anode to electric fuse structure 1.Employed electric current has one section preferable range when fusing, and when electric current was too low, the resistance of gained was too low, can make electrical migration imperfect, and electric current can cause the electric fuse thermal fracture when too high.
Fuse in the traditional electrical fuse-wires structure, negative electrode and anode normally are made of polycrystalline silicon material, and are provided with metal silicide layer and a plurality of contact plungers that are connected negative electrode and anode on the polycrystalline silicon material again.Metal silicide layer is mainly used to help form between each contact plunger and each electrode excellent electrical property and contacts.Set contact plunger then provides enough electron stream to negative electrode on the negative electrode, and flows in the polysilicon layer and metal silicide layer of fuse, produces electromigration, and fuse is disconnected.Generally for the blowout current of the electric fuse structure of 45nm processing procedure approximately between 9 milliampere to 14.5 milliamperes (mA).Yet, in order to reach this magnitude of current and also need usually the device for fusing of large-size (as MOS transistor etc.), not only on processing procedure, be difficult for making, also cause integrated level to reduce.Therefore, how to provide a kind of and can under reduced-current, be an important topic now with regard to the electric fuse structure that reaches electromigration.
Summary of the invention
Therefore the present invention discloses a kind of electric fuse structure, with the improvement shortcoming that above-mentioned electric fuse structure was met with now.
The preferred embodiment of the present invention is to disclose a kind of electric fuse structure, comprising: a fuse is located on the semiconductor substrate surface; One anode electrically connects an end of fuse; And one negative electrode electrically connect the other end of fuse, no any metal silicide layer (silicide) to the small part negative electrode wherein.
Another embodiment of the present invention is to disclose a kind of method of making electric fuse structure, comprises the following steps.The semiconductor substrate at first is provided, and has a transistor area and an electric fuse district at semiconductor-based the end.Form a transistor then on the semiconductor-based end of transistor area, and form a fuse, a negative electrode and an anode on the semiconductor-based end in electric fuse district.Then form a metal silicide barrier layer (SAB) and cover this cathode surface to small part, and then form a metal silicide layer in transistor area and part electric fuse district.
Description of drawings
Fig. 1 is the disconnection mechanism of a traditional efuse device.
Fig. 2 is the top view of an electric fuse structure of the preferred embodiment of the present invention.
Fig. 3 is along the schematic cross-section of tangent line BB ' among Fig. 2.
Fig. 4 to Fig. 6 is the top view of the electric fuse structure of different embodiments of the invention.
Fig. 7 is the top view of the electric fuse structure of one embodiment of the invention.
Fig. 8 to Fig. 9 integrates the processing procedure schematic diagram of a MOS transistor and an electric fuse structure for the present invention.
The main element symbol description
1 electric fuse structure, 2 device for fusing
30 insulating barriers of the semiconductor-based ends 31
32 polysilicon layers, 34 metal silicide layers
36 fuse, 38 anodes
40 negative electrodes, 42 metal silicide barrier layers
The 50 semiconductor-based ends of 46 contact plungers
52,54 shallow trench isolation structures, 56 gate electrodes
58 gate dielectrics, 60 electric fuse patterned layer
62,64 regions and source
66 sidewalls, 68 metal silicide layers
70 dielectric layers
72,74,76,78,80 contact plungers
82,84 metal interconnectings, 86 zones
88 regional 90 zones
92 metal silicide barrier layers
102 transistor area, 104 electric fuse districts
Embodiment
Please refer to Fig. 2 and Fig. 3, Fig. 2 is the top view of the electric fuse structure of one of preferred embodiment of the present invention, and Fig. 3 then is along the schematic cross-section of tangent line BB ' among Fig. 2.As shown in FIG., the present invention mainly provides semiconductor substrate 30 earlier, then the insulating barrier 31 that formation one is made of carbon silica hydride (SiCOH), silicon dioxide (SiO2) or silicon nitride (Si3N4) on the semiconductor-based end 30.Cover a polysilicon layer (figure does not show) then on the semiconductor-based end 30, and polysilicon layer carried out a pattern transfer producing process, for example utilize a patterning photoresist layer to be used as mask and remove the part polysilicon layer, on the insulating barrier 31 at the semiconductor-based end 30, to form a fuse (fuseelement) 36 that is constituted by the polysilicon layer 32 of patterning and the anode 38 and negative electrode 40 that connects fuse 36 two ends.In the present embodiment, though fuse 36 preferably is made of polycrystalline silicon material with anode 38, negative electrode 40, and the patterning process of following fuse 36 prepares simultaneously and gets, but be not limited to this, fuse 36 can comprise any electric conducting material again with the material of anode 38, negative electrode 40, for example polysilicon, metal or the combination of the two, and can be same to each other or different to each other.
Then carry out a metal silicide (silicide) processing procedure, metal silicide barrier layer (the salicide block that for example first formation one is made of silicon dioxide (SiO2), silicon nitride (SiN) or tetraethyl silane (TEOS), SAB) 42 and cover to small part negative electrode 40 surfaces, deposit a metal level that is constituted by cobalt, titanium, nickel, platinum, palladium or molybdenum etc. (figure does not show) then in the zone that unsilicided metal barrier 42 is covered, as the zones such as part negative electrode 40 of being covered to small part fuse 36, anode 38 and unsilicided metal barrier 42.Then carry out the annealing process that is rapidly heated, utilizing high temperature to make metal level and polysilicon layer 32 surface reactions is a metal silicide layer 34.Remove the unreacted metal layer at last again.
Cover a dielectric layer (figure do not show) then on fuse 36, negative electrode 40 and anode 38 and carry out a lithographic process, remove the dielectric layer of part, in dielectric layer, to form a plurality of contacts hole and to expose segment anode 38 and part negative electrode 40.Then in the contact hole, insert the metal material that is constituted by tungsten, aluminium, copper, tantalum, tantalum nitride, titanium or titanium nitride etc., to form the contact plunger 46 of a plurality of connection anodes 38 and negative electrode 40.So far promptly finish an electric fuse structure of the preferred embodiment of the present invention.
It should be noted that, though above-mentioned metal silicide barrier layer 42 preferably covers to small part negative electrode 40 surfaces, but be not limited to this, can adjust the area and the position on metal silicide barrier layer 42 again, and then control subsequent silicidation metal level 34 formed positions according to product demand.For instance, can be with reference to Fig. 4 to Fig. 6, Fig. 4 to Fig. 6 is located at the metal silicide barrier layer for different embodiments of the invention the top view of one electric fuse structure.For instance, 42 set positions, metal silicide of the present invention barrier layer can be adjusted arbitrarily according to process requirement, for example metal silicide barrier layer 42 can be located at regional 86 (as shown in Figure 4), 88 (as shown in Figure 5) of zone or regional 90 (as shown in Figure 6).Wherein, metal silicide the barrier layer 42 only contact plunger 46 of covered cathode 40 central authorities and fuse 36 partly represents in zone 86, so metal silicide layer 34 is preferably formed in two contact plunger 46 places at negative electrode 40 two ends and part not by on zone 86 fuse of being covered 36 and the anode 38.All contact plungers 46 and a part of fuse 36 of metal silicide barrier layer 42 covered cathodes 40 are represented in zone 88, so metal silicide layer 34 is preferably formed in part not by on zone 88 fuse of being covered 36 and the whole anode 38.Zone 90 represent metal silicide barrier layer 42 only covered cathode 40 contact plunger 46 but do not cover any fuse 36 and anode 38, so metal silicide layer 34 is preferably formed on whole fuse 36 and the anode 38.
Because the contact plunger 46 that is arranged on the anode 38 all is to contact with metal silicide layer 34, at least one contact plunger 46 that is arranged on the negative electrode 40 then is to run through silication metal barrier 42 and directly contact with polysilicon layer 32, therefore the resistance of electric fuse structure can be bigger at negative electrode 40 places, it is more to give birth to heat, temperature improves, and the tungsten metal generation electromigration that can help the contact plunger 46 of direct contact polysilicon layer 32 in the negative electrode 40 is to cause disconnection.According to the preferred embodiments of the present invention, utilize this electric fuse structure only to need just can disconnect whole electric fuse structure fully less than the electric current of 9 milliamperes, reach the effect of electromigration.In addition, another advantage of the present invention is, because the part of negative electrode 40 close fuse 36 there is no metal silicide layer 34, so in fusing process, be not supplemented to fuse 36 because of there being any metal silicide from negative electrode 40, the present invention can reduce the required time of blow out fuse whereby.
Secondly, though present embodiment is example at the formed contact plunger 46 of negative electrode 40 ends with single three, but the quantity of contact plunger 46 can be adjusted arbitrarily according to process requirement again, for example can form the contact plunger 46 of eight of two row's sums at negative electrode 40 ends, as shown in Figure 7, and can adjust the position that metal silicide barrier layer 42 is covered arbitrarily as the method on above-mentioned formation metal silicide barrier layer 42, this embodiment also belongs to the scope that the present invention is contained.
The above embodiment of the present invention is only made an electric fuse structure on the semiconductor-based end 30, but be not limited to above-mentioned design, the present invention can integrate the processing procedure of MOS transistor again according to process requirement when making electric fuse structure, this design also belongs to the scope that the present invention is contained.Please refer to Fig. 8 to Fig. 9, Fig. 8 to Fig. 9 integrates the processing procedure schematic diagram of a MOS transistor and an electric fuse structure for the present invention.As shown in Figure 8, at first provide semiconductor substrate 50, definition has a transistor area 102 and an electric fuse district 104 on it.Carry out one then and isolate (isolation) processing procedure, forming the isolation structure 52 of shallow isolating trough (STI) for example, and in the semiconductor-based end 50 in electric fuse district 104, form another shallow isolating trough 54 simultaneously simultaneously at the semiconductor-based end 50 between transistor area 102 and electric fuse district 104.Then comprehensively deposition one by dielectric layer (figure does not show) that oxide constituted on surface, the semiconductor-based ends 50, and form one by gate material layers (figure does not show) that polysilicon constituted on dielectric layer.Carry out a lithographic process then, remove the gate material layers and the dielectric layer of part, with one gate electrode 56 of formation on the semiconductor-based end 50 of transistor area 102 and the gate dielectric 58 that is located under it, and while formation one on the shallow isolating trough 54 in electric fuse district 104 has the electric fuse patterned layer 60 of fuse, negative electrode block and anode block.Though the gate material layers of present embodiment is made of polysilicon, is not limited to this, gate material layers can be made of materials such as metal, metal and polysilicon stacked on top again, and this all belongs to the scope that the present invention is contained.
Form the gate electrode 56 and electric fuse patterned layer 60 sidewalls of sidewall 66 then, and carry out an ion implantation process, in the semiconductor-based end 50 of sidewall 66 both sides of transistor area 102, to form source territory 62/64 in transistor area 102.Be noted that present embodiment is to be example with the sidewall of single structure 66 and source territory 62/64, but can form sidewall of sandwich construction and the making of the lightly doped drain of can arranging in pairs or groups simultaneously according to process requirement on the sidewall of gate electrode 56.For instance, can form off normal sidewall earlier, carry out a light dope ion then and inject, in the semiconductor-based end of the sub-both sides of off normal sidewall, to form a lightly doped drain in gate electrode sidewalls.Then around off normal sidewall, form major side wall, and carry out a heavy doping ion and inject, in the semiconductor-based end of the sub-both sides of major side wall, to form the source territory.In addition, the sequencing that forms off normal sidewall, major side wall, lightly doped drain and regions and source can be adjusted arbitrarily according to process requirement again, and is not limited to this.
Then carry out a metal silicide processing procedure, metal silicide barrier layer (the salicide block that for example first formation one is made of silicon dioxide (SiO2) or tetraethyl silane (TEOS), SAB) 92 and covering transistor district 102 not desire form the zone of metal silicide layer, as the zone beyond gate electrode 56 and the drain/source zone 62/64, and in the electric fuse district 104 electric fuse patterned layer 60 to the small part cathode surface.Cover a metal level that is constituted by cobalt, titanium, nickel, platinum, palladium or molybdenum etc. (figure does not show) then in zone that unsilicided metal barrier 92 is covered, and the annealing process that is rapidly heated is carried out in collocation, formation one metal silicide layer 68 on the part negative electrode that is covered with fuse, anode and unsilicided metal barrier 92 in the gate electrode 56 of transistor area 102 and regions and source 62/64 and electric fuse district 104, as shown in Figure 9.Remove the unreacted metal layer at last again, to finish a MOS transistor in transistor area 102 and to finish an electric fuse structure in electric fuse district 104.Mention as above-mentioned embodiment, metal silicide layer 68 preferably is located to small part fuse and anode, and also visual process requirement is provided with part metal silicide layer 68 on the negative electrode, does not add in addition at this and gives unnecessary details.
Deposit one then and cover transistor area 102 and electric fuse district 104 by the dielectric layer 70 that oxide or nitride constituted.Carry out a lithographic process subsequently, remove part dielectric layer 70 with form a plurality of contacts hole and expose gate electrode 56 tops of MOS transistor and regions and source 62,64 and electric fuse district 104 by the negative electrode that polycrystalline silicon material was constituted and the part metal silicide layer 68 of anode tap.
Then insert the metal material that constituted by tungsten, aluminium, copper, tantalum, tantalum nitride, titanium or titanium nitride etc. in the contact hole, a plurality ofly run through dielectric layer 70 and electrically connect MOS transistor and the contact plunger of electric fuse patterned layer 60 72/74/76/78/80 to form respectively in transistor area 102 and electric fuse district 104.Wherein, contact plunger 72/76/78/80 all directly contacts corresponding metal silicide layer 68, and contact plunger 74 then runs through silication metal barrier 92 and directly contacts polysilicon layer in the negative electrode.Can carry out a metal interconnecting processing procedure then, for example form a metal interconnecting 82 and connect contact plunger 76 on contact plunger 74 and the regions and source 62 on the negative electrodes and a metal interconnecting 84 and is connected contact plunger 72 and peripheral logical circuit on the anode.So far promptly finish the conformability MOS transistor and the electric fuse structure of another embodiment of the present invention.
The above only is the preferred embodiments of the present invention, and all equalizations of being done according to the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. electric fuse structure comprises:
One fuse is located on the semiconductor substrate surface;
One anode electrically connects an end of this fuse; And
One negative electrode electrically connects the other end of this fuse, wherein no any metal silicide layer to this negative electrode of small part.
2. electric fuse structure according to claim 1 does not wherein have any metal silicide layer on this negative electrode fully.
3. electric fuse structure according to claim 1, wherein no any metal silicide layer on this fuse of part.
4. electric fuse structure according to claim 1, wherein this anode is provided with a metal silicide layer.
5. electric fuse structure according to claim 1, wherein the width of this fuse is respectively less than the width of this anode and the width of this negative electrode.
6. electric fuse structure according to claim 1 comprises that more a plurality of contact plungers are electrically connected this negative electrode and this anode.
7. method of making electric fuse structure comprises:
The semiconductor substrate is provided, has a transistor area and an electric fuse district on this semiconductor-based end;
Form a transistor on this semiconductor-based end of this transistor area;
Form a fuse, a negative electrode and an anode on this semiconductor-based end in this electric fuse district;
Form a metal silicide barrier layer (SAB) and cover this cathode surface to small part; And
Form a metal silicide layer in this transistor area and this electric fuse district of part.
8. method according to claim 7 also comprises and utilizes this metal silicide barrier layer to cover this cathode surface fully.
9. method according to claim 7 also comprises and utilizes this metal silicide barrier layer portions to cover this fuse.
10. method according to claim 7 also comprises forming this metal silicide layer this transistorized regions and source in this transistor area.
11. method according to claim 7 also comprises forming this metal silicide layer this anode in this electric fuse district.
12. method according to claim 7 also comprises forming this metal silicide layer this fuse of part in this electric fuse district.
13. method according to claim 7 also comprises forming this metal silicide layer this negative electrode of part in this electric fuse district.
14. method according to claim 7 also comprises forming this metal silicide layer that a plurality of contact plungers connect this transistor area and this electric fuse district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101789095A CN102034790A (en) | 2009-09-28 | 2009-09-28 | Electric fuse structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101789095A CN102034790A (en) | 2009-09-28 | 2009-09-28 | Electric fuse structure and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN102034790A true CN102034790A (en) | 2011-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101789095A Withdrawn CN102034790A (en) | 2009-09-28 | 2009-09-28 | Electric fuse structure and manufacturing method thereof |
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| CN (1) | CN102034790A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165572A (en) * | 2011-12-16 | 2013-06-19 | 台湾积体电路制造股份有限公司 | Anti-fuses on semiconductor fins |
-
2009
- 2009-09-28 CN CN2009101789095A patent/CN102034790A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165572A (en) * | 2011-12-16 | 2013-06-19 | 台湾积体电路制造股份有限公司 | Anti-fuses on semiconductor fins |
| CN103165572B (en) * | 2011-12-16 | 2016-02-24 | 台湾积体电路制造股份有限公司 | Antifuse in semiconductor fin |
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Open date: 20110427 |