CN102006032B - High-speed comparer LATCH circuit - Google Patents
High-speed comparer LATCH circuit Download PDFInfo
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- CN102006032B CN102006032B CN 201010606599 CN201010606599A CN102006032B CN 102006032 B CN102006032 B CN 102006032B CN 201010606599 CN201010606599 CN 201010606599 CN 201010606599 A CN201010606599 A CN 201010606599A CN 102006032 B CN102006032 B CN 102006032B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 94
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
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Abstract
The invention relates to a high-speed comparer LATCH circuit which comprises a current source, a first MOS (Metal Oxide Semiconductor) transistor , a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor, wherein the source electrode of the first MOS transistor and the source electrode of the second MOS transistor are connected with the current source, grid electrodes of the first and the second MOS transistors are respectively used for receiving a first input voltage and a second input voltage, drain electrodes of the first and the second MOS transistors are respectively connected with source electrodes of the third and the fourth MOS transistors, the drain electrode of the third MOS transistor and the grid electrode of the fourth MOS transistor as well as the grid electrode of the sixth MOS transistor are respectively connected with the drain electrode of the fifth MOS transistor, the drain electrode of the fourth MOS transistor and the grid electrode of the third MOS transistor as well as the grid electrode of the fifth MOS transistor are respectively connected with the drain electrode of the sixth MOS transistor, and the source electrode of the fifth MOS transistor and the source electrode of the sixth MOS transistor are grounded. The invention can improve the conversion speed of the last stage of LATCH of a high-speed comparer, and acutely reduce the kick noise when the LATCH turns.
Description
Technical field
The present invention relates to microelectronic circuit, relate in particular to a kind of high-speed comparator LATCH (latch) circuit.
Background technology
As shown in Figure 1, if LATCH main circuit commonly used forms LATCH by two couples of metal-oxide-semiconductor M3, M4 and M5, M6 under positive feedback in the industry, wherein, PMOS pipe M1, M2 are the input pipes of LATCH, voltage Vin1, Vin2 are two incoming levels, X point and Y point are the inflow points that input current flows to the LATCH core, so that metal-oxide-semiconductor M3, M4 and M5, M6 form positive feedback.Just because of output point is just at X and Y point, therefore, X and Y point voltage excursion and frequency are all quite large, the shortcoming of this comparator configuration be counter-rotating kick back noise can be large and conversion speed be not the fastest.
Common solution is a pair of PMOS pipe on the pad below input PMOS pipe is right in the industry, forms CASCODE (cascade) structure; Although this structure can reduce to kick back noise slightly, X point or Y point are being transformed into high level in the time of the stage, and corresponding input pipe M1 or M2 can enter linear zone, and the situation that conversion speed reduces does not still improve; Particularly when two incoming level Vin1 and Vin2 were very low, the affected situation of speed was obvious especially.Therefore, In view of the foregoing, now in the urgent need to traditional LATCH circuit is carried out structural improvement.
Summary of the invention
The problem that exists in order to solve above-mentioned prior art, the present invention aims to provide a kind of high-speed comparer LATCH circuit, with the purpose of the conversion speed that realizes further improving high-speed comparator afterbody LATCH level.
A kind of high-speed comparer LATCH circuit of the present invention, it comprises a current source and the first to the 6th metal-oxide-semiconductor, wherein, the source electrode of the first metal-oxide-semiconductor be connected the source electrode of metal-oxide-semiconductor and be connected with described current source, their grid receives respectively the first input voltage and the second input voltage, their drain electrode is connected with the source electrode of described the 3rd metal-oxide-semiconductor and the source electrode of the 4th metal-oxide-semiconductor respectively, the drain electrode of described the 3rd metal-oxide-semiconductor, the grid of the grid of the 4th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor is connected with the drain electrode of described the 5th metal-oxide-semiconductor respectively, the drain electrode of described the 4th metal-oxide-semiconductor, the grid of the grid of the 3rd metal-oxide-semiconductor and the 5th metal-oxide-semiconductor is connected with the drain electrode of described the 6th metal-oxide-semiconductor respectively, the source electrode of the source electrode of described the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor ground connection that links to each other, described LATCH circuit also comprises the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, the drain electrode of described the 7th metal-oxide-semiconductor is connected with the source electrode of described the 3rd metal-oxide-semiconductor, and export the first output voltage, the drain electrode of described the 8th metal-oxide-semiconductor is connected with the source electrode of described the 4th metal-oxide-semiconductor, and export the second output voltage, and the source electrode of described the 7th metal-oxide-semiconductor is connected with the source electrode of the 8th metal-oxide-semiconductor, their the grid ground connection that links to each other.
In above-mentioned high-speed comparer LATCH circuit, described the first metal-oxide-semiconductor and the second metal-oxide-semiconductor are the NMOS pipe, and their source electrode is connected the output head grounding of this current source with the input of described current source.
Owing to having adopted above-mentioned technical solution, the present invention is by increasing a pair of PMOS pipe, i.e. the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, and with their grounded-grid, simultaneously the inflow point of input current is changed to the drain terminal of the PMOS pipe of new interpolation, thereby, can provide enough electric current to reach need high-speed, in addition, the variation in voltage of the inflow point of input current can be very little, thereby can sharply reduce the noise that kicks back in LATCH upset time.Simultaneously, the present invention also will change the NMOS pipe into as the first metal-oxide-semiconductor and second metal-oxide-semiconductor of input pipe, so that whole LATCH is not in the situation that need to reset and also can overturn.
Description of drawings
Fig. 1 is the structural representation of existing LATCH circuit;
Fig. 2 is the structural representation of a kind of high-speed comparer LATCH circuit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, specific embodiments of the invention are elaborated.
As shown in Figure 2, the present invention, i.e. a kind of high-speed comparer LATCH circuit, it comprises a current source Iss and the first to the 8th metal-oxide-semiconductor M1 to M8, wherein, the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6 are the NMOS pipe.The 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8 are the PMOS pipe.
The source electrode of the first metal-oxide-semiconductor M1 be connected the source electrode of metal-oxide-semiconductor M2 and be connected the output head grounding of current source Iss with the input of current source Iss;
The grid of the grid of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 receives respectively the first input voltage vin 1 and the second input voltage vin 2, and their drain electrode is connected with the source electrode of the 3rd metal-oxide-semiconductor M3 and the source electrode of the 4th metal-oxide-semiconductor M4 respectively;
The grid of the grid of the drain electrode of the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6 is connected with the drain electrode of the 5th metal-oxide-semiconductor M5 respectively, the grid of the grid of the drain electrode of the 4th metal-oxide-semiconductor M4, the 3rd metal-oxide-semiconductor M3 and the 5th metal-oxide-semiconductor M5 is connected with the drain electrode of the 6th metal-oxide-semiconductor M6 respectively, the source electrode of the source electrode of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 ground connection that links to each other;
The drain electrode of the 7th metal-oxide-semiconductor M7 is connected with the source electrode of the 3rd metal-oxide-semiconductor M3, and export the first output voltage V out1, the drain electrode of the 8th metal-oxide-semiconductor M8 is connected with the source electrode of the 4th metal-oxide-semiconductor M4, and export the second output voltage V out2, and the source electrode of the source electrode of the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 is connected to external power source VDD, their the grid ground connection that links to each other.
Among the present invention, X point and Y point voltage are near the value of external power source VDD, so the speed of LATCH circuit is very fast, the electric current that positive feedback needs can both be provided by external power source VDD that (this manages PMOS if do not add the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8, perhaps the grid voltage of the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 is earth-free, then X point or Y point voltage can descend in transfer process, power supply capacity also can reduce, can only reach at most the value of current source Iss, thereby affect the speed of LATCH, kicking back noise can be very not low yet), and X point and Y point voltage are very high, this can not be in degree of depth linear zone to the NMOS pipe the first metal-oxide-semiconductor M1 of input and the second metal-oxide-semiconductor M2, therefore input reaches the value of current source Iss to the conference of the difference between current of X point and the injection of Y point, therefore, needs only the suitable value of choosing current source Iss, the hysteresis voltage of whole LATCH circuit can be lower than the value of external power source VDD, thereby so that the LATCH circuit in the situation that do not need to reset and also can overturn.Also just because of in the conversion switching process, the voltage that X point and Y are ordered is all externally near the value of power vd D, therefore, LATCH circuit structure of the present invention kick back suitable little of noise, also less much than conventional structure employing input CASCODE structure.
Below embodiment has been described in detail the present invention by reference to the accompanying drawings, and those skilled in the art can make the many variations example to the present invention according to the above description.Thereby some details among the embodiment should not consist of limitation of the invention, and the scope that the present invention will define with appended claims is as protection scope of the present invention.
Claims (2)
1. high-speed comparer LATCH circuit, it comprises a current source and the first to the 6th metal-oxide-semiconductor, wherein, the source electrode of the first metal-oxide-semiconductor be connected the source electrode of metal-oxide-semiconductor and be connected with described current source, their grid receives respectively the first input voltage and the second input voltage, their drain electrode is connected with the source electrode of described the 3rd metal-oxide-semiconductor and the source electrode of the 4th metal-oxide-semiconductor respectively, the drain electrode of described the 3rd metal-oxide-semiconductor, the grid of the grid of the 4th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor is connected with the drain electrode of described the 5th metal-oxide-semiconductor respectively, the drain electrode of described the 4th metal-oxide-semiconductor, the grid of the grid of the 3rd metal-oxide-semiconductor and the 5th metal-oxide-semiconductor is connected with the drain electrode of described the 6th metal-oxide-semiconductor respectively, the source electrode of the source electrode of described the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor ground connection that links to each other, it is characterized in that, described LATCH circuit also comprises the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, the drain electrode of described the 7th metal-oxide-semiconductor is connected with the source electrode of described the 3rd metal-oxide-semiconductor, and export the first output voltage, the drain electrode of described the 8th metal-oxide-semiconductor is connected with the source electrode of described the 4th metal-oxide-semiconductor, and export the second output voltage, and the source electrode of described the 7th metal-oxide-semiconductor is connected with the source electrode of the 8th metal-oxide-semiconductor, their the grid ground connection that links to each other.
2. high-speed comparer LATCH circuit according to claim 1 is characterized in that, described the first metal-oxide-semiconductor and the second metal-oxide-semiconductor are the NMOS pipe, and their source electrode is connected the output head grounding of this current source with the input of described current source.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010606599 CN102006032B (en) | 2010-12-27 | 2010-12-27 | High-speed comparer LATCH circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010606599 CN102006032B (en) | 2010-12-27 | 2010-12-27 | High-speed comparer LATCH circuit |
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| CN102006032A CN102006032A (en) | 2011-04-06 |
| CN102006032B true CN102006032B (en) | 2013-02-13 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6493257B1 (en) * | 2002-03-27 | 2002-12-10 | International Business Machines Corporation | CMOS state saving latch |
| CN101207365A (en) * | 2006-12-20 | 2008-06-25 | 上海华虹Nec电子有限公司 | Gain bootstrap operational amplifier |
| CN201956985U (en) * | 2010-12-27 | 2011-08-31 | 上海贝岭股份有限公司 | Comparator latch circuit |
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2010
- 2010-12-27 CN CN 201010606599 patent/CN102006032B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6493257B1 (en) * | 2002-03-27 | 2002-12-10 | International Business Machines Corporation | CMOS state saving latch |
| CN101207365A (en) * | 2006-12-20 | 2008-06-25 | 上海华虹Nec电子有限公司 | Gain bootstrap operational amplifier |
| CN201956985U (en) * | 2010-12-27 | 2011-08-31 | 上海贝岭股份有限公司 | Comparator latch circuit |
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| CN102006032A (en) | 2011-04-06 |
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