CN101976999B

CN101976999B - Three-leg nine-switch inverter for driving double-alternating current motor

Info

Publication number: CN101976999B
Application number: CN2010105658743A
Authority: CN
Inventors: 黄雷; 窦汝振; 王慧波; 张勇; 杜智明; 米彦青
Original assignee: 中国汽车技术研究中心; 天津清源电动车辆有限责任公司
Priority date: 2010-11-30
Filing date: 2010-11-30
Publication date: 2012-05-02
Also published as: CN101976999A

Abstract

The invention discloses a three-leg nine-switch inverter for driving a double-alternating current motor. The inverter comprises a main loop, a first encoder, a second encoder, a current detection circuit, a digital signal processor, a driving circuit and a pulse width modulation signal generator, wherein the main loop comprises a direct current power supply, a filter capacitor, nine switching elements, a first current transformer and a second current transformer. One three-leg nine-switch inverter for driving the double-alternating current motor of the invention can be used for independently controlling two three-phase alternating current motors at the same time; and because the inverter comprises nine the switching elements and the number of the switching elements is reduced by three compared with that of the prior art, the volume of a controller and the number of the driving circuit can be reduced to effectively reduce the cost. In addition, the inverter has the advantages of rational structural design, high control accuracy, high practicability and the like.

Description

Be used for double cross and flow motor-driven three brachium pontis, nine switching inverters

Technical field

The present invention relates to a kind of inverter, particularly relate to and a kind ofly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters.

Background technology

A lot of industrial applications such as the motor vehicle that drives such as wheel hub motor, industrial robot, mine, electric locomotive all need realize the independent control of two or four alternating current machines.

Alternating current machine is normally driven by the DC-AC inverter of an AC power supply.The DC busbar voltage is supplied with inverter and is converted AC voltage to, is used to drive each phase of alternating current machine.Alternating current machine generally adopts three-phase structure.Microcontroller or digital signal processor are the typical elements that is used for control inverter; Come to apply predetermined driving voltage as the switch element gate signal of power device in their control inverters to alternating current machine; General pulse-width modulation (PWM) signal that adopts, the switch element of employing is generally IGBT or MOSFET.When needs are controlled two alternating current machines separately; Method commonly used at present has two kinds: a kind of is to dispose an inverter separately for every alternating current machine; Promptly use two inverters; Wherein every inverter all is three brachium pontis, comprises two switch elements in each brachium pontis, needs 12 switch elements altogether.Because the volume of controller is bigger when adopting two inverters, and the number of inverse parallel diode, drive circuit is more, so cost is higher.A kind of in addition method is to adopt an inverter to control two alternating current machines simultaneously; This moment, inverter was six brachium pontis, comprised two switch elements in each brachium pontis, and six brachium pontis are divided into two groups; Control an alternating current machine separately for every group; Though be merged into the quantity and a cost that can reduce parts such as inverter casing, radiator because of inverter by two when adopting this method, and the volume of controller reduces to some extent, because the number of switch element does not change; And the number of inverse parallel diode, drive circuit also reduces, so cost is still higher.

Summary of the invention

In order to address the above problem, the object of the present invention is to provide a kind of double cross that is used for that can effectively reduce cost to flow motor-driven three brachium pontis, nine switching inverters.

In order to achieve the above object, provided by the inventionly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and comprise: major loop, the 1st encoder, the 2nd encoder, current detection circuit, digital signal processor, drive circuit and pulse-width signal generator; Wherein, Three-phase brachium pontis and the 1st, the 2nd current transformer that major loop is formed by DC power supply, filtering capacitor, by 9 switch elements are formed; It has two three phase power output ports; Be connected with the 2nd three phase electric machine with the 1st three phase electric machine respectively; And 1st, the 2nd current transformer is installed in respectively on above-mentioned two three phase power output ports, and its two output ports are connected with two input ports of current detection circuit respectively, are used to detect the running current value of the 1st three phase electric machine and the 2nd three phase electric machine; The 1st encoder and the 2nd encoder are installed in respectively on the main shaft of the 1st three phase electric machine and the 2nd three phase electric machine, and its two output ports are connected with two input ports of digital signal processor respectively; Current detection circuit is the input interface circuit of the 1st, the 2 current transformer, and two input ports are connected with the 1st, the 2 current transformer respectively on it, and two output ports are connected with two input ports of digital signal processor respectively; Digital signal processor is the master controller of inverter, and its output port directly is connected with the pulse-width signal generator, and its input port is connected with the 2nd encoder and current detection circuit with the 1st encoder respectively; The pulse-width signal generator is the pwm pulse signal generating means, is connected between digital signal processor and the drive circuit; Drive circuit is the required gate drive circuit of switch element, is connected between pulse-width signal generator and the major loop.

Described major loop comprises: DC power supply, filter capacitor, 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH and the 1st, the 2nd current transformer; Wherein filter capacitor is the power-type filtering capacitor, and it is pressed for dc bus provides galvanic current after the DC power supply parallel connection; 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH form the three-phase bridge arm jointly; Wherein switch element UL, UM, UH are composed in series U phase brachium pontis; Switch element VL, VM, VH are composed in series V phase brachium pontis; Switch element WL, WM, WH are composed in series W phase brachium pontis, and U, V, W three-phase brachium pontis all are directly parallel on the dc bus; Three phase windings of the 1st three phase electric machine are connected between switch element UH and UM, VH and VM, WH and the WM; Three phase windings of the 2nd three phase electric machine are connected between switch element UL and UM, VL and VM, WL and the WM; 1st, the 2nd current transformer is installed in respectively on the major loop on the connecting line of two three phase power output ports and the 1st three phase electric machine and the 2nd three phase electric machine.

Described switch element UL, VL, WL, UM, VM, WM, UH, VH, WH are IGBT or MOSFET device.

Described pulse-width signal generator comprises pulse-width modulation signal generating circuit, the 1st, the 2nd reference signal generator and carrier signal generator; Wherein pulse-width modulation signal generating circuit comprises the 1st, the 2nd comparator, the 1st, the 2nd inverter and OR circuit; Wherein the 1st, the 2nd comparator is a voltage comparator; Be input to the positive input terminal of the 1st comparator after the 1st reference signal and the stack of the 1st shifted signal; Be input to the positive input terminal of the 2nd comparator after the 2nd reference signal and the stack of the 2nd shifted signal, carrier signal is input to the negative input end of the 1st, the 2nd comparator respectively; The output of the 1st comparator is the output of the required pulse-width signal of the last brachium pontis arteries and veins be made up of switch element UH, VH, WH; The output of the 1st comparator is connected with the input of the 1st inverter simultaneously, and the output of the 1st inverter then is connected with an input of OR circuit; Another input of OR circuit is connected with the output of the 2nd comparator, and its output is the output of the required wide modulation signal of the middle brachium pontis arteries and veins be made up of switch element UM, VM, WM; The input of the 2nd inverter is connected with the output of the 2nd comparator, and its output is the output of the required pulse-width signal of the following brachium pontis be made up of switch element UL, VL, WL; 1st, the 2nd reference signal generator is controlled sine wave signal generator, and it can produce the 1st reference signal and the 2nd reference signal that is used to control the 1st three phase electric machine and the 2nd three phase electric machine under the control of digital signal processor; Carrier signal generator is controlled triangular signal generator based, and it can produce triangular signal under the control of digital signal processor, thereby is that the 1st, the 2nd comparator provides carrier signal.

The model of described digital signal processor 7 is TMS320F28335.

Described the 1st encoder and the 2nd encoder are the photoelectric type pulse coder.

Provided by the inventionly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and can simultaneously two three phase alternating current motors be controlled separately by enough inverters; Because the number of switch element is 9 in the inverter; 3 have been reduced than prior art; So can reduce the volume of controller and the number of drive circuit, therefore can effectively reduce cost.In addition, this inverter also has advantages such as reasonable in design, control precision be high, practical.

Description of drawings

Fig. 1 is used for double cross and flows motor-driven three brachium pontis, nine switching inverter major loop primary structure sketch mapes for provided by the invention.

Fig. 2 is the operational mode sketch map that motor-driven three brachium pontis, nine switching inverter major loops are flowed in double cross that is used for shown in Fig. 1.

Fig. 3 is INV1 shown in Fig. 2 and INV2 gate pole pulse-width signal generating principle sequential chart.

Carrier signal and the reference waveform signal sketch map of Fig. 4 when the 1st carrier signal among Fig. 3 and the 2nd carrier signal being merged into a complete triangular signal.

Fig. 5 is used for double cross and flows motor-driven three brachium pontis, nine switching inverter pulse-width modulation signal generating circuit schematic diagrams for provided by the invention.

Fig. 6 is used for double cross and flows motor-driven three brachium pontis, nine switching inverters and form structural representation for provided by the invention.

Embodiment

In order to make the object of the invention, technical scheme clearer, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only is used to explain the present invention, and be not used in qualification the present invention.

Fig. 1 is used for double cross and flows motor-driven three brachium pontis, nine switching inverter major loop primary structure sketch mapes for provided by the invention.As shown in Figure 1, provided by the inventionly be used for double cross and flow motor-driven three brachium pontis, nine switching inverter major loops and mainly comprise: DC power supply E, filter capacitor C and 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH; Wherein filter capacitor C is the power-type filtering capacitor, and it is pressed for dc bus AB provides galvanic current after DC power supply E parallel connection; 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH are IGBT or MOSFET device; Form the three-phase brachium pontis altogether; Wherein switch element UL, UM, UH are composed in series U phase brachium pontis; Switch element VL, VM, VH are composed in series V phase brachium pontis, and switch element WL, WM, WH are composed in series W phase brachium pontis, and U, V, W three-phase brachium pontis all are directly parallel on the dc bus AB; Three phase windings of the 1st three phase electric machine 2 are connected between switch element UH and UM, VH and VM, WH and the WM; Three phase windings of the 2nd three phase electric machine 3 are connected between switch element UL and UM, VL and VM, WL and the WM.

Owing to adopted above-mentioned three brachium pontis, nine switch topology, each brachium pontis all contains three switch elements and two-way output on dc bus AB.Yet, be implemented in and drive two motors on the dc bus simultaneously independently, just must adopt the operational mode of timesharing control, promptly through the reasonable cooperation of 9 switch element switch motions, realize the timesharing control of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3.The relative theory and the control method of two motor timesharing controls are described through Fig. 2 and Fig. 3 below.

Fig. 2 is the operational mode sketch map that motor-driven three brachium pontis, nine switching inverter major loops are flowed in double cross that is used for shown in Fig. 1.As shown in Figure 2, the figure middle and upper part is divided into the pattern 1 that is used to drive the 1st three phase electric machine 2, and the top of brachium pontis is called INV1 in the pattern 1, the figure lower middle portion be used to drive the 2nd three phase electric machine 3 pattern 2, the lower part of brachium pontis is called INV2 in the pattern 2.INV1 comprises switch element UM, VM, WM, UH, VH, WH, and INV2 comprises switch element UM, VM, WM, UL, VL, WL.

Fig. 3 is INV1 shown in Fig. 2 and INV2 gate pole pulse-width signal generating principle sequential chart.As shown in Figure 3; The carrier signal that is used for pulse-width modulation has adopted unique waveform; Be characterized in: when the pulse-width signal of the 1st three phase electric machine 2 is operated; The 2nd reference signal that is used to control the 2nd three phase electric machine 3 always is lower than the 2nd carrier signal that is used for 3 controls of the 2nd three phase electric machine, and when the pulse-width signal of the 2nd three phase electric machine 3 was operated, the 1st reference signal that is used to control the 1st three phase electric machine 2 always was higher than the 1st carrier signal that is used for 2 controls of the 1st three phase electric machine.Therefore, when inverter drove the 1st three phase electric machine 2, switch element UL, VL, WL were in " opening " state, and when inverter drove the 2nd three phase electric machine 3, switch element UH, VH, WH were in " opening " state.In addition, the 1st carrier signal among Fig. 3 and the 2nd carrier signal can merge when producing gate electrode drive signals, and the carrier signal after the merging is a complete triangular signal.

Carrier signal and the reference waveform signal sketch map of Fig. 4 when the 1st carrier signal among Fig. 3 and the 2nd carrier signal being merged into a complete triangular signal.As shown in Figure 4, when the first half that is in triangular wave (be ordinate greater than zero part), calculate the pulse-width signal of INV1, when the latter half that is in triangular wave (being the minus part of ordinate), calculate the pulse-width signal of INV2.Order INV1 U phase reference voltage value INV2 U-phase voltage reference value and

$V_{u 1}^{ref} = A_{1} \sin (2 π f_{1} t + θ_{1})$

$V_{u 2}^{ref} = A_{2} \sin (2 π f_{2} t + θ_{2})$

Wherein: A ₁, A ₂Be amplitude, f ₁, f ₂Be frequency, θ ₁, θ ₂Be phase place.

Unified modulation rate m is:

$m = \frac{V_{ref}}{E / 2}$

Wherein: E is a d-c bus voltage value.

When calculating pulse-width signal, the 1st shifted signal E/4 is added on the 1st reference signal, the 2nd shifted signal-E/4 is added on the 2nd reference signal, thereby the modulation rate of the 1st reference signal and the 2nd reference signal is respectively:

$m_{1 u} = \frac{V_{u 1}^{ref} + E / 4}{E / 2} = \frac{V_{u 1}^{ref}}{E / 2} + \frac{1}{2}$

$m_{2 u} = \frac{V_{u 2}^{ref} - E / 4}{E / 2} = \frac{V_{u 2}^{ref}}{E / 2} - \frac{1}{2}$

Can reach a conclusion thus: the reference voltage range of INV1 and INV2 is respectively:

$- E / 4 \leq V_{u 1}^{ref} \leq E / 4$

$- E / 4 \leq V_{u 2}^{ref} \leq E / 4$

Fig. 5 is used for double cross and flows motor-driven three brachium pontis, nine switching inverter pulse-width modulation signal generating circuit schematic diagrams for provided by the invention.As shown in Figure 5, described pulse-width modulation signal generating circuit comprises the 1st, the 2nd comparator U1, U2, the 1st, the 2nd inverter U3, U4 and OR circuit U5; Wherein the 1st, the 2nd comparator U1, U2 are voltage comparator; Be input to the positive input terminal of the 1st comparator U1 after the 1st reference signal and the stack of the 1st shifted signal; Be input to the positive input terminal of the 2nd comparator U2 after the 2nd reference signal and the stack of the 2nd shifted signal, carrier signal is input to the negative input end of the 1st, the 2nd comparator U1, U2 respectively; The output of the 1st comparator U1 is the output of the required pulse-width signal of the last brachium pontis be made up of switch element UH, VH, WH; The output of the 1st comparator U1 is connected with the input of the 1st inverter U3 simultaneously, and the output of the 1st inverter U3 then is connected with the input of OR circuit U5; Another input of OR circuit U5 is connected with the output of the 2nd comparator U2, and its output is the output of the required pulse-width signal of the middle brachium pontis be made up of switch element UM, VM, WM; The input of the 2nd inverter U4 is connected with the output of the 2nd comparator U2, and its output is the output of the required pulse-width signal of the following brachium pontis be made up of switch element UL, VL, WL.

The course of work of pulse-width modulation signal generating circuit shown in Figure 5 is: the 1st reference signal and the 1st shifted signal stack back generate the INV1 signal; This signal compares with carrier wave (triangular wave) signal again; When INV1 signal during greater than carrier signal, the drive signal of switch element UH, VH, WH is effective; The 2nd reference signal and the 2nd shifted signal stack back generates the INV2 signal, and this signal compares with carrier signal again, and when INV2 signal during less than carrier signal, the drive signal of switch element UL, VL, WL is effective; The drive signal of switch element UM, VM, WM is for carrying out the resulting result of logical "or" with the inversion signal of the drive signal of switch element UL, VL, WL again after the drive signal negate of switch element UH, VH, WH.

Fig. 6 is used for double cross and flows motor-driven three brachium pontis, nine switching inverters and form structural representation for provided by the invention.As shown in Figure 6, provided by the inventionly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and comprise: major loop the 1, the 1st encoder the 4, the 2nd encoder 5, current detection circuit 6, digital signal processor (DSP) 7, drive circuit 8 and pulse-width signal generator 9; Wherein, Major loop 1 has adopted the topological structure that motor-driven three brachium pontis, nine switching inverter major loops are flowed in double cross that is used for shown in Figure 1; Three-phase brachium pontis and the 1st, the 2nd current transformer CT1 that it is formed by DC power supply E, filtering capacitor C, by 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH; CT2 forms; It has two three phase power output ports, be connected with the 2nd three phase electric machine 3 with the 1st three phase electric machine 2 respectively, and the 1st, the 2nd current transformer CT1 and CT2 is installed in respectively on above-mentioned two three phase power output ports; Its two output ports are connected with two input ports of current detection circuit 6 respectively, are used to detect the running current value of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3; The 1st encoder 4 and the 2nd encoder 5 are installed in respectively on the main shaft of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3, and its two output ports are connected with two input ports of digital signal processor 7 respectively; Current detection circuit 6 is the input interface circuit of the 1st, the 2nd current transformer CT1 and CT2; Two input ports link to each other with CT2 with the 1st, the 2nd current transformer CT1 respectively on it, and two output ports join with two input ports of digital signal processor 7 respectively mutually; Drive circuit 8 is switch element UL, VL, WL, UM, VM, WM, UH, VH, the required gate drive circuit of WH, is connected between pulse-width signal generator 9 and the major loop 1; Digital signal processor 7 is the master controller of inverter; Be responsible for accomplishing the control and the computing of whole inverter; Its output port directly is connected with pulse-width signal generator 9; Its input port is connected with the 2nd encoder 5 and current detection circuit 6 with the 1st encoder 4 respectively, thereby forms the control closed loop of electric current loop and rotating speed/position ring; Pulse-width signal generator 9 is the pwm pulse signal generating means; Effect is to produce the gate electrode drive signals (pulse-width signal) that is used to control three brachium pontis, nine switching inverter major loop switch elements provided by the invention; Its circuit is formed and mainly is made up of the pulse-width modulation signal generating circuit shown in Fig. 5, the 1st, the 2nd reference signal generator and carrier signal generator; Wherein pulse-width modulation signal generating circuit is made up of the 1st, the 2nd comparator U1, U2, the 1st, the 2nd inverter U3, U4 and OR circuit U5; Its effect is to generate required pulse-width signal according to the relation between the 1st, the 2nd reference signal and the carrier signal; 1st, the 2nd reference signal generator is controlled sine wave signal generator, and it can produce the 1st reference signal and the 2nd reference signal that is used to control the 1st three phase electric machine 2 and the 2nd three phase electric machine 3 under the control of digital signal processor 7; Carrier signal generator is controlled triangular signal generator based, and it can produce triangular signal under the control of digital signal processor 7, thereby is that the 1st, the 2nd comparator U1 and U2 provide carrier signal; The course of work of pulse-width signal generator 9 is: at first send command signal by digital signal processor 7; 1st, the 2nd reference signal generator and carrier signal generator produce corresponding the 1st reference signal, the 2nd reference signal and carrier signal according to the requirement of command signal; These signals enter among the pulse-width modulation signal generating circuit shown in Fig. 5; Thereby generate required pulse-width signal; Because whole inverter being used to of exporting drives the characteristic that the essential characteristic of the alternating current of three phase alternating current motor mainly depends on corresponding reference signal and carrier signal waveform; Therefore, digital signal processor 7 can reach the purpose of controlling the 1st, the 2nd three phase electric machine 2,3 independently through some characteristic (like frequency, amplitude etc.) of control the 1st reference signal, the 2nd reference signal and carrier signal.In addition, described controlled sine wave signal generator and controlled triangular signal generator based this area typical component commonly used that is, the software of available multiple routine or hardware approach are realized, therefore introduce no longer in detail here.

Described the 1st encoder 4 and the 2nd encoder 5 are the photoelectric type pulse coder.

The model of described digital signal processor 7 is TMS320F28335.

Be used for double cross and flow motor-driven three brachium pontis, the nine switching inverter courses of work and describe provided by the invention at present: described digital signal processor 7 obtains the speed/positional signal of the 1st three phase electric machines 2 and the 2nd three phase electric machine 3 through the 1st encoder the 4, the 2nd encoder 5; Obtain the running current information of the 1st three phase electric machine 2 and the 2nd three phase electric machine 3 simultaneously through current detection circuit 6; Produce the pulse-width signal that is used for all switch element UL, VL, WL, UM, VM, WM, UH, VH, WH on the driving main loop 1 through control pulse-width signal generator 9 after conversion and the computing then; And promote major loop 1 through drive circuit 8 and carry out work, come the 1st three phase electric machine 2 and the 2nd three phase electric machine 3 are carried out independent electric current and speed closed loop control with this.

Claims

1. one kind is used for double cross and flows motor-driven three brachium pontis, nine switching inverters, it is characterized in that: describedly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters and comprise: major loop (1), the 1st encoder (4), the 2nd encoder (5), current detection circuit (6), digital signal processor (7), drive circuit (8) and pulse-width signal generator (9); Wherein, Three-phase brachium pontis that major loop (1) is formed by DC power supply (E), filtering capacitor (C), by 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH and the 1st current transformer (CT1) and the 2nd current transformer (CT2) are formed; It has two three phase power output ports; Be connected with the 2nd three phase electric machine (3) with the 1st three phase electric machine (2) respectively; And the 1st current transformer (CT1) and the 2nd current transformer (CT2) are installed in respectively on above-mentioned two three phase power output ports; Its two output ports are connected with two input ports of current detection circuit (6) respectively, are used to detect the running current value of the 1st three phase electric machine (2) and the 2nd three phase electric machine (3); The 1st encoder (4) and the 2nd encoder (5) are installed in respectively on the main shaft of the 1st three phase electric machine (2) and the 2nd three phase electric machine (3), and its two output ports are connected with two input ports of digital signal processor (7) respectively; Current detection circuit (6) is the input interface circuit of the 1st current transformer (CT1) and the 2nd current transformer (CT2); Two input ports link to each other with the 2nd current transformer (CT2) with the 1st current transformer (CT1) respectively on it, and two output ports join with two input ports of digital signal processor (7) simultaneously; Digital signal processor (7) is the master controller of inverter, and its output port directly is connected with pulse-width signal generator (9), and its input port is connected with the 2nd encoder (5) and current detection circuit (6) with the 1st encoder (4) respectively; Pulse-width signal generator (9) is the pwm pulse signal generating means, is connected between digital signal processor (7) and the drive circuit (8); Drive circuit (8) is switch element UL, VL, W L, UM, VM, WM, UH, VH, the required gate drive circuit of WH, is connected between pulse-width signal generator (9) and the major loop (1).

2. according to claim 1ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: described major loop (1) comprising: DC power supply (E), filter capacitor (C), 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH and the 1st current transformers (CT1), the 2nd current transformer (CT2); Wherein filter capacitor (C) is the power-type filtering capacitor, and it is pressed for dc bus (AB) provides galvanic current after DC power supply (E) parallel connection; 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH form the three-phase bridge arm jointly; Wherein 3 switch element UL, UM, UH are composed in series U phase brachium pontis; 3 switch element VL, VM, VH are composed in series V phase brachium pontis; 3 switch element WL, WM, WH are composed in series W phase brachium pontis, and U, V, W three-phase brachium pontis all are directly parallel on the dc bus (AB); Three phase windings of the 1st three phase electric machine (2) are connected between switch element UH and switch element UM, switch element VH and switch element VM, switch element WH and the switch element WM; Three phase windings of the 2nd three phase electric machine (3) are connected between switch element UL and switch element UM, switch element VL and switch element VM, switch element WL and the switch element WM; The 1st current transformer (CT1) and the 2nd current transformer (CT2) are installed in respectively on the connecting line of last two the three phase power output ports of major loop (1) and the 1st three phase electric machine (2) and the 2nd three phase electric machine (3).

3. according to claim 2ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: described 9 switch element UL, VL, WL, UM, VM, WM, UH, VH, WH are IGBT or MOSFET device.

4. according to claim 1ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: described pulse-width signal generator (9) comprises pulse-width modulation signal generating circuit, the 1st, the 2nd reference signal generator and carrier signal generator; Wherein pulse-width modulation signal generating circuit comprises the 1st comparator (U1), the 2nd comparator (U2), the 1st inverter (U3), the 2nd inverter (U4) and OR circuit (U5); Wherein the 1st comparator (U1), the 2nd comparator (U2) are voltage comparator; Be input to the positive input terminal of the 1st comparator (U1) after the 1st reference signal and the stack of the 1st shifted signal; Be input to the positive input terminal of the 2nd comparator (U2) after the 2nd reference signal and the stack of the 2nd shifted signal, carrier signal is input to the negative input end of the 1st comparator (U1), the 2nd comparator (U2) respectively; The output of the 1st comparator (U1) is the output of the required pulse-width signal of the last brachium pontis be made up of 3 switch element UH, VH, WH; The output of the 1st comparator (U1) is connected with the input of the 1st inverter (U3) simultaneously, and the output of the 1st inverter (U3) then is connected with an input of OR circuit (U5); Another input of OR circuit (U5) is connected with the output of the 2nd comparator (U2), and its output is the output of the required pulse-width signal of the middle brachium pontis be made up of 3 switch element UM, VM, WM; The input of the 2nd inverter (U4) is connected with the output of the 2nd comparator (U2), and its output is the output of the required pulse-width signal of the following brachium pontis be made up of 3 switch element UL, VL, WL; 1st, the 2nd reference signal generator is controlled sine wave signal generator, and it can produce the 1st reference signal and the 2nd reference signal that is used to control the 1st three phase electric machine (2) and the 2nd three phase electric machine (3) under the control of digital signal processor (7); Carrier signal generator is controlled triangular signal generator based, and it can produce triangular signal under the control of digital signal processor (7), thereby is that the 1st comparator (U1), the 2nd comparator (U2) provide carrier signal.

5. according to claim 1ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: the model of described digital signal processor (7) is TMS320F28335.

6. according to claim 1ly be used for double cross and flow motor-driven three brachium pontis, nine switching inverters, it is characterized in that: described the 1st encoder (4) and the 2nd encoder (5) are the photoelectric type pulse coder.